diff options
author | Craig Topper <craig.topper@gmail.com> | 2013-08-25 22:23:38 +0000 |
---|---|---|
committer | Craig Topper <craig.topper@gmail.com> | 2013-08-25 22:23:38 +0000 |
commit | a4959f3f6eb9b6ab3cbbe085a2797208682e96c6 (patch) | |
tree | 0bb606cb8e2250fe925ca7af32b9b8ab1ad1a9ac /lib/Target/X86/X86InstrInfo.td | |
parent | f27c35347aa9fdd36c4ed6268380e2574ccfc87f (diff) | |
download | llvm-a4959f3f6eb9b6ab3cbbe085a2797208682e96c6.tar.gz llvm-a4959f3f6eb9b6ab3cbbe085a2797208682e96c6.tar.bz2 llvm-a4959f3f6eb9b6ab3cbbe085a2797208682e96c6.tar.xz |
First round of fixes for the x86 fixes for the x86 move accumulator from/to memory offset instructions.
-Assembly parser now properly check the size of the memory operation specified in intel syntax. So 'mov word ptr [5], al' is no longer accepted.
-x86-32 disassembly of these instructions no longer sign extends the 32-bit address immediate based on size.
-Intel syntax printing prints the ptr size and places brackets around the address immediate.
Known remaining issues with these instructions:
-Segment override prefix is not supported. PR16962 and PR16961.
-Immediate size should be changed by address size prefix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189201 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 50 |
1 files changed, 39 insertions, 11 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index f4118daa36..adad17ac8f 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -439,17 +439,45 @@ let OperandType = "OPERAND_PCREL", def i32imm_pcrel : Operand<i32>; def i16imm_pcrel : Operand<i16>; -def offset8 : Operand<i64>; -def offset16 : Operand<i64>; -def offset32 : Operand<i64>; -def offset64 : Operand<i64>; - // Branch targets have OtherVT type and print as pc-relative values. def brtarget : Operand<OtherVT>; def brtarget8 : Operand<OtherVT>; } +def X86MemOffs8AsmOperand : AsmOperandClass { + let Name = "MemOffs8"; + let SuperClasses = [X86Mem8AsmOperand]; +} +def X86MemOffs16AsmOperand : AsmOperandClass { + let Name = "MemOffs16"; + let SuperClasses = [X86Mem16AsmOperand]; +} +def X86MemOffs32AsmOperand : AsmOperandClass { + let Name = "MemOffs32"; + let SuperClasses = [X86Mem32AsmOperand]; +} +def X86MemOffs64AsmOperand : AsmOperandClass { + let Name = "MemOffs64"; + let SuperClasses = [X86Mem64AsmOperand]; +} + +let OperandType = "OPERAND_MEMORY" in { +def offset8 : Operand<i64> { + let ParserMatchClass = X86MemOffs8AsmOperand; + let PrintMethod = "printMemOffs8"; } +def offset16 : Operand<i64> { + let ParserMatchClass = X86MemOffs16AsmOperand; + let PrintMethod = "printMemOffs16"; } +def offset32 : Operand<i64> { + let ParserMatchClass = X86MemOffs32AsmOperand; + let PrintMethod = "printMemOffs32"; } +def offset64 : Operand<i64> { + let ParserMatchClass = X86MemOffs64AsmOperand; + let PrintMethod = "printMemOffs64"; } +} + + def SSECC : Operand<i8> { let PrintMethod = "printSSECC"; let OperandType = "OPERAND_IMMEDIATE"; @@ -1104,13 +1132,13 @@ def MOV32ao32 : Ii32 <0xA3, RawFrm, (outs offset32:$dst), (ins), // These forms all have full 64-bit absolute addresses in their instructions // and use the movabs mnemonic to indicate this specific form. let mayLoad = 1 in { -def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset64:$src), +def MOV64o8a : RIi64_NOREX<0xA0, RawFrm, (outs), (ins offset8:$src), "movabs{b}\t{$src, %al|al, $src}", []>, Requires<[In64BitMode]>; -def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src), +def MOV64o16a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset16:$src), "movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize, Requires<[In64BitMode]>; -def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset64:$src), +def MOV64o32a : RIi64_NOREX<0xA1, RawFrm, (outs), (ins offset32:$src), "movabs{l}\t{$src, %eax|eax, $src}", []>, Requires<[In64BitMode]>; def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src), @@ -1119,13 +1147,13 @@ def MOV64o64a : RIi64<0xA1, RawFrm, (outs), (ins offset64:$src), } let mayStore = 1 in { -def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset64:$dst), (ins), +def MOV64ao8 : RIi64_NOREX<0xA2, RawFrm, (outs offset8:$dst), (ins), "movabs{b}\t{%al, $dst|$dst, al}", []>, Requires<[In64BitMode]>; -def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins), +def MOV64ao16 : RIi64_NOREX<0xA3, RawFrm, (outs offset16:$dst), (ins), "movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize, Requires<[In64BitMode]>; -def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset64:$dst), (ins), +def MOV64ao32 : RIi64_NOREX<0xA3, RawFrm, (outs offset32:$dst), (ins), "movabs{l}\t{%eax, $dst|$dst, eax}", []>, Requires<[In64BitMode]>; def MOV64ao64 : RIi64<0xA3, RawFrm, (outs offset64:$dst), (ins), |