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| author | Craig Topper <craig.topper@gmail.com> | 2011-12-30 04:48:54 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2011-12-30 04:48:54 +0000 |
| commit | 5d1a38cbfac62f75ee22cc0c9195616ea5fe5553 (patch) | |
| tree | 8f1bb39af7d74c8327413cc876b2e63f52d993b5 /lib/Target/X86/X86InstrXOP.td | |
| parent | 4d5c4423b91caf059f335815bcc16d61632ad48a (diff) | |
| download | llvm-5d1a38cbfac62f75ee22cc0c9195616ea5fe5553.tar.gz llvm-5d1a38cbfac62f75ee22cc0c9195616ea5fe5553.tar.bz2 llvm-5d1a38cbfac62f75ee22cc0c9195616ea5fe5553.tar.xz | |
Separate the concept of having memory access in operand 4 from the concept of having the W bit set for XOP instructons. Removes ORing W-bits in the encoder and will similarly simplify the disassembler implementation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147366 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrXOP.td')
| -rw-r--r-- | lib/Target/X86/X86InstrXOP.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrXOP.td b/lib/Target/X86/X86InstrXOP.td index 64cc44d5b6..9ab5a50bd4 100644 --- a/lib/Target/X86/X86InstrXOP.td +++ b/lib/Target/X86/X86InstrXOP.td @@ -169,7 +169,7 @@ multiclass xop4op<bits<8> opc, string OpcodeStr> { (ins VR128:$src1, VR128:$src2, f128mem:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), - []>, VEX_4V, VEX_I8IMM, XOP_W; + []>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4; def mr : IXOPi8<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2, VR128:$src3), !strconcat(OpcodeStr, @@ -192,7 +192,7 @@ multiclass xop4op256<bits<8> opc, string OpcodeStr> { (ins VR256:$src1, VR256:$src2, f256mem:$src3), !strconcat(OpcodeStr, "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"), - []>, VEX_4V, VEX_I8IMM, XOP_W; + []>, VEX_4V, VEX_I8IMM, VEX_W, MemOp4; def mrY : IXOPi8<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, f256mem:$src2, VR256:$src3), !strconcat(OpcodeStr, @@ -214,7 +214,7 @@ multiclass xop5op<bits<8> opc, string OpcodeStr> { (ins VR128:$src1, VR128:$src2, f128mem:$src3, i8imm:$src4), !strconcat(OpcodeStr, "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), - []>, XOP_W; + []>, VEX_W, MemOp4; def mr : IXOP5<opc, MRMSrcMem, (outs VR128:$dst), (ins VR128:$src1, f128mem:$src2, VR128:$src3, i8imm:$src4), !strconcat(OpcodeStr, @@ -229,7 +229,7 @@ multiclass xop5op<bits<8> opc, string OpcodeStr> { (ins VR256:$src1, VR256:$src2, f256mem:$src3, i8imm:$src4), !strconcat(OpcodeStr, "\t{$src4, $src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3, $src4}"), - []>, XOP_W; + []>, VEX_W, MemOp4; def mrY : IXOP5<opc, MRMSrcMem, (outs VR256:$dst), (ins VR256:$src1, f256mem:$src2, VR256:$src3, i8imm:$src4), !strconcat(OpcodeStr, |