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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-25 19:49:33 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-05-25 19:49:33 +0000
commit4fda9670f0a9cd448d1905ab669421316b8864c5 (patch)
tree910d029c7f10e84cb691b878c4c8a18197bf3465 /lib/Target/X86/X86RegisterInfo.td
parent39e2dd7bab1925e12d4a03ae7abca0eff87274d6 (diff)
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Remove NumberHack entirely.
SubRegIndex instances are now numbered uniquely the same way Register instances are - in lexicographical order by name. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104627 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.td')
-rw-r--r--lib/Target/X86/X86RegisterInfo.td16
1 files changed, 8 insertions, 8 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 551260ffcf..7e1708661a 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -19,14 +19,14 @@
let Namespace = "X86" in {
// Subregister indices.
- def sub_8bit : SubRegIndex { let NumberHack = 1; }
- def sub_8bit_hi : SubRegIndex { let NumberHack = 2; }
- def sub_16bit : SubRegIndex { let NumberHack = 3; }
- def sub_32bit : SubRegIndex { let NumberHack = 4; }
-
- def sub_ss : SubRegIndex { let NumberHack = 1; }
- def sub_sd : SubRegIndex { let NumberHack = 2; }
- def sub_xmm : SubRegIndex { let NumberHack = 3; }
+ def sub_8bit : SubRegIndex;
+ def sub_8bit_hi : SubRegIndex;
+ def sub_16bit : SubRegIndex;
+ def sub_32bit : SubRegIndex;
+
+ def sub_ss : SubRegIndex;
+ def sub_sd : SubRegIndex;
+ def sub_xmm : SubRegIndex;
// In the register alias definitions below, we define which registers alias