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author | Andrew Trick <atrick@apple.com> | 2013-04-02 01:58:47 +0000 |
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committer | Andrew Trick <atrick@apple.com> | 2013-04-02 01:58:47 +0000 |
commit | 92142b327598822fdbeb386e5a5b68ec963be4ad (patch) | |
tree | 09c98f467ab3ed3a53502cc43b242d6493ad4ee6 /lib/Target/X86/X86SchedHaswell.td | |
parent | 080e3c523e87ec68ca1ea5db4cd49816028dd8bd (diff) | |
download | llvm-92142b327598822fdbeb386e5a5b68ec963be4ad.tar.gz llvm-92142b327598822fdbeb386e5a5b68ec963be4ad.tar.bz2 llvm-92142b327598822fdbeb386e5a5b68ec963be4ad.tar.xz |
The divide unit is not pipeline, but it is still buffered.
Buffered means a later divide may be executed out-of-order while a
prior divide is sitting (buffered) in a reservation station.
You can tell it's not pipelined, because operations that use it
reserve it for more than one cycle:
def : WriteRes<WriteIDiv, [HWPort0, HWDivider]> {
let Latency = 25;
let ResourceCycles = [1, 10];
}
We don't currently distinguish between an unpipeline operation and one
that is split into multiple micro-ops requiring the same unit. Except
that the later may have NumMicroOps > 1 if they also consume
issue/dispatch resources.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86SchedHaswell.td')
-rw-r--r-- | lib/Target/X86/X86SchedHaswell.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86SchedHaswell.td b/lib/Target/X86/X86SchedHaswell.td index b3eb460d3c..7de6791f2e 100644 --- a/lib/Target/X86/X86SchedHaswell.td +++ b/lib/Target/X86/X86SchedHaswell.td @@ -50,8 +50,8 @@ def HWPort15 : ProcResGroup<[HWPort1, HWPort5]>; def HWPort015 : ProcResGroup<[HWPort0, HWPort1, HWPort5]>; def HWPort0156: ProcResGroup<[HWPort0, HWPort1, HWPort5, HWPort6]>; -// Integer division issued on port 0, but uses the non-pipelined divider. -def HWDivider : ProcResource<1> { let Buffered = 0; } +// Integer division issued on port 0. +def HWDivider : ProcResource<1>; // Loads are 4 cycles, so ReadAfterLd registers needn't be available until 4 // cycles after the memory operand. |