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authorMichael Liao <michael.liao@intel.com>2013-03-26 17:47:11 +0000
committerMichael Liao <michael.liao@intel.com>2013-03-26 17:47:11 +0000
commit675eb3b9ac547119f6db676ebdd172d40a797b1c (patch)
tree4f13b3e2e5500e67183794bd4f1409ccd12b04d9 /lib/Target/X86/X86Subtarget.cpp
parent30ebb962b6fe110514917f31522a81f2c6d914ba (diff)
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Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Subtarget.cpp')
-rw-r--r--lib/Target/X86/X86Subtarget.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index 0f2c008ab9..1a7c2c29eb 100644
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -283,6 +283,10 @@ void X86Subtarget::AutoDetectSubtargetFeatures() {
HasLZCNT = true;
ToggleFeature(X86::FeatureLZCNT);
}
+ if (IsIntel && ((ECX >> 8) & 0x1)) {
+ HasPRFCHW = true;
+ ToggleFeature(X86::FeaturePRFCHW);
+ }
if (IsAMD) {
if ((ECX >> 6) & 0x1) {
HasSSE4A = true;
@@ -440,6 +444,7 @@ void X86Subtarget::initializeEnvironment() {
HasBMI2 = false;
HasRTM = false;
HasADX = false;
+ HasPRFCHW = false;
IsBTMemSlow = false;
IsUAMemFast = false;
HasVectorUAMem = false;