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| author | Michael Liao <michael.liao@intel.com> | 2013-03-26 17:47:11 +0000 |
|---|---|---|
| committer | Michael Liao <michael.liao@intel.com> | 2013-03-26 17:47:11 +0000 |
| commit | 675eb3b9ac547119f6db676ebdd172d40a797b1c (patch) | |
| tree | 4f13b3e2e5500e67183794bd4f1409ccd12b04d9 /lib/Target/X86/X86Subtarget.h | |
| parent | 30ebb962b6fe110514917f31522a81f2c6d914ba (diff) | |
| download | llvm-675eb3b9ac547119f6db676ebdd172d40a797b1c.tar.gz llvm-675eb3b9ac547119f6db676ebdd172d40a797b1c.tar.bz2 llvm-675eb3b9ac547119f6db676ebdd172d40a797b1c.tar.xz | |
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Subtarget.h')
| -rw-r--r-- | lib/Target/X86/X86Subtarget.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index e97da4b6f4..b9f29fdcee 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -124,6 +124,9 @@ protected: /// HasADX - Processor has ADX instructions. bool HasADX; + /// HasPRFCHW - Processor has PRFCHW instructions. + bool HasPRFCHW; + /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow. bool IsBTMemSlow; @@ -254,6 +257,7 @@ public: bool hasBMI2() const { return HasBMI2; } bool hasRTM() const { return HasRTM; } bool hasADX() const { return HasADX; } + bool hasPRFCHW() const { return HasPRFCHW; } bool isBTMemSlow() const { return IsBTMemSlow; } bool isUnalignedMemAccessFast() const { return IsUAMemFast; } bool hasVectorUAMem() const { return HasVectorUAMem; } |