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authorDan Gohman <gohman@apple.com>2010-07-10 09:00:22 +0000
committerDan Gohman <gohman@apple.com>2010-07-10 09:00:22 +0000
commit84023e0fbefc406a4c611d3d64a10df5d3a97dd7 (patch)
tree8f47ad9a2c30661cf7b3e3f5bbe5fe195a8a44f8 /lib/Target/X86/X86TargetMachine.cpp
parentd737fcafc4cedcbe798930d96203a9e22c1e6e68 (diff)
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Reapply bottom-up fast-isel, with several fixes for x86-32:
- Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108039 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86TargetMachine.cpp')
-rw-r--r--lib/Target/X86/X86TargetMachine.cpp4
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index a0d7cf6619..df00d3ffcc 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -173,6 +173,10 @@ bool X86TargetMachine::addInstSelector(PassManagerBase &PM,
// Install an instruction selector.
PM.add(createX86ISelDag(*this, OptLevel));
+ // For 32-bit, prepend instructions to set the "global base reg" for PIC.
+ if (!Subtarget.is64Bit())
+ PM.add(createGlobalBaseRegPass());
+
return false;
}