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| author | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-20 07:30:17 +0000 |
| commit | 420761a0f193e87d08ee1c51b26bba23ab4bac7f (patch) | |
| tree | 55aa0936b18927fe72fb4806eeab177b42c2f9cd /lib/Target/XCore/XCoreISelLowering.cpp | |
| parent | c909950c384e8234a7b3c5a76b7f79e3f7012ceb (diff) | |
| download | llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.gz llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.bz2 llvm-420761a0f193e87d08ee1c51b26bba23ab4bac7f.tar.xz | |
Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155188 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreISelLowering.cpp')
| -rw-r--r-- | lib/Target/XCore/XCoreISelLowering.cpp | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index fdf2b78324..ee4ba10912 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -66,7 +66,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) Subtarget(*XTM.getSubtargetImpl()) { // Set up the register classes. - addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); + addRegisterClass(MVT::i32, &XCore::GRRegsRegClass); // Compute derived properties from the register classes computeRegisterProperties(); @@ -1121,8 +1121,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, llvm_unreachable(0); } case MVT::i32: - unsigned VReg = RegInfo.createVirtualRegister( - XCore::GRRegsRegisterClass); + unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT)); } @@ -1172,8 +1171,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, offset -= StackSlotSize; SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); // Move argument from phys reg -> virt reg - unsigned VReg = RegInfo.createVirtualRegister( - XCore::GRRegsRegisterClass); + unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); RegInfo.addLiveIn(ArgRegs[i], VReg); SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); // Move argument from virt reg -> stack @@ -1611,7 +1609,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, switch (Constraint[0]) { default : break; case 'r': - return std::make_pair(0U, XCore::GRRegsRegisterClass); + return std::make_pair(0U, &XCore::GRRegsRegClass); } } // Use the default implementation in TargetLowering to convert the register |