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authorTorok Edwin <edwintorok@gmail.com>2009-07-14 16:55:14 +0000
committerTorok Edwin <edwintorok@gmail.com>2009-07-14 16:55:14 +0000
commitc23197a26f34f559ea9797de51e187087c039c42 (patch)
treebf497ec9a02cd2fc0b64e3e58eff037a719a854d /lib/Target/XCore/XCoreInstrInfo.cpp
parent1f316e321a8f2fa0e193c5444584a67a8aabe9a8 (diff)
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llvm_unreachable->llvm_unreachable(0), LLVM_UNREACHABLE->llvm_unreachable.
This adds location info for all llvm_unreachable calls (which is a macro now) in !NDEBUG builds. In NDEBUG builds location info and the message is off (it only prints "UREACHABLE executed"). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75640 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.cpp')
-rw-r--r--lib/Target/XCore/XCoreInstrInfo.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.cpp b/lib/Target/XCore/XCoreInstrInfo.cpp
index ea35504766..ad47ac2665 100644
--- a/lib/Target/XCore/XCoreInstrInfo.cpp
+++ b/lib/Target/XCore/XCoreInstrInfo.cpp
@@ -187,7 +187,7 @@ static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc)
static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::BRFT_lru6;
case XCore::COND_FALSE : return XCore::BRFF_lru6;
}
@@ -198,7 +198,7 @@ static inline unsigned GetCondBranchFromCond(XCore::CondCode CC)
static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC)
{
switch (CC) {
- default: LLVM_UNREACHABLE("Illegal condition code!");
+ default: llvm_unreachable("Illegal condition code!");
case XCore::COND_TRUE : return XCore::COND_FALSE;
case XCore::COND_FALSE : return XCore::COND_TRUE;
}
@@ -408,7 +408,7 @@ void XCoreInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented");
+ llvm_unreachable("unimplemented");
}
void XCoreInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
@@ -428,7 +428,7 @@ void XCoreInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const
{
- LLVM_UNREACHABLE("unimplemented");
+ llvm_unreachable("unimplemented");
}
bool XCoreInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,