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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-13 20:44:29 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2012-07-13 20:44:29 +0000 |
| commit | 68c10a2ff74fe882cfd789983b2d0f12e42fb0ec (patch) | |
| tree | 2eb1c748a9019ff5f8f2330d9db3c6a15e8af670 /lib/Target/XCore/XCoreInstrInfo.td | |
| parent | 135fb455b72b1db12d93aa13b13872780db6315b (diff) | |
| download | llvm-68c10a2ff74fe882cfd789983b2d0f12e42fb0ec.tar.gz llvm-68c10a2ff74fe882cfd789983b2d0f12e42fb0ec.tar.bz2 llvm-68c10a2ff74fe882cfd789983b2d0f12e42fb0ec.tar.xz | |
Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.td')
| -rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index b2f0603776..f6f15309ec 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -741,14 +741,12 @@ let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { def BL_u10 : _FU10< - (outs), - (ins calltarget:$target, variable_ops), + (outs), (ins calltarget:$target), "bl $target", [(XCoreBranchLink immU10:$target)]>; def BL_lu10 : _FLU10< - (outs), - (ins calltarget:$target, variable_ops), + (outs), (ins calltarget:$target), "bl $target", [(XCoreBranchLink immU20:$target)]>; } @@ -988,7 +986,7 @@ def ECALLF_1r : _F1R<(outs), (ins GRRegs:$src), let isCall=1, // All calls clobber the link register and the non-callee-saved registers: Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in { -def BLA_1r : _F1R<(outs), (ins GRRegs:$addr, variable_ops), +def BLA_1r : _F1R<(outs), (ins GRRegs:$addr), "bla $addr", [(XCoreBranchLink GRRegs:$addr)]>; } |