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author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:06:00 +0000 |
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committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:06:00 +0000 |
commit | 8c993e1632383a7cc6793568be43fdd6f626a8c6 (patch) | |
tree | 9669c0302d286bf19f5a974cb52fae7acaefd7ea /lib/Target | |
parent | 25af73303f13357d18b0f33af44c2895438ad9c5 (diff) | |
download | llvm-8c993e1632383a7cc6793568be43fdd6f626a8c6.tar.gz llvm-8c993e1632383a7cc6793568be43fdd6f626a8c6.tar.bz2 llvm-8c993e1632383a7cc6793568be43fdd6f626a8c6.tar.xz |
Provide proper patterns for and with imm instructions. Tune the tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75979 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 256 | ||||
-rw-r--r-- | lib/Target/SystemZ/SystemZOperands.td | 274 |
2 files changed, 289 insertions, 241 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index e91a66e8b7..49fd403a18 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -61,224 +61,8 @@ def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond, def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>; def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>; -//===----------------------------------------------------------------------===// -// Instruction Pattern Stuff. -//===----------------------------------------------------------------------===// - -// SystemZ specific condition code. These correspond to CondCode in -// SystemZ.h. They must be kept in synch. -def SYSTEMZ_COND_E : PatLeaf<(i8 0)>; -def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>; -def SYSTEMZ_COND_H : PatLeaf<(i8 2)>; -def SYSTEMZ_COND_L : PatLeaf<(i8 3)>; -def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>; -def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>; - -def LL16 : SDNodeXForm<imm, [{ - // Transformation function: return low 16 bits. - return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL); -}]>; - -def LH16 : SDNodeXForm<imm, [{ - // Transformation function: return bits 16-31. - return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16); -}]>; - -def HL16 : SDNodeXForm<imm, [{ - // Transformation function: return bits 32-47. - return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32); -}]>; - -def HH16 : SDNodeXForm<imm, [{ - // Transformation function: return bits 48-63. - return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48); -}]>; - -def LO32 : SDNodeXForm<imm, [{ - // Transformation function: return low 32 bits. - return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL); -}]>; - -def HI32 : SDNodeXForm<imm, [{ - // Transformation function: return bits 32-63. - return getI32Imm(N->getZExtValue() >> 32); -}]>; - -def i32ll16 : PatLeaf<(i32 imm), [{ - // i32ll16 predicate - true if the 32-bit immediate has only rightmost 16 - // bits set. - return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); -}], LL16>; - -def i32lh16 : PatLeaf<(i32 imm), [{ - // i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set. - return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); -}], LH16>; - -def i64ll16 : PatLeaf<(imm), [{ - // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16 - // bits set. - return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); -}], LL16>; - -def i64lh16 : PatLeaf<(imm), [{ - // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set. - return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); -}], LH16>; - -def i64hl16 : PatLeaf<(i64 imm), [{ - // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set. - return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue()); -}], HL16>; - -def i64hh16 : PatLeaf<(i64 imm), [{ - // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set. - return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue()); -}], HH16>; - -def immSExt16 : PatLeaf<(imm), [{ - // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended - // field. - if (N->getValueType(0) == MVT::i64) { - uint64_t val = N->getZExtValue(); - return ((int64_t)val == (int16_t)val); - } else if (N->getValueType(0) == MVT::i32) { - uint32_t val = N->getZExtValue(); - return ((int32_t)val == (int16_t)val); - } - - return false; -}]>; - -def immSExt32 : PatLeaf<(i64 imm), [{ - // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended - // field. - uint64_t val = N->getZExtValue(); - return ((int64_t)val == (int32_t)val); -}]>; - -def i64lo32 : PatLeaf<(i64 imm), [{ - // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32 - // bits set. - return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue()); -}], LO32>; - -def i64hi32 : PatLeaf<(i64 imm), [{ - // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set. - return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue()); -}], HI32>; - -def i32immSExt8 : PatLeaf<(i32 imm), [{ - // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit - // sign extended field. - return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); -}]>; - -def i32immSExt16 : PatLeaf<(i32 imm), [{ - // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit - // sign extended field. - return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue(); -}]>; - -def i64immSExt32 : PatLeaf<(i64 imm), [{ - // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit - // sign extended field. - return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue(); -}]>; - -def i64immZExt32 : PatLeaf<(i64 imm), [{ - // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit - // zero extended field. - return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue(); -}]>; - -// extloads -def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; -def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; -def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; -def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; -def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; - -def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; -def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; -def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; -def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; -def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; - -def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; -def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; -def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; -def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; -def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; - -// A couple of more descriptive operand definitions. -// 32-bits but only 8 bits are significant. -def i32i8imm : Operand<i32>; -// 32-bits but only 16 bits are significant. -def i32i16imm : Operand<i32>; -// 64-bits but only 32 bits are significant. -def i64i32imm : Operand<i64>; -// Branch targets have OtherVT type. -def brtarget : Operand<OtherVT>; - -// Unigned i12 -def u12imm : Operand<i32> { - let PrintMethod = "printU16ImmOperand"; -} -// Signed i16 -def s16imm : Operand<i32> { - let PrintMethod = "printS16ImmOperand"; -} -def s16imm64 : Operand<i64> { - let PrintMethod = "printS16ImmOperand"; -} -// Signed i20 -def s20imm : Operand<i32> { - let PrintMethod = "printS20ImmOperand"; -} -def s20imm64 : Operand<i64> { - let PrintMethod = "printS20ImmOperand"; -} -// Signed i32 -def s32imm : Operand<i32> { - let PrintMethod = "printS32ImmOperand"; -} -def s32imm64 : Operand<i64> { - let PrintMethod = "printS32ImmOperand"; -} -//===----------------------------------------------------------------------===// -// SystemZ Operand Definitions. -//===----------------------------------------------------------------------===// - -// Address operands - -// riaddr := reg + imm -def riaddr32 : Operand<i32>, - ComplexPattern<i32, 2, "SelectAddrRI32", []> { - let PrintMethod = "printRIAddrOperand"; - let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp); -} - -def riaddr : Operand<i64>, - ComplexPattern<i64, 2, "SelectAddrRI", []> { - let PrintMethod = "printRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp); -} - -//===----------------------------------------------------------------------===// - -// rriaddr := reg + reg + imm -def rriaddr : Operand<i64>, - ComplexPattern<i64, 3, "SelectAddrRRI", [], []> { - let PrintMethod = "printRRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); -} -def laaddr : Operand<i64>, - ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> { - let PrintMethod = "printRRIAddrOperand"; - let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); -} +include "SystemZOperands.td" //===----------------------------------------------------------------------===// // Instruction list.. @@ -602,38 +386,36 @@ def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), // FIXME: Provide proper encoding! // FIXME: Compute masked bits properly! -/* def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "nill\t{$dst, $src2}", - [(set GR32:$dst, (and GR32:$src1, i32ll16:$src2))]>; + [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>; def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nill\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64ll16:$src2))]>; + [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>; def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "nilh\t{$dst, $src2}", - [(set GR32:$dst, (and GR32:$src1, i32lh16:$src2))]>; + [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>; def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nilh\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64lh16:$src2))]>; + [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>; def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nihl\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64hl16:$src2))]>; + [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>; def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nihh\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64hh16:$src2))]>; -*/ + [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>; + def AND32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "nilf\t{$dst, $src2}", [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>; -/*def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), +def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nilf\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64lo32:$src2))]>; + [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>; def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), "nihf\t{$dst, $src2}", - [(set GR64:$dst, (and GR64:$src1, i64hi32:$src2))]>; -*/ + [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>; let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y // FIXME: Provide proper encoding! @@ -645,12 +427,12 @@ def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2), [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>; } -def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), +def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "oill\t{$dst, $src2}", - [(set GR32:$dst, (or GR32:$src1, i64ll16:$src2))]>; -def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i16imm:$src2), + [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>; +def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "oilh\t{$dst, $src2}", - [(set GR32:$dst, (or GR32:$src1, i64lh16:$src2))]>; + [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>; def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "oilf\t{$dst, $src2}", [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>; @@ -698,14 +480,6 @@ def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), "xilf\t{$dst, $src2}", [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>; -// FIXME: these 2 instructions seem to require extimm facility -def XOR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), - "xilf\t{$dst, $src2}", - [(set GR64:$dst, (xor GR64:$src1, i64lo32:$src2))]>; -def XOR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2), - "xihf\t{$dst, $src2}", - [(set GR64:$dst, (xor GR64:$src1, i64hi32:$src2))]>; - } // Defs = [PSW] let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td new file mode 100644 index 0000000000..446e426abf --- /dev/null +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -0,0 +1,274 @@ +//=====- SystemZOperands.td - SystemZ Operands defs ---------*- tblgen-*-=====// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the various SystemZ instruction operands. +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Instruction Pattern Stuff. +//===----------------------------------------------------------------------===// + +// SystemZ specific condition code. These correspond to CondCode in +// SystemZ.h. They must be kept in synch. +def SYSTEMZ_COND_E : PatLeaf<(i8 0)>; +def SYSTEMZ_COND_NE : PatLeaf<(i8 1)>; +def SYSTEMZ_COND_H : PatLeaf<(i8 2)>; +def SYSTEMZ_COND_L : PatLeaf<(i8 3)>; +def SYSTEMZ_COND_HE : PatLeaf<(i8 4)>; +def SYSTEMZ_COND_LE : PatLeaf<(i8 5)>; + +def LL16 : SDNodeXForm<imm, [{ + // Transformation function: return low 16 bits. + return getI16Imm(N->getZExtValue() & 0x000000000000FFFFULL); +}]>; + +def LH16 : SDNodeXForm<imm, [{ + // Transformation function: return bits 16-31. + return getI16Imm((N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16); +}]>; + +def HL16 : SDNodeXForm<imm, [{ + // Transformation function: return bits 32-47. + return getI16Imm((N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32); +}]>; + +def HH16 : SDNodeXForm<imm, [{ + // Transformation function: return bits 48-63. + return getI16Imm((N->getZExtValue() & 0xFFFF000000000000ULL) >> 48); +}]>; + +def LO32 : SDNodeXForm<imm, [{ + // Transformation function: return low 32 bits. + return getI32Imm(N->getZExtValue() & 0x00000000FFFFFFFFULL); +}]>; + +def HI32 : SDNodeXForm<imm, [{ + // Transformation function: return bits 32-63. + return getI32Imm(N->getZExtValue() >> 32); +}]>; + +def i32ll16 : PatLeaf<(i32 imm), [{ + // i32ll16 predicate - true if the 32-bit immediate has only rightmost 16 + // bits set. + return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); +}], LL16>; + +def i32lh16 : PatLeaf<(i32 imm), [{ + // i32lh16 predicate - true if the 32-bit immediate has only bits 16-31 set. + return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); +}], LH16>; + +def i32ll16c : PatLeaf<(i32 imm), [{ + // i32ll16c predicate - true if the 32-bit immediate has all bits 16-31 set. + return ((N->getZExtValue() | 0x00000000FFFF0000ULL) == N->getZExtValue()); +}], LL16>; + +def i32lh16c : PatLeaf<(i32 imm), [{ + // i32lh16c predicate - true if the 32-bit immediate has all rightmost 16 + // bits set. + return ((N->getZExtValue() | 0x000000000000FFFFULL) == N->getZExtValue()); +}], LH16>; + +def i64ll16 : PatLeaf<(i64 imm), [{ + // i64ll16 predicate - true if the 64-bit immediate has only rightmost 16 + // bits set. + return ((N->getZExtValue() & 0x000000000000FFFFULL) == N->getZExtValue()); +}], LL16>; + +def i64lh16 : PatLeaf<(i64 imm), [{ + // i64lh16 predicate - true if the 64-bit immediate has only bits 16-31 set. + return ((N->getZExtValue() & 0x00000000FFFF0000ULL) == N->getZExtValue()); +}], LH16>; + +def i64hl16 : PatLeaf<(i64 imm), [{ + // i64hl16 predicate - true if the 64-bit immediate has only bits 32-47 set. + return ((N->getZExtValue() & 0x0000FFFF00000000ULL) == N->getZExtValue()); +}], HL16>; + +def i64hh16 : PatLeaf<(i64 imm), [{ + // i64hh16 predicate - true if the 64-bit immediate has only bits 48-63 set. + return ((N->getZExtValue() & 0xFFFF000000000000ULL) == N->getZExtValue()); +}], HH16>; + +def i64ll16c : PatLeaf<(i64 imm), [{ + // i64ll16c predicate - true if the 64-bit immediate has only rightmost 16 + // bits set. + return ((N->getZExtValue() | 0xFFFFFFFFFFFF0000ULL) == N->getZExtValue()); +}], LL16>; + +def i64lh16c : PatLeaf<(i64 imm), [{ + // i64lh16c predicate - true if the 64-bit immediate has only bits 16-31 set. + return ((N->getZExtValue() | 0xFFFFFFFF0000FFFFULL) == N->getZExtValue()); +}], LH16>; + +def i64hl16c : PatLeaf<(i64 imm), [{ + // i64hl16c predicate - true if the 64-bit immediate has only bits 32-47 set. + return ((N->getZExtValue() | 0xFFFF0000FFFFFFFFULL) == N->getZExtValue()); +}], HL16>; + +def i64hh16c : PatLeaf<(i64 imm), [{ + // i64hh16c predicate - true if the 64-bit immediate has only bits 48-63 set. + return ((N->getZExtValue() | 0x0000FFFFFFFFFFFFULL) == N->getZExtValue()); +}], HH16>; + +def immSExt16 : PatLeaf<(imm), [{ + // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended + // field. + if (N->getValueType(0) == MVT::i64) { + uint64_t val = N->getZExtValue(); + return ((int64_t)val == (int16_t)val); + } else if (N->getValueType(0) == MVT::i32) { + uint32_t val = N->getZExtValue(); + return ((int32_t)val == (int16_t)val); + } + + return false; +}]>; + +def immSExt32 : PatLeaf<(i64 imm), [{ + // immSExt32 predicate - true if the immediate fits in a 32-bit sign extended + // field. + uint64_t val = N->getZExtValue(); + return ((int64_t)val == (int32_t)val); +}]>; + +def i64lo32 : PatLeaf<(i64 imm), [{ + // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32 + // bits set. + return ((N->getZExtValue() & 0x00000000FFFFFFFFULL) == N->getZExtValue()); +}], LO32>; + +def i64hi32 : PatLeaf<(i64 imm), [{ + // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set. + return ((N->getZExtValue() & 0xFFFFFFFF00000000ULL) == N->getZExtValue()); +}], HI32>; + +def i64lo32c : PatLeaf<(i64 imm), [{ + // i64lo32 predicate - true if the 64-bit immediate has only rightmost 32 + // bits set. + return ((N->getZExtValue() | 0xFFFFFFFF00000000ULL) == N->getZExtValue()); +}], LO32>; + +def i64hi32c : PatLeaf<(i64 imm), [{ + // i64hi32 predicate - true if the 64-bit immediate has only bits 32-63 set. + return ((N->getZExtValue() | 0x00000000FFFFFFFFULL) == N->getZExtValue()); +}], HI32>; + +def i32immSExt8 : PatLeaf<(i32 imm), [{ + // i32immSExt8 predicate - True if the 32-bit immediate fits in a 8-bit + // sign extended field. + return (int32_t)N->getZExtValue() == (int8_t)N->getZExtValue(); +}]>; + +def i32immSExt16 : PatLeaf<(i32 imm), [{ + // i32immSExt16 predicate - True if the 32-bit immediate fits in a 16-bit + // sign extended field. + return (int32_t)N->getZExtValue() == (int16_t)N->getZExtValue(); +}]>; + +def i64immSExt32 : PatLeaf<(i64 imm), [{ + // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit + // sign extended field. + return (int64_t)N->getZExtValue() == (int32_t)N->getZExtValue(); +}]>; + +def i64immZExt32 : PatLeaf<(i64 imm), [{ + // i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit + // zero extended field. + return (uint64_t)N->getZExtValue() == (uint32_t)N->getZExtValue(); +}]>; + +// extloads +def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; +def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; +def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; +def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; +def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (extloadi32 node:$ptr))>; + +def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; +def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; +def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; +def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; +def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; + +def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; +def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; +def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; +def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; +def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; + +// A couple of more descriptive operand definitions. +// 32-bits but only 8 bits are significant. +def i32i8imm : Operand<i32>; +// 32-bits but only 16 bits are significant. +def i32i16imm : Operand<i32>; +// 64-bits but only 32 bits are significant. +def i64i32imm : Operand<i64>; +// Branch targets have OtherVT type. +def brtarget : Operand<OtherVT>; + +// Unigned i12 +def u12imm : Operand<i32> { + let PrintMethod = "printU16ImmOperand"; +} +// Signed i16 +def s16imm : Operand<i32> { + let PrintMethod = "printS16ImmOperand"; +} +def s16imm64 : Operand<i64> { + let PrintMethod = "printS16ImmOperand"; +} +// Signed i20 +def s20imm : Operand<i32> { + let PrintMethod = "printS20ImmOperand"; +} +def s20imm64 : Operand<i64> { + let PrintMethod = "printS20ImmOperand"; +} +// Signed i32 +def s32imm : Operand<i32> { + let PrintMethod = "printS32ImmOperand"; +} +def s32imm64 : Operand<i64> { + let PrintMethod = "printS32ImmOperand"; +} + +//===----------------------------------------------------------------------===// +// SystemZ Operand Definitions. +//===----------------------------------------------------------------------===// + +// Address operands + +// riaddr := reg + imm +def riaddr32 : Operand<i32>, + ComplexPattern<i32, 2, "SelectAddrRI32", []> { + let PrintMethod = "printRIAddrOperand"; + let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp); +} + +def riaddr : Operand<i64>, + ComplexPattern<i64, 2, "SelectAddrRI", []> { + let PrintMethod = "printRIAddrOperand"; + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp); +} + +//===----------------------------------------------------------------------===// + +// rriaddr := reg + reg + imm +def rriaddr : Operand<i64>, + ComplexPattern<i64, 3, "SelectAddrRRI", [], []> { + let PrintMethod = "printRRIAddrOperand"; + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); +} +def laaddr : Operand<i64>, + ComplexPattern<i64, 3, "SelectLAAddr", [add, sub, or, frameindex], []> { + let PrintMethod = "printRRIAddrOperand"; + let MIOperandInfo = (ops ADDR64:$base, s20imm64:$disp, ADDR64:$index); +} |