rename TargetInstrDescriptor -> TargetInstrDesc.

Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695 91177308-0d34-0410-b5e6-96231b3b80d8

17 files changed, 81 insertions, 84 deletions

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 62d4da4b51..2105f14d3a 100644
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -55,7 +55,7 @@ namespace {
 
     void emitInstruction(const MachineInstr &MI);
     int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
-    unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+    unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
     unsigned getBinaryCodeForInstr(const MachineInstr &MI);
 
     void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
@@ -103,8 +103,8 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
 }
 
 /// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
-  return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
+  return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
 }
 
 /// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
@@ -201,15 +201,15 @@ void Emitter::emitInstruction(const MachineInstr &MI) {
 }
 
 unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
-  const TargetInstrDescriptor *Desc = MI.getDesc();
-  unsigned opcode = Desc->Opcode;
+  const TargetInstrDesc &Desc = MI.getDesc();
+  unsigned opcode = Desc.Opcode;
   // initial instruction mask
   unsigned Value = 0xE0000000;
   unsigned op;
 
-  switch (Desc->TSFlags & ARMII::AddrModeMask) {
+  switch (Desc.TSFlags & ARMII::AddrModeMask) {
   case ARMII::AddrModeNone: {
-    switch(Desc->TSFlags & ARMII::FormMask) {
+    switch(Desc.TSFlags & ARMII::FormMask) {
     default: {
       assert(0 && "Unknown instruction subtype!");
       // treat special instruction CLZ
@@ -241,7 +241,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
       unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
       Value |= BaseOpcode << 4;
 
-      unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+      unsigned Format = (Desc.TSFlags & ARMII::FormMask);
       if (Format == ARMII::MulSMUL)
         Value |= 1 << 22;
 
@@ -342,7 +342,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
 
     // treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
     // MOVrx.
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     if (Format == ARMII::DPRdMisc) {
       Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
       Value |= getMachineOpValue(MI,1);
@@ -499,7 +499,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     // bit 26 is always 1
     Value |= 1 << 26;
 
-    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
     // if the instruction uses offset addressing or pre-indexed addressing,
     // set bit P(24) to 1
     if (Index == ARMII::IndexModePre || Index == 0)
@@ -508,7 +508,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     if (Index == ARMII::IndexModePre)
       Value |= 1 << 21;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // If it is a load instruction (except LDRD), set bit L(20) to 1
     if (Format == ARMII::LdFrm)
       Value |= 1 << ARMII::L_BitShift;
@@ -555,14 +555,13 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     break;
   }
   case ARMII::AddrMode3: {
-
-    unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+    unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
     // if the instruction uses offset addressing or pre-indexed addressing,
     // set bit P(24) to 1
     if (Index == ARMII::IndexModePre || Index == 0)
       Value |= 1 << ARMII::IndexShift;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // If it is a load instruction (except LDRD), set bit L(20) to 1
     if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
       Value |= 1 << ARMII::L_BitShift;
@@ -607,7 +606,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
     // bit 27 is always 1
     Value |= 1 << 27;
 
-    unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+    unsigned Format = Desc.TSFlags & ARMII::FormMask;
     // if it is a load instr, set bit L(20) to 1
     if (Format == ARMII::LdFrm)
       Value |= 1 << ARMII::L_BitShift;
diff --git a/lib/Target/ARM/ARMConstantIslandPass.cpp b/lib/Target/ARM/ARMConstantIslandPass.cpp
index 5f54e1f656..ea1ee9e39d 100644
--- a/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ b/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -371,7 +371,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
       MBBSize += ARM::GetInstSize(I);
 
       int Opc = I->getOpcode();
-      if (I->getDesc()->isBranch()) {
+      if (I->getDesc().isBranch()) {
         bool isCond = false;
         unsigned Bits = 0;
         unsigned Scale = 1;
@@ -423,7 +423,7 @@ void ARMConstantIslands::InitialFunctionScan(MachineFunction &Fn,
           // Basic size info comes from the TSFlags field.
           unsigned Bits = 0;
           unsigned Scale = 1;
-          unsigned TSFlags = I->getDesc()->TSFlags;
+          unsigned TSFlags = I->getDesc().TSFlags;
           switch (TSFlags & ARMII::AddrModeMask) {
           default: 
             // Constant pool entries can reach anything.
diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index 2e9d802d70..513f9ecef2 100644
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -63,7 +63,7 @@ bool ARMInstrInfo::isMoveInstr(const MachineInstr &MI,
     return true;
   case ARM::MOVr:
   case ARM::tMOVr:
-    assert(MI.getDesc()->getNumOperands() >= 2 &&
+    assert(MI.getDesc().getNumOperands() >= 2 &&
            MI.getOperand(0).isRegister() &&
            MI.getOperand(1).isRegister() &&
            "Invalid ARM MOV instruction");
@@ -180,7 +180,7 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
     return NULL;
 
   MachineInstr *MI = MBBI;
-  unsigned TSFlags = MI->getDesc()->TSFlags;
+  unsigned TSFlags = MI->getDesc().TSFlags;
   bool isPre = false;
   switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
   default: return NULL;
@@ -200,9 +200,9 @@ ARMInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
   MachineInstr *UpdateMI = NULL;
   MachineInstr *MemMI = NULL;
   unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned NumOps = TID->getNumOperands();
-  bool isLoad = TID->isSimpleLoad();
+  const TargetInstrDesc &TID = MI->getDesc();
+  unsigned NumOps = TID.getNumOperands();
+  bool isLoad = TID.isSimpleLoad();
   const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
   const MachineOperand &Base = MI->getOperand(2);
   const MachineOperand &Offset = MI->getOperand(NumOps-3);
@@ -837,8 +837,8 @@ ARMInstrInfo::SubsumesPredicate(const std::vector<MachineOperand> &Pred1,
 
 bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
                                     std::vector<MachineOperand> &Pred) const {
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
     return false;
 
   bool Found = false;
@@ -870,8 +870,8 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
   const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
 
   // Basic size info comes from the TSFlags field.
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  unsigned TSFlags = TID->TSFlags;
+  const TargetInstrDesc &TID = MI->getDesc();
+  unsigned TSFlags = TID.TSFlags;
   
   switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
   default:
@@ -897,9 +897,9 @@ unsigned ARM::GetInstSize(MachineInstr *MI) {
     case ARM::tBR_JTr: {
       // These are jumptable branches, i.e. a branch followed by an inlined
       // jumptable. The size is 4 + 4 * number of entries.
-      unsigned NumOps = TID->getNumOperands();
+      unsigned NumOps = TID.getNumOperands();
       MachineOperand JTOP =
-        MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
+        MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
       unsigned JTI = JTOP.getIndex();
       MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
       const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
diff --git a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index 29da83d9d9..347ed8b326 100644
--- a/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -599,8 +599,8 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
       unsigned Base = MBBI->getOperand(1).getReg();
       unsigned PredReg = 0;
       ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
-      const TargetInstrDescriptor *TID = MBBI->getDesc();
-      unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
+      unsigned NumOperands = MBBI->getDesc().getNumOperands();
+      unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
       int Offset = isAM2
         ? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
       if (isAM2) {
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index fc721329f4..01d08414b2 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -581,7 +581,7 @@ void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   }
 
   unsigned Opcode = MI.getOpcode();
-  const TargetInstrDescriptor &Desc = *MI.getDesc();
+  const TargetInstrDesc &Desc = MI.getDesc();
   unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
   bool isSub = false;
 
@@ -1036,7 +1036,7 @@ ARMRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
           for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
             if (I->getOperand(i).isFrameIndex()) {
               unsigned Opcode = I->getOpcode();
-              const TargetInstrDescriptor &Desc = TII.get(Opcode);
+              const TargetInstrDesc &Desc = TII.get(Opcode);
               unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
               if (AddrMode == ARMII::AddrMode3) {
                 Limit = (1 << 8) - 1;
diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp
index c3f92f842c..881cd12929 100644
--- a/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -59,7 +59,7 @@ runOnMachineBasicBlock(MachineBasicBlock &MBB)
 {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (I->getDesc()->hasDelaySlot()) {
+    if (I->getDesc().hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
       BuildMI(MBB, J, TII->get(Mips::NOP));
diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 8896b35aed..85c1048d34 100644
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -175,7 +175,7 @@ bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
   // If there is only one terminator instruction, process it.
   unsigned LastOpc = LastInst->getOpcode();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
-    if (!LastInst->getDesc()->isBranch())
+    if (!LastInst->getDesc().isBranch())
       return true;
 
     // Unconditional branch
@@ -259,7 +259,7 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
     } else {
       // Conditional branch.
       unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
-      const TargetInstrDescriptor &TID = get(Opc);
+      const TargetInstrDesc &TID = get(Opc);
 
       if (TID.getNumOperands() == 3)
         BuildMI(&MBB, TID).addReg(Cond[1].getReg())
@@ -275,15 +275,13 @@ InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   
   // Two-way Conditional branch.
   unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
-  const TargetInstrDescriptor &TID = get(Opc);
+  const TargetInstrDesc &TID = get(Opc);
 
   if (TID.getNumOperands() == 3)
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg())
-                      .addReg(Cond[2].getReg())
+    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
                       .addMBB(TBB);
   else
-    BuildMI(&MBB, TID).addReg(Cond[1].getReg())
-                      .addMBB(TBB);
+    BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
 
   BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
   return 2;
diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index 3c7fcfa666..58df0d6db2 100644
--- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -70,7 +70,7 @@ PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
   }
   Opcode -= ISD::BUILTIN_OP_END;
   
-  const TargetInstrDescriptor &TID = TII.get(Opcode);
+  const TargetInstrDesc &TID = TII.get(Opcode);
   
   isLoad  = TID.isSimpleLoad();
   isStore = TID.mayStore();
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 7ab17bce1b..6e8cebd979 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -262,13 +262,13 @@ void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
   
   // Find all return blocks, outputting a restore in each epilog.
   for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
-    if (!BB->empty() && BB->back().getDesc()->isReturn()) {
+    if (!BB->empty() && BB->back().getDesc().isReturn()) {
       IP = BB->end(); --IP;
       
       // Skip over all terminator instructions, which are part of the return
       // sequence.
       MachineBasicBlock::iterator I2 = IP;
-      while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
+      while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
         IP = I2;
       
       // Emit: MTVRSAVE InVRSave
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 866c2bfe46..19d7afa7f4 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -540,7 +540,7 @@ static void RemoveVRSaveCode(MachineInstr *MI) {
   // epilog blocks.
   for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
     // If last instruction is a return instruction, add an epilogue
-    if (!I->empty() && I->back().getDesc()->isReturn()) {
+    if (!I->empty() && I->back().getDesc().isReturn()) {
       bool FoundIt = false;
       for (MBBI = I->end(); MBBI != I->begin(); ) {
         --MBBI;
diff --git a/lib/Target/Sparc/DelaySlotFiller.cpp b/lib/Target/Sparc/DelaySlotFiller.cpp
index 00d14f2784..818573253f 100644
--- a/lib/Target/Sparc/DelaySlotFiller.cpp
+++ b/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -65,7 +65,7 @@ FunctionPass *llvm::createSparcDelaySlotFillerPass(TargetMachine &tm) {
 bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
   bool Changed = false;
   for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
-    if (I->getDesc()->hasDelaySlot()) {
+    if (I->getDesc().hasDelaySlot()) {
       MachineBasicBlock::iterator J = I;
       ++J;
       BuildMI(MBB, J, TII->get(SP::NOP));
diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 5342dd1872..10a5cdb624 100644
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -18,7 +18,7 @@ using namespace llvm;
 
 /// findTiedToSrcOperand - Returns the operand that is tied to the specified
 /// dest operand. Returns -1 if there isn't one.
-int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
+int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
   for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
     if (i == OpNum)
       continue;
@@ -29,22 +29,22 @@ int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
 }
 
 
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
                                  unsigned numOpcodes)
-  : desc(Desc), NumOpcodes(numOpcodes) {
+  : Descriptors(Desc), NumOpcodes(numOpcodes) {
 }
 
 TargetInstrInfo::~TargetInstrInfo() {
 }
 
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (!TID->isTerminator()) return false;
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.isTerminator()) return false;
   
   // Conditional branch is a special case.
-  if (TID->isBranch() && !TID->isBarrier())
+  if (TID.isBranch() && !TID.isBarrier())
     return true;
-  if (!TID->isPredicable())
+  if (!TID.isPredicable())
     return true;
   return !isPredicated(MI);
 }
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp
index d25ede168d..bd9e5c653c 100644
--- a/lib/Target/X86/X86CodeEmitter.cpp
+++ b/lib/Target/X86/X86CodeEmitter.cpp
@@ -60,7 +60,7 @@ namespace {
     }
 
     void emitInstruction(const MachineInstr &MI,
-                         const TargetInstrDescriptor *Desc);
+                         const TargetInstrDesc *Desc);
 
   private:
     void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
@@ -115,10 +115,10 @@ bool Emitter::runOnMachineFunction(MachineFunction &MF) {
       MCE.StartMachineBasicBlock(MBB);
       for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
            I != E; ++I) {
-        const TargetInstrDescriptor *Desc = I->getDesc();
-        emitInstruction(*I, Desc);
+        const TargetInstrDesc &Desc = I->getDesc();
+        emitInstruction(*I, &Desc);
         // MOVPC32r is basically a call plus a pop instruction.
-        if (Desc->Opcode == X86::MOVPC32r)
+        if (Desc.getOpcode() == X86::MOVPC32r)
           emitInstruction(*I, &II->get(X86::POP32r));
         NumEmitted++;  // Keep track of the # of mi's emitted
       }
@@ -394,7 +394,7 @@ void Emitter::emitMemModRMByte(const MachineInstr &MI,
   }
 }
 
-static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
+static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
   switch (Desc->TSFlags & X86II::ImmMask) {
   case X86II::Imm8:   return 1;
   case X86II::Imm16:  return 2;
@@ -436,18 +436,18 @@ inline static bool isX86_64NonExtLowByteReg(unsigned reg) {
 /// size, and 3) use of X86-64 extended registers.
 unsigned Emitter::determineREX(const MachineInstr &MI) {
   unsigned REX = 0;
-  const TargetInstrDescriptor *Desc = MI.getDesc();
+  const TargetInstrDesc &Desc = MI.getDesc();
 
   // Pseudo instructions do not need REX prefix byte.
-  if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
+  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
     return 0;
-  if (Desc->TSFlags & X86II::REX_W)
+  if (Desc.TSFlags & X86II::REX_W)
     REX |= 1 << 3;
 
-  unsigned NumOps = Desc->getNumOperands();
+  unsigned NumOps = Desc.getNumOperands();
   if (NumOps) {
     bool isTwoAddr = NumOps > 1 &&
-      Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
+      Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
 
     // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
     unsigned i = isTwoAddr ? 1 : 0;
@@ -460,7 +460,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
       }
     }
 
-    switch (Desc->TSFlags & X86II::FormMask) {
+    switch (Desc.TSFlags & X86II::FormMask) {
     case X86II::MRMInitReg:
       if (isX86_64ExtendedReg(MI.getOperand(0)))
         REX |= (1 << 0) | (1 << 2);
@@ -528,7 +528,7 @@ unsigned Emitter::determineREX(const MachineInstr &MI) {
 }
 
 void Emitter::emitInstruction(const MachineInstr &MI,
-                              const TargetInstrDescriptor *Desc) {
+                              const TargetInstrDesc *Desc) {
   unsigned Opcode = Desc->Opcode;
 
   // Emit the repeat opcode prefix as needed.
diff --git a/lib/Target/X86/X86FloatingPoint.cpp b/lib/Target/X86/X86FloatingPoint.cpp
index 3d0d4238d2..1b3e0b8749 100644
--- a/lib/Target/X86/X86FloatingPoint.cpp
+++ b/lib/Target/X86/X86FloatingPoint.cpp
@@ -205,7 +205,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
 
   for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
     MachineInstr *MI = I;
-    unsigned Flags = MI->getDesc()->TSFlags;
+    unsigned Flags = MI->getDesc().TSFlags;
     if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
       continue;  // Efficiently ignore non-fp insts!
 
@@ -597,7 +597,7 @@ void FPS::handleZeroArgFP(MachineBasicBlock::iterator &I) {
 ///
 void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->getNumOperands();
+  unsigned NumOps = MI->getDesc().getNumOperands();
   assert((NumOps == 5 || NumOps == 1) &&
          "Can only handle fst* & ftst instructions!");
 
@@ -657,7 +657,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
 ///
 void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
   MachineInstr *MI = I;
-  unsigned NumOps = MI->getDesc()->getNumOperands();
+  unsigned NumOps = MI->getDesc().getNumOperands();
   assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
 
   // Is this the last use of the source register?
@@ -766,7 +766,7 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) {
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->getNumOperands();
+  unsigned NumOperands = MI->getDesc().getNumOperands();
   assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
   unsigned Dest = getFPReg(MI->getOperand(0));
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
@@ -864,7 +864,7 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) {
   ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
   MachineInstr *MI = I;
 
-  unsigned NumOperands = MI->getDesc()->getNumOperands();
+  unsigned NumOperands = MI->getDesc().getNumOperands();
   assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
   unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
   unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index cae382d64a..42e41279f6 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1243,13 +1243,13 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
 }
 
 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
-  const TargetInstrDescriptor *TID = MI->getDesc();
-  if (!TID->isTerminator()) return false;
+  const TargetInstrDesc &TID = MI->getDesc();
+  if (!TID.isTerminator()) return false;
   
   // Conditional branch is a special case.
-  if (TID->isBranch() && !TID->isBarrier())
+  if (TID.isBranch() && !TID.isBarrier())
     return true;
-  if (!TID->isPredicable())
+  if (!TID.isPredicable())
     return true;
   return !isPredicated(MI);
 }
@@ -1276,7 +1276,7 @@ bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
   
   // If there is only one terminator instruction, process it.
   if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
-    if (!LastInst->getDesc()->isBranch())
+    if (!LastInst->getDesc().isBranch())
       return true;
     
     // If the block ends with a branch there are 3 possibilities:
@@ -1640,7 +1640,7 @@ static MachineInstr *FuseTwoAddrInst(unsigned Opcode,
     MIB.addImm(1).addReg(0).addImm(0);
   
   // Loop over the rest of the ri operands, converting them over.
-  unsigned NumOps = MI->getDesc()->getNumOperands()-2;
+  unsigned NumOps = MI->getDesc().getNumOperands()-2;
   for (unsigned i = 0; i != NumOps; ++i) {
     MachineOperand &MO = MI->getOperand(i+2);
     MIB = X86InstrAddOperand(MIB, MO);
@@ -1692,9 +1692,9 @@ X86InstrInfo::foldMemoryOperand(MachineInstr *MI, unsigned i,
                                    SmallVector<MachineOperand,4> &MOs) const {
   const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
   bool isTwoAddrFold = false;
-  unsigned NumOps = MI->getDesc()->getNumOperands();
+  unsigned NumOps = MI->getDesc().getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
-    MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   MachineInstr *NewMI = NULL;
   // Folding a memory location into the two-address part of a two-address
@@ -1798,7 +1798,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperand(MachineInstr *MI,
     return NULL;
 
   SmallVector<MachineOperand,4> MOs;
-  unsigned NumOps = LoadMI->getDesc()->getNumOperands();
+  unsigned NumOps = LoadMI->getDesc().getNumOperands();
   for (unsigned i = NumOps - 4; i != NumOps; ++i)
     MOs.push_back(LoadMI->getOperand(i));
   return foldMemoryOperand(MI, Ops[0], MOs);
@@ -1826,9 +1826,9 @@ bool X86InstrInfo::canFoldMemoryOperand(MachineInstr *MI,
 
   unsigned OpNum = Ops[0];
   unsigned Opc = MI->getOpcode();
-  unsigned NumOps = MI->getDesc()->getNumOperands();
+  unsigned NumOps = MI->getDesc().getNumOperands();
   bool isTwoAddr = NumOps > 1 &&
-    MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
 
   // Folding a memory location into the two-address part of a two-address
   // instruction is different than folding it other places.  It requires
@@ -1880,7 +1880,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
     return false;
   UnfoldStore &= FoldedStore;
 
-  const TargetInstrDescriptor &TID = get(Opc);
+  const TargetInstrDesc &TID = get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
     ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
@@ -1979,7 +1979,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   unsigned Index = I->second.second & 0xf;
   bool FoldedLoad = I->second.second & (1 << 4);
   bool FoldedStore = I->second.second & (1 << 5);
-  const TargetInstrDescriptor &TID = get(Opc);
+  const TargetInstrDesc &TID = get(Opc);
   const TargetOperandInfo &TOI = TID.OpInfo[Index];
   const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
     ? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index c0aefb4147..27675b94b1 100644
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -364,7 +364,7 @@ public:
   // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
   // specified machine instruction.
   //
-  unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
+  unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
     return TID->TSFlags >> X86II::OpcodeShift;
   }
   unsigned char getBaseOpcodeFor(unsigned Opcode) const {
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 1e5441794a..56523eb14d 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -729,7 +729,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF,
     MachineBasicBlock::iterator PI = prior(MBBI);
     unsigned Opc = PI->getOpcode();
     if (Opc != X86::POP32r && Opc != X86::POP64r &&
-        !PI->getDesc()->isTerminator())
+        !PI->getDesc().isTerminator())
       break;
     --MBBI;
   }