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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-07 14:33:13 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-07 14:33:13 +0000 |
| commit | f0e3ca012bc7dd6b95c091a7f5f147794983cf97 (patch) | |
| tree | f44b8d55869d9f6796238cb573e0b4193bfc77c3 /lib/Target | |
| parent | 13d297260f62ffae53b5349a55250fe3a4c4bcc2 (diff) | |
| download | llvm-f0e3ca012bc7dd6b95c091a7f5f147794983cf97.tar.gz llvm-f0e3ca012bc7dd6b95c091a7f5f147794983cf97.tar.bz2 llvm-f0e3ca012bc7dd6b95c091a7f5f147794983cf97.tar.xz | |
Most PPC M[TF]CR instructions do not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178978 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/PowerPC/PPCInstr64Bit.td | 9 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 15 |
2 files changed, 19 insertions, 5 deletions
diff --git a/lib/Target/PowerPC/PPCInstr64Bit.td b/lib/Target/PowerPC/PPCInstr64Bit.td index 600c11e9fb..45beecd792 100644 --- a/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/lib/Target/PowerPC/PPCInstr64Bit.td @@ -224,6 +224,7 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), // 64-bit CR instructions +let neverHasSideEffects = 1 in { def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; @@ -232,7 +233,13 @@ let isCodeGenOnly = 1 in def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), "#MFCR8pseud", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; - +} // neverHasSideEffects = 1 + +// MFCR uses all CR registers, but marking that explicitly causes +// problems because some of them appear to be undefined. Because +// this form is used only in prologue code, just mark it as having +// side effects. +let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), "mfcr $rT", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 14f35ef064..585368185b 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -1337,6 +1337,7 @@ let mayLoad = 1 in def RESTORE_VRSAVE : Pseudo<(outs VRSAVERC:$vrsave), (ins memri:$F), "#RESTORE_VRSAVE", []>; +let neverHasSideEffects = 1 in { def MTCRF : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins GPRC:$rS), "mtcrf $FXM, $rS", BrMCRX>, PPC970_MicroCode, PPC970_Unit_CRU; @@ -1355,14 +1356,20 @@ let isCodeGenOnly = 1 in def MFCRpseud: XFXForm_3<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), "#MFCRpseud", SprMFCR>, PPC970_MicroCode, PPC970_Unit_CRU; - -def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), - "mfcr $rT", SprMFCR>, - PPC970_MicroCode, PPC970_Unit_CRU; def MFOCRF: XFXForm_5a<31, 19, (outs GPRC:$rT), (ins crbitm:$FXM), "mfocrf $rT, $FXM", SprMFCR>, PPC970_DGroup_First, PPC970_Unit_CRU; +} // neverHasSideEffects = 1 + +// MFCR uses all CR registers, but marking that explicitly causes +// problems because some of them appear to be undefined. Because +// this form is used only in prologue code, just mark it as having +// side effects. +let /* Uses = [CR0, CR1, CR2, CR3, CR4, CR5, CR6] */ hasSideEffects = 1 in +def MFCR : XFXForm_3<31, 19, (outs GPRC:$rT), (ins), + "mfcr $rT", SprMFCR>, + PPC970_MicroCode, PPC970_Unit_CRU; // Pseudo instruction to perform FADD in round-to-zero mode. let usesCustomInserter = 1, Uses = [RM] in { |