diff options
author | Dan Gohman <gohman@apple.com> | 2009-01-15 22:18:12 +0000 |
---|---|---|
committer | Dan Gohman <gohman@apple.com> | 2009-01-15 22:18:12 +0000 |
commit | fc54c552963545a81e4ea38e60460590afb2d5ae (patch) | |
tree | bc07efaf419ac8d6edd959e8ff291c62d8ac6acd /lib/Target | |
parent | c475c3608a5f0fc0c6bd43da04ae786649690070 (diff) | |
download | llvm-fc54c552963545a81e4ea38e60460590afb2d5ae.tar.gz llvm-fc54c552963545a81e4ea38e60460590afb2d5ae.tar.bz2 llvm-fc54c552963545a81e4ea38e60460590afb2d5ae.tar.xz |
Generalize the HazardRecognizer interface so that it can be used
to support MachineInstr-based scheduling in addition to
SDNode-based scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62284 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target')
-rw-r--r-- | lib/Target/CellSPU/SPUHazardRecognizers.cpp | 11 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUHazardRecognizers.h | 12 | ||||
-rw-r--r-- | lib/Target/CellSPU/SPUISelDAGToDAG.cpp | 2 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCHazardRecognizers.cpp | 9 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCHazardRecognizers.h | 9 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 2 |
6 files changed, 26 insertions, 19 deletions
diff --git a/lib/Target/CellSPU/SPUHazardRecognizers.cpp b/lib/Target/CellSPU/SPUHazardRecognizers.cpp index 26392ed4b9..caaa71a422 100644 --- a/lib/Target/CellSPU/SPUHazardRecognizers.cpp +++ b/lib/Target/CellSPU/SPUHazardRecognizers.cpp @@ -17,6 +17,8 @@ #include "SPUHazardRecognizers.h" #include "SPU.h" #include "SPUInstrInfo.h" +#include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/Support/Debug.h" using namespace llvm; @@ -38,14 +40,15 @@ SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) : /// instruction. Currently returns NoHazard. /// /// \return NoHazard -HazardRecognizer::HazardType -SPUHazardRecognizer::getHazardType(SDNode *Node) +ScheduleHazardRecognizer::HazardType +SPUHazardRecognizer::getHazardType(SUnit *SU) { // Initial thoughts on how to do this, but this code cannot work unless the // function's prolog and epilog code are also being scheduled so that we can // accurately determine which pipeline is being scheduled. #if 0 - HazardRecognizer::HazardType retval = NoHazard; + const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); + ScheduleHazardRecognizer::HazardType retval = NoHazard; bool mustBeOdd = false; switch (Node->getOpcode()) { @@ -120,7 +123,7 @@ SPUHazardRecognizer::getHazardType(SDNode *Node) #endif } -void SPUHazardRecognizer::EmitInstruction(SDNode *Node) +void SPUHazardRecognizer::EmitInstruction(SUnit *SU) { } diff --git a/lib/Target/CellSPU/SPUHazardRecognizers.h b/lib/Target/CellSPU/SPUHazardRecognizers.h index 6b73083bd1..d0ae2d8e71 100644 --- a/lib/Target/CellSPU/SPUHazardRecognizers.h +++ b/lib/Target/CellSPU/SPUHazardRecognizers.h @@ -15,13 +15,14 @@ #ifndef SPUHAZRECS_H #define SPUHAZRECS_H -#include "llvm/CodeGen/ScheduleDAGSDNodes.h" -#include "SPUInstrInfo.h" +#include "llvm/CodeGen/ScheduleHazardRecognizer.h" namespace llvm { + +class TargetInstrInfo; /// SPUHazardRecognizer -class SPUHazardRecognizer : public HazardRecognizer +class SPUHazardRecognizer : public ScheduleHazardRecognizer { private: const TargetInstrInfo &TII; @@ -29,8 +30,8 @@ private: public: SPUHazardRecognizer(const TargetInstrInfo &TII); - virtual HazardType getHazardType(SDNode *Node); - virtual void EmitInstruction(SDNode *Node); + virtual HazardType getHazardType(SUnit *SU); + virtual void EmitInstruction(SUnit *SU); virtual void AdvanceCycle(); virtual void EmitNoop(); }; @@ -38,4 +39,3 @@ public: } // end namespace llvm #endif - diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index 858802cbb2..816502d9f5 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -353,7 +353,7 @@ public: /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. - virtual HazardRecognizer *CreateTargetHazardRecognizer() { + virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() { const TargetInstrInfo *II = TM.getInstrInfo(); assert(II && "No InstrInfo?"); return new SPUHazardRecognizer(*II); diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/lib/Target/PowerPC/PPCHazardRecognizers.cpp index 14745e61e1..d8a21bf38b 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.cpp +++ b/lib/Target/PowerPC/PPCHazardRecognizers.cpp @@ -15,6 +15,7 @@ #include "PPCHazardRecognizers.h" #include "PPC.h" #include "PPCInstrInfo.h" +#include "llvm/CodeGen/ScheduleDAG.h" #include "llvm/Support/Debug.h" using namespace llvm; @@ -118,8 +119,9 @@ isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const { /// terminate terminate the dispatch group. We turn NoopHazard for any /// instructions that wouldn't terminate the dispatch group that would cause a /// pipeline flush. -HazardRecognizer::HazardType PPCHazardRecognizer970:: -getHazardType(SDNode *Node) { +ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: +getHazardType(SUnit *SU) { + const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); bool isFirst, isSingle, isCracked, isLoad, isStore; PPCII::PPC970_Unit InstrType = GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, @@ -217,7 +219,8 @@ getHazardType(SDNode *Node) { return NoHazard; } -void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) { +void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { + const SDNode *Node = SU->getNode()->getFlaggedMachineNode(); bool isFirst, isSingle, isCracked, isLoad, isStore; PPCII::PPC970_Unit InstrType = GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, diff --git a/lib/Target/PowerPC/PPCHazardRecognizers.h b/lib/Target/PowerPC/PPCHazardRecognizers.h index 8957d180da..a596255a2f 100644 --- a/lib/Target/PowerPC/PPCHazardRecognizers.h +++ b/lib/Target/PowerPC/PPCHazardRecognizers.h @@ -14,7 +14,8 @@ #ifndef PPCHAZRECS_H #define PPCHAZRECS_H -#include "llvm/CodeGen/ScheduleDAGSDNodes.h" +#include "llvm/CodeGen/ScheduleHazardRecognizer.h" +#include "llvm/CodeGen/SelectionDAGNodes.h" #include "PPCInstrInfo.h" namespace llvm { @@ -25,7 +26,7 @@ namespace llvm { /// avoid structural hazards that cause significant performance penalties (e.g. /// setting the CTR register then branching through it within a dispatch group), /// or storing then loading from the same address within a dispatch group. -class PPCHazardRecognizer970 : public HazardRecognizer { +class PPCHazardRecognizer970 : public ScheduleHazardRecognizer { const TargetInstrInfo &TII; unsigned NumIssued; // Number of insts issued, including advanced cycles. @@ -47,8 +48,8 @@ class PPCHazardRecognizer970 : public HazardRecognizer { public: PPCHazardRecognizer970(const TargetInstrInfo &TII); - virtual HazardType getHazardType(SDNode *Node); - virtual void EmitInstruction(SDNode *Node); + virtual HazardType getHazardType(SUnit *SU); + virtual void EmitInstruction(SUnit *SU); virtual void AdvanceCycle(); virtual void EmitNoop(); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index a86604b1aa..0259a72801 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -181,7 +181,7 @@ namespace { /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. - virtual HazardRecognizer *CreateTargetHazardRecognizer() { + virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() { // Should use subtarget info to pick the right hazard recognizer. For // now, always return a PPC970 recognizer. const TargetInstrInfo *II = TM.getInstrInfo(); |