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| author | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:15:24 +0000 |
|---|---|---|
| committer | Anton Korobeynikov <asl@math.spbu.ru> | 2009-07-16 14:15:24 +0000 |
| commit | 48e8b3cc5841f0652430aa9f0ce3eb9fa09bdcda (patch) | |
| tree | 579a056782b0b042e66b2825650ca3df0081abb3 /lib | |
| parent | e3a7f7a2b20ad791626f58e16d76a514ea66b62b (diff) | |
| download | llvm-48e8b3cc5841f0652430aa9f0ce3eb9fa09bdcda.tar.gz llvm-48e8b3cc5841f0652430aa9f0ce3eb9fa09bdcda.tar.bz2 llvm-48e8b3cc5841f0652430aa9f0ce3eb9fa09bdcda.tar.xz | |
Implement shifts properly (hopefilly - finally!)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/SystemZ/SystemZISelLowering.cpp | 2 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 22 | ||||
| -rw-r--r-- | lib/Target/SystemZ/SystemZOperands.td | 6 |
3 files changed, 9 insertions, 21 deletions
diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 952f4edb63..6dea471dd9 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -52,7 +52,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : // Set shifts properties setShiftAmountFlavor(Extend); - setShiftAmountType(MVT::i32); + setShiftAmountType(MVT::i64); // Provide all sorts of operation actions setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index a1202aa2e1..1784331e3b 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -627,10 +627,7 @@ def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>; def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), "srlg\t{$dst, $src, $amt}", - [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>; -def SRLA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), - "srlg\t{$dst, $src, $amt}", - [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>; + [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>; let isTwoAddress = 1 in def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), @@ -638,10 +635,7 @@ def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>; def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), "sllg\t{$dst, $src, $amt}", - [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>; -def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), - "sllg\t{$dst, $src, $amt}", - [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>; + [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>; let Defs = [PSW] in { let isTwoAddress = 1 in @@ -649,13 +643,10 @@ def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), "sra\t{$src, $amt}", [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)), (implicit PSW)]>; + def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), "srag\t{$dst, $src, $amt}", - [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))), - (implicit PSW)]>; -def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), - "srag\t{$dst, $src, $amt}", - [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))), + [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)), (implicit PSW)]>; } // Defs = [PSW] @@ -664,10 +655,7 @@ def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt), [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>; def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt), "rllg\t{$dst, $src, $amt}", - [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>; -def ROTL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt), - "rllg\t{$dst, $src, $amt}", - [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>; + [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>; //===----------------------------------------------------------------------===// // Test instructions (like AND but do not produce any result) diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index d783050358..8eccd3a4ed 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -251,10 +251,10 @@ def s32imm64 : Operand<i64> { // Address operands // riaddr := reg + imm -def riaddr32 : Operand<i32>, - ComplexPattern<i32, 2, "SelectAddrRI12Only", []> { +def riaddr32 : Operand<i64>, + ComplexPattern<i64, 2, "SelectAddrRI12Only", []> { let PrintMethod = "printRIAddrOperand"; - let MIOperandInfo = (ops ADDR32:$base, u12imm:$disp); + let MIOperandInfo = (ops ADDR64:$base, u12imm:$disp); } def riaddr12 : Operand<i64>, |