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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 23:07:24 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-06-02 23:07:24 +0000 |
commit | 4f3fb6d08be511a277f92279e803ae6e95b00126 (patch) | |
tree | 1906d63cdd31b8c9ced9a5ff0032778404623d5e /lib | |
parent | f462e3fac7ac67503657d63dc35330d0b19359b3 (diff) | |
download | llvm-4f3fb6d08be511a277f92279e803ae6e95b00126.tar.gz llvm-4f3fb6d08be511a277f92279e803ae6e95b00126.tar.bz2 llvm-4f3fb6d08be511a277f92279e803ae6e95b00126.tar.xz |
Flag unallocatable register classes instead of giving them empty
allocation orders.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132509 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/ARM/ARMRegisterInfo.td | 4 | ||||
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.td | 22 | ||||
-rw-r--r-- | lib/Target/XCore/XCoreRegisterInfo.td | 21 |
3 files changed, 8 insertions, 39 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td index 962158580c..99418733c3 100644 --- a/lib/Target/ARM/ARMRegisterInfo.td +++ b/lib/Target/ARM/ARMRegisterInfo.td @@ -540,4 +540,6 @@ def QQQQPR : RegisterClass<"ARM", [v8i64], } // Condition code registers. -def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; +def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]> { + let isAllocatable = 0; +} diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index b5014b17d7..2c3cbfa459 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -681,15 +681,7 @@ def RFP80 : RegisterClass<"X86",[f80], 32, [FP0, FP1, FP2, FP3, FP4, FP5, FP6]>; // for transforming FPn allocations to STn registers) def RST : RegisterClass<"X86", [f80, f64, f32], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - RSTClass::iterator - RSTClass::allocation_order_end(const MachineFunction &MF) const { - return begin(); - } - }]; + let isAllocatable = 0; } // Generic vector registers: VR64 and VR128. @@ -742,15 +734,5 @@ def VR256 : RegisterClass<"X86", [v32i8, v8i32, v4i64, v8f32, v4f64], 256, // Status flags registers. def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> { let CopyCost = -1; // Don't allow copying of status registers. - - // EFLAGS is not allocatable. - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - CCRClass::iterator - CCRClass::allocation_order_end(const MachineFunction &MF) const { - return allocation_order_begin(MF); - } - }]; + let isAllocatable = 0; } diff --git a/lib/Target/XCore/XCoreRegisterInfo.td b/lib/Target/XCore/XCoreRegisterInfo.td index 765f717e20..b1ba964069 100644 --- a/lib/Target/XCore/XCoreRegisterInfo.td +++ b/lib/Target/XCore/XCoreRegisterInfo.td @@ -70,22 +70,7 @@ def GRRegs : RegisterClass<"XCore", [i32], 32, }]; } -def RRegs : RegisterClass<"XCore", [i32], 32, - // Reserved - [CP, DP, SP, LR]> { - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - RRegsClass::iterator - RRegsClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - RRegsClass::iterator - RRegsClass::allocation_order_end(const MachineFunction &MF) const { - // No allocatable registers - return begin(); - } - }]; +// Reserved +def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { + let isAllocatable = 0; } |