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author | Pawel Wodnicki <pawel@32bitmicro.com> | 2012-11-29 02:35:17 +0000 |
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committer | Pawel Wodnicki <pawel@32bitmicro.com> | 2012-11-29 02:35:17 +0000 |
commit | 01a2efa74ef4308167f3ea5342b03dc1dc8e9b8b (patch) | |
tree | 1530e6e3df4025f151a385582318e3220c27bde7 /lib | |
parent | 0bf24700008587be800865149b7e58b374de6fbf (diff) | |
download | llvm-01a2efa74ef4308167f3ea5342b03dc1dc8e9b8b.tar.gz llvm-01a2efa74ef4308167f3ea5342b03dc1dc8e9b8b.tar.bz2 llvm-01a2efa74ef4308167f3ea5342b03dc1dc8e9b8b.tar.xz |
Merging r168837: into the 3.2 release branch.
Avoid rewriting instructions twice.
This could cause miscompilations in targets where sub-register
composition is not always idempotent (ARM).
<rdar://problem/12758887>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_32@168849 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/CodeGen/RegisterCoalescer.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/lib/CodeGen/RegisterCoalescer.cpp b/lib/CodeGen/RegisterCoalescer.cpp index e47a677b77..2538f10ede 100644 --- a/lib/CodeGen/RegisterCoalescer.cpp +++ b/lib/CodeGen/RegisterCoalescer.cpp @@ -850,8 +850,17 @@ void RegisterCoalescer::updateRegDefsUses(unsigned SrcReg, // Update LiveDebugVariables. LDV->renameRegister(SrcReg, DstReg, SubIdx); + SmallPtrSet<MachineInstr*, 8> Visited; for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(SrcReg); MachineInstr *UseMI = I.skipInstruction();) { + // Each instruction can only be rewritten once because sub-register + // composition is not always idempotent. When SrcReg != DstReg, rewriting + // the UseMI operands removes them from the SrcReg use-def chain, but when + // SrcReg is DstReg we could encounter UseMI twice if it has multiple + // operands mentioning the virtual register. + if (SrcReg == DstReg && !Visited.insert(UseMI)) + continue; + SmallVector<unsigned,8> Ops; bool Reads, Writes; tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops); |