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| author | Andrew Trick <atrick@apple.com> | 2013-04-05 00:31:34 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2013-04-05 00:31:34 +0000 |
| commit | 614dacc9102ed3bf3fe4c985b5bc12857a26bae2 (patch) | |
| tree | bc3df65343cd34f0b26e2af6d412e1e1b68c9b10 /lib | |
| parent | 2182977ff2cc8ff1259e3a2c3528651496d818d4 (diff) | |
| download | llvm-614dacc9102ed3bf3fe4c985b5bc12857a26bae2.tar.gz llvm-614dacc9102ed3bf3fe4c985b5bc12857a26bae2.tar.bz2 llvm-614dacc9102ed3bf3fe4c985b5bc12857a26bae2.tar.xz | |
RegisterPressure heuristics currently require signed comparisons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178823 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/MachineScheduler.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/CodeGen/MachineScheduler.cpp b/lib/CodeGen/MachineScheduler.cpp index ed6b9861dc..5bd2349b50 100644 --- a/lib/CodeGen/MachineScheduler.cpp +++ b/lib/CodeGen/MachineScheduler.cpp @@ -1660,7 +1660,7 @@ initResourceDelta(const ScheduleDAGMI *DAG, } /// Return true if this heuristic determines order. -static bool tryLess(unsigned TryVal, unsigned CandVal, +static bool tryLess(int TryVal, int CandVal, ConvergingScheduler::SchedCandidate &TryCand, ConvergingScheduler::SchedCandidate &Cand, ConvergingScheduler::CandReason Reason) { @@ -1676,7 +1676,7 @@ static bool tryLess(unsigned TryVal, unsigned CandVal, return false; } -static bool tryGreater(unsigned TryVal, unsigned CandVal, +static bool tryGreater(int TryVal, int CandVal, ConvergingScheduler::SchedCandidate &TryCand, ConvergingScheduler::SchedCandidate &Cand, ConvergingScheduler::CandReason Reason) { |