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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:40:10 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:40:10 +0000 |
| commit | 06ae1d2c00a9af483c4e3fcf8117dfb7c290f175 (patch) | |
| tree | 9b085b365f5d803e2aef82728243f05e44c91c83 /lib | |
| parent | 0b71dafd66dba5eb9d438d6620f229d7aece0650 (diff) | |
| download | llvm-06ae1d2c00a9af483c4e3fcf8117dfb7c290f175.tar.gz llvm-06ae1d2c00a9af483c4e3fcf8117dfb7c290f175.tar.bz2 llvm-06ae1d2c00a9af483c4e3fcf8117dfb7c290f175.tar.xz | |
Merging r205630:
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r205630 | hfinkel | 2014-04-04 11:15:57 -0400 (Fri, 04 Apr 2014) | 6 lines
[PowerPC] Add a full condition code register to make the "cc" clobber work
gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205908 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index d566e2c3e5..43663ce013 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -144,6 +144,13 @@ def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; } +// The full condition-code register. This is not modeled fully, but defined +// here primarily, for compatibility with gcc, to allow the inline asm "cc" +// clobber specification to work. +def CC : PPCReg<"cc">, DwarfRegAlias<CR0> { + let Aliases = [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7]; +} + // Link register def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; //let Aliases = [LR] in @@ -234,3 +241,8 @@ def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>; def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY)> { let CopyCost = -1; } + +def CCRC : RegisterClass<"PPC", [i32], 32, (add CC)> { + let isAllocatable = 0; +} + |