Fixed instruction syntax in the comments (specifies how instr is used).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@7071 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 83 insertions, 83 deletions

diff --git a/lib/Target/SparcV9/SparcV9.td b/lib/Target/SparcV9/SparcV9.td
index 8bfb9a695e..6ee2f2160d 100644
--- a/lib/Target/SparcV9/SparcV9.td
+++ b/lib/Target/SparcV9/SparcV9.td
@@ -42,7 +42,7 @@ def ADDCi   : F3_2<2, 0b001000, "addC">;            // addC r, i, r
 def ADDCccr : F3_1<2, 0b011000, "addCcc">;          // addCcc r, r, r
 def ADDCcci : F3_2<2, 0b011000, "addCcc">;          // addCcc r, i, r
 
-// Section A.3: Branch on Integer Register with Prediction - p162
+// Section A.3: Branch on Integer Register with Prediction - p138
 set op2 = 0b011 in {
   def BRZ     : F2_4<0b001, "brz">;                 // Branch on rs1 == 0
   def BRLEZ   : F2_4<0b010, "brlez">;               // Branch on rs1 <= 0
@@ -524,94 +524,94 @@ def FMOVRQGEZ : F4_6<2, 0b110101, 0b111, 0b00111, "fmovrqgez">;//fmovsrz r,r,rd
 
 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
 // For integer condition codes
-def MOVAr    : F4_3<2, 0b101100, 0b1000, "mova">;      // mova i/xcc, rs2, rd
-def MOVAi    : F4_4<2, 0b101100, 0b1000, "mova">;      // mova i/xcc, rs2, rd
-def MOVNr    : F4_3<2, 0b101100, 0b0000, "movn">;      // mova i/xcc, rs2, rd
-def MOVNi    : F4_4<2, 0b101100, 0b0000, "movn">;      // mova i/xcc, rs2, rd
-def MOVNEr   : F4_3<2, 0b101100, 0b1001, "movne">;     // mova i/xcc, rs2, rd
-def MOVNEi   : F4_4<2, 0b101100, 0b1001, "movne">;     // mova i/xcc, rs2, rd
-def MOVEr    : F4_3<2, 0b101100, 0b0001, "move">;      // mova i/xcc, rs2, rd
-def MOVEi    : F4_4<2, 0b101100, 0b0001, "move">;      // mova i/xcc, rs2, rd
-def MOVGr    : F4_3<2, 0b101100, 0b1010, "movg">;      // mova i/xcc, rs2, rd
-def MOVGi    : F4_4<2, 0b101100, 0b1010, "movg">;      // mova i/xcc, rs2, rd
-def MOVLEr   : F4_3<2, 0b101100, 0b0010, "movle">;     // mova i/xcc, rs2, rd
-def MOVLEi   : F4_4<2, 0b101100, 0b0010, "movle">;     // mova i/xcc, rs2, rd
-def MOVGEr   : F4_3<2, 0b101100, 0b1011, "movge">;     // mova i/xcc, rs2, rd
-def MOVGEi   : F4_4<2, 0b101100, 0b1011, "movge">;     // mova i/xcc, rs2, rd
-def MOVLr    : F4_3<2, 0b101100, 0b0011, "movl">;      // mova i/xcc, rs2, rd
-def MOVLi    : F4_4<2, 0b101100, 0b0011, "movl">;      // mova i/xcc, rs2, rd
-def MOVGUr   : F4_3<2, 0b101100, 0b1100, "movgu">;     // mova i/xcc, rs2, rd
-def MOVGUi   : F4_4<2, 0b101100, 0b1100, "movgu">;     // mova i/xcc, rs2, rd
-def MOVLEUr  : F4_3<2, 0b101100, 0b0100, "movleu">;    // mova i/xcc, rs2, rd
-def MOVLEUi  : F4_4<2, 0b101100, 0b0100, "movleu">;    // mova i/xcc, rs2, rd
-def MOVCCr   : F4_3<2, 0b101100, 0b1101, "movcc">;     // mova i/xcc, rs2, rd
-def MOVCCi   : F4_4<2, 0b101100, 0b1101, "movcc">;     // mova i/xcc, rs2, rd
-def MOVCSr   : F4_3<2, 0b101100, 0b0101, "movcs">;     // mova i/xcc, rs2, rd
-def MOVCSi   : F4_4<2, 0b101100, 0b0101, "movcs">;     // mova i/xcc, rs2, rd
-def MOVPOSr  : F4_3<2, 0b101100, 0b1110, "movpos">;    // mova i/xcc, rs2, rd
-def MOVPOSi  : F4_4<2, 0b101100, 0b1110, "movpos">;    // mova i/xcc, rs2, rd
-def MOVNEGr  : F4_3<2, 0b101100, 0b0110, "movneg">;    // mova i/xcc, rs2, rd
-def MOVNEGi  : F4_4<2, 0b101100, 0b0110, "movneg">;    // mova i/xcc, rs2, rd
-def MOVVCr   : F4_3<2, 0b101100, 0b1111, "movvc">;     // mova i/xcc, rs2, rd
-def MOVVCi   : F4_4<2, 0b101100, 0b1111, "movvc">;     // mova i/xcc, rs2, rd
-def MOVVSr   : F4_3<2, 0b101100, 0b0111, "movvs">;     // mova i/xcc, rs2, rd
-def MOVVSi   : F4_4<2, 0b101100, 0b0111, "movvs">;     // mova i/xcc, rs2, rd
+def MOVAr    : F4_3<2, 0b101100, 0b1000, "mova">;      // mova   i/xcc, rs2, rd
+def MOVAi    : F4_4<2, 0b101100, 0b1000, "mova">;      // mova   i/xcc, rs2, rd
+def MOVNr    : F4_3<2, 0b101100, 0b0000, "movn">;      // movn   i/xcc, rs2, rd
+def MOVNi    : F4_4<2, 0b101100, 0b0000, "movn">;      // movn   i/xcc, rs2, rd
+def MOVNEr   : F4_3<2, 0b101100, 0b1001, "movne">;     // movne  i/xcc, rs2, rd
+def MOVNEi   : F4_4<2, 0b101100, 0b1001, "movne">;     // movne  i/xcc, rs2, rd
+def MOVEr    : F4_3<2, 0b101100, 0b0001, "move">;      // move   i/xcc, rs2, rd
+def MOVEi    : F4_4<2, 0b101100, 0b0001, "move">;      // move   i/xcc, rs2, rd
+def MOVGr    : F4_3<2, 0b101100, 0b1010, "movg">;      // movg   i/xcc, rs2, rd
+def MOVGi    : F4_4<2, 0b101100, 0b1010, "movg">;      // movg   i/xcc, rs2, rd
+def MOVLEr   : F4_3<2, 0b101100, 0b0010, "movle">;     // movle  i/xcc, rs2, rd
+def MOVLEi   : F4_4<2, 0b101100, 0b0010, "movle">;     // movle  i/xcc, rs2, rd
+def MOVGEr   : F4_3<2, 0b101100, 0b1011, "movge">;     // movge  i/xcc, rs2, rd
+def MOVGEi   : F4_4<2, 0b101100, 0b1011, "movge">;     // movge  i/xcc, rs2, rd
+def MOVLr    : F4_3<2, 0b101100, 0b0011, "movl">;      // movl   i/xcc, rs2, rd
+def MOVLi    : F4_4<2, 0b101100, 0b0011, "movl">;      // movl   i/xcc, rs2, rd
+def MOVGUr   : F4_3<2, 0b101100, 0b1100, "movgu">;     // movgu  i/xcc, rs2, rd
+def MOVGUi   : F4_4<2, 0b101100, 0b1100, "movgu">;     // movgu  i/xcc, rs2, rd
+def MOVLEUr  : F4_3<2, 0b101100, 0b0100, "movleu">;    // movleu i/xcc, rs2, rd
+def MOVLEUi  : F4_4<2, 0b101100, 0b0100, "movleu">;    // movleu i/xcc, rs2, rd
+def MOVCCr   : F4_3<2, 0b101100, 0b1101, "movcc">;     // movcc  i/xcc, rs2, rd
+def MOVCCi   : F4_4<2, 0b101100, 0b1101, "movcc">;     // movcc  i/xcc, rs2, rd
+def MOVCSr   : F4_3<2, 0b101100, 0b0101, "movcs">;     // movcs  i/xcc, rs2, rd
+def MOVCSi   : F4_4<2, 0b101100, 0b0101, "movcs">;     // movcs  i/xcc, rs2, rd
+def MOVPOSr  : F4_3<2, 0b101100, 0b1110, "movpos">;    // movpos i/xcc, rs2, rd
+def MOVPOSi  : F4_4<2, 0b101100, 0b1110, "movpos">;    // movpos i/xcc, rs2, rd
+def MOVNEGr  : F4_3<2, 0b101100, 0b0110, "movneg">;    // movneg i/xcc, rs2, rd
+def MOVNEGi  : F4_4<2, 0b101100, 0b0110, "movneg">;    // movneg i/xcc, rs2, rd
+def MOVVCr   : F4_3<2, 0b101100, 0b1111, "movvc">;     // movvc  i/xcc, rs2, rd
+def MOVVCi   : F4_4<2, 0b101100, 0b1111, "movvc">;     // movvc  i/xcc, rs2, rd
+def MOVVSr   : F4_3<2, 0b101100, 0b0111, "movvs">;     // movvs  i/xcc, rs2, rd
+def MOVVSi   : F4_4<2, 0b101100, 0b0111, "movvs">;     // movvs  i/xcc, rs2, rd
 
 // For floating-point condition codes
-def MOVFAr   : F4_3<2, 0b101100, 0b1000, "movfa">;     // mova i/xcc, rs2, rd
-def MOVFAi   : F4_4<2, 0b101100, 0b1000, "movfa">;     // mova i/xcc, rs2, rd
-def MOVFNr   : F4_3<2, 0b101100, 0b0000, "movfn">;     // mova i/xcc, rs2, rd
-def MOVFNi   : F4_4<2, 0b101100, 0b0000, "movfn">;     // mova i/xcc, rs2, rd
-def MOVFUr   : F4_3<2, 0b101100, 0b0111, "movfu">;     // mova i/xcc, rs2, rd
-def MOVFUi   : F4_4<2, 0b101100, 0b0111, "movfu">;     // mova i/xcc, rs2, rd
-def MOVFGr   : F4_3<2, 0b101100, 0b0110, "movfg">;     // mova i/xcc, rs2, rd
-def MOVFGi   : F4_4<2, 0b101100, 0b0110, "movfg">;     // mova i/xcc, rs2, rd
-def MOVFUGr  : F4_3<2, 0b101100, 0b0101, "movfug">;    // mova i/xcc, rs2, rd
-def MOVFUGi  : F4_4<2, 0b101100, 0b0101, "movfug">;    // mova i/xcc, rs2, rd
-def MOVFLr   : F4_3<2, 0b101100, 0b0100, "movfl">;     // mova i/xcc, rs2, rd
-def MOVFLi   : F4_4<2, 0b101100, 0b0100, "movfl">;     // mova i/xcc, rs2, rd
-def MOVFULr  : F4_3<2, 0b101100, 0b0011, "movful">;    // mova i/xcc, rs2, rd
-def MOVFULi  : F4_4<2, 0b101100, 0b0011, "movful">;    // mova i/xcc, rs2, rd
-def MOVFLGr  : F4_3<2, 0b101100, 0b0010, "movflg">;    // mova i/xcc, rs2, rd
-def MOVFLGi  : F4_4<2, 0b101100, 0b0010, "movflg">;    // mova i/xcc, rs2, rd
-def MOVFNEr  : F4_3<2, 0b101100, 0b0001, "movfne">;    // mova i/xcc, rs2, rd
-def MOVFNEi  : F4_4<2, 0b101100, 0b0001, "movfne">;    // mova i/xcc, rs2, rd
-def MOVFEr   : F4_3<2, 0b101100, 0b1001, "movfe">;     // mova i/xcc, rs2, rd
-def MOVFEi   : F4_4<2, 0b101100, 0b1001, "movfe">;     // mova i/xcc, rs2, rd
-def MOVFUEr  : F4_3<2, 0b101100, 0b1010, "movfue">;    // mova i/xcc, rs2, rd
-def MOVFUEi  : F4_4<2, 0b101100, 0b1010, "movfue">;    // mova i/xcc, rs2, rd
-def MOVFGEr  : F4_3<2, 0b101100, 0b1011, "movfge">;    // mova i/xcc, rs2, rd
-def MOVFGEi  : F4_4<2, 0b101100, 0b1011, "movfge">;    // mova i/xcc, rs2, rd
-def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">;   // mova i/xcc, rs2, rd
-def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">;   // mova i/xcc, rs2, rd
-def MOVFLEr  : F4_3<2, 0b101100, 0b1101, "movfle">;    // mova i/xcc, rs2, rd
-def MOVFLEi  : F4_4<2, 0b101100, 0b1101, "movfle">;    // mova i/xcc, rs2, rd
-def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">;   // mova i/xcc, rs2, rd
-def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">;   // mova i/xcc, rs2, rd
-def MOVFOr   : F4_3<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
-def MOVFOi   : F4_4<2, 0b101100, 0b1111, "movfo">;     // mova i/xcc, rs2, rd
+def MOVFAr   : F4_3<2, 0b101100, 0b1000, "movfa">;     // movfa   i/xcc, rs2, rd
+def MOVFAi   : F4_4<2, 0b101100, 0b1000, "movfa">;     // movfa   i/xcc, rs2, rd
+def MOVFNr   : F4_3<2, 0b101100, 0b0000, "movfn">;     // movfn   i/xcc, rs2, rd
+def MOVFNi   : F4_4<2, 0b101100, 0b0000, "movfn">;     // movfn   i/xcc, rs2, rd
+def MOVFUr   : F4_3<2, 0b101100, 0b0111, "movfu">;     // movfu   i/xcc, rs2, rd
+def MOVFUi   : F4_4<2, 0b101100, 0b0111, "movfu">;     // movfu   i/xcc, rs2, rd
+def MOVFGr   : F4_3<2, 0b101100, 0b0110, "movfg">;     // movfg   i/xcc, rs2, rd
+def MOVFGi   : F4_4<2, 0b101100, 0b0110, "movfg">;     // movfg   i/xcc, rs2, rd
+def MOVFUGr  : F4_3<2, 0b101100, 0b0101, "movfug">;    // movfug  i/xcc, rs2, rd
+def MOVFUGi  : F4_4<2, 0b101100, 0b0101, "movfug">;    // movfug  i/xcc, rs2, rd
+def MOVFLr   : F4_3<2, 0b101100, 0b0100, "movfl">;     // movfl   i/xcc, rs2, rd
+def MOVFLi   : F4_4<2, 0b101100, 0b0100, "movfl">;     // movfl   i/xcc, rs2, rd
+def MOVFULr  : F4_3<2, 0b101100, 0b0011, "movful">;    // movful  i/xcc, rs2, rd
+def MOVFULi  : F4_4<2, 0b101100, 0b0011, "movful">;    // movful  i/xcc, rs2, rd
+def MOVFLGr  : F4_3<2, 0b101100, 0b0010, "movflg">;    // movflg  i/xcc, rs2, rd
+def MOVFLGi  : F4_4<2, 0b101100, 0b0010, "movflg">;    // movflg  i/xcc, rs2, rd
+def MOVFNEr  : F4_3<2, 0b101100, 0b0001, "movfne">;    // movfne  i/xcc, rs2, rd
+def MOVFNEi  : F4_4<2, 0b101100, 0b0001, "movfne">;    // movfne  i/xcc, rs2, rd
+def MOVFEr   : F4_3<2, 0b101100, 0b1001, "movfe">;     // movfe   i/xcc, rs2, rd
+def MOVFEi   : F4_4<2, 0b101100, 0b1001, "movfe">;     // movfe   i/xcc, rs2, rd
+def MOVFUEr  : F4_3<2, 0b101100, 0b1010, "movfue">;    // movfue  i/xcc, rs2, rd
+def MOVFUEi  : F4_4<2, 0b101100, 0b1010, "movfue">;    // movfue  i/xcc, rs2, rd
+def MOVFGEr  : F4_3<2, 0b101100, 0b1011, "movfge">;    // movfge  i/xcc, rs2, rd
+def MOVFGEi  : F4_4<2, 0b101100, 0b1011, "movfge">;    // movfge  i/xcc, rs2, rd
+def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">;   // movfuge i/xcc, rs2, rd
+def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">;   // movfuge i/xcc, rs2, rd
+def MOVFLEr  : F4_3<2, 0b101100, 0b1101, "movfle">;    // movfle  i/xcc, rs2, rd
+def MOVFLEi  : F4_4<2, 0b101100, 0b1101, "movfle">;    // movfle  i/xcc, rs2, rd
+def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">;   // movfule i/xcc, rs2, rd
+def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">;   // movfule i/xcc, rs2, rd
+def MOVFOr   : F4_3<2, 0b101100, 0b1111, "movfo">;     // movfo   i/xcc, rs2, rd
+def MOVFOi   : F4_4<2, 0b101100, 0b1111, "movfo">;     // movfo   i/xcc, rs2, rd
 
 // Section A.36: Move Integer Register on Register Condition (MOVR)
-def MOVRZr   : F3_5<2, 0b101111, 0b001, "movrz">;      // movrz rs1, rs2, rd
-def MOVRZi   : F3_6<2, 0b101111, 0b001, "movrz">;      // movrz rs1, imm, rd
-def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">;    // movrz rs1, rs2, rd
-def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">;    // movrz rs1, imm, rd
-def MOVRLZr  : F3_5<2, 0b101111, 0b011, "movrlz">;     // movrz rs1, rs2, rd
-def MOVRLZi  : F3_6<2, 0b101111, 0b011, "movrlz">;     // movrz rs1, imm, rd
-def MOVRNZr  : F3_5<2, 0b101111, 0b101, "movrnz">;     // movrz rs1, rs2, rd
-def MOVRNZi  : F3_6<2, 0b101111, 0b101, "movrnz">;     // movrz rs1, imm, rd
-def MOVRGZr  : F3_5<2, 0b101111, 0b110, "movrgz">;     // movrz rs1, rs2, rd
-def MOVRGZi  : F3_6<2, 0b101111, 0b110, "movrgz">;     // movrz rs1, imm, rd
-def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">;    // movrz rs1, rs2, rd
-def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">;    // movrz rs1, imm, rd
+def MOVRZr   : F3_5<2, 0b101111, 0b001, "movrz">;      // movrz   rs1, rs2, rd
+def MOVRZi   : F3_6<2, 0b101111, 0b001, "movrz">;      // movrz   rs1, imm, rd
+def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">;    // movrlez rs1, rs2, rd
+def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">;    // movrlez rs1, imm, rd
+def MOVRLZr  : F3_5<2, 0b101111, 0b011, "movrlz">;     // movrlz  rs1, rs2, rd
+def MOVRLZi  : F3_6<2, 0b101111, 0b011, "movrlz">;     // movrlz  rs1, imm, rd
+def MOVRNZr  : F3_5<2, 0b101111, 0b101, "movrnz">;     // movrnz  rs1, rs2, rd
+def MOVRNZi  : F3_6<2, 0b101111, 0b101, "movrnz">;     // movrnz  rs1, imm, rd
+def MOVRGZr  : F3_5<2, 0b101111, 0b110, "movrgz">;     // movrgz  rs1, rs2, rd
+def MOVRGZi  : F3_6<2, 0b101111, 0b110, "movrgz">;     // movrgz  rs1, imm, rd
+def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">;    // movrgez rs1, rs2, rd
+def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">;    // movrgez rs1, imm, rd
 
 // Section A.37: Multiply and Divide (64-bit) - p199
-def MULXr  : F3_1<2, 0b001001, "mulx">;        // mulx  r, r, r
-def SDIVXr : F3_1<2, 0b101101, "sdivx">;       // mulx  r, r, r
-def UDIVXr : F3_1<2, 0b001101, "udivx">;       // mulx  r, r, r
-def MULXi  : F3_2<2, 0b001001, "mulx">;        // mulx  r, i, r
-def SDIVXi : F3_2<2, 0b101101, "sdivx">;       // mulx  r, i, r
-def UDIVXi : F3_2<2, 0b001101, "udivx">;       // mulx  r, i, r
+def MULXr  : F3_1<2, 0b001001, "mulx">;        // mulx   r, r, r
+def SDIVXr : F3_1<2, 0b101101, "sdivx">;       // sdivx  r, r, r
+def UDIVXr : F3_1<2, 0b001101, "udivx">;       // udivx  r, r, r
+def MULXi  : F3_2<2, 0b001001, "mulx">;        // mulx   r, i, r
+def SDIVXi : F3_2<2, 0b101101, "sdivx">;       // sdivx  r, i, r
+def UDIVXi : F3_2<2, 0b001101, "udivx">;       // udivx  r, i, r
 
 // Section A.38: Multiply (32-bit) - p200
 // Not used in the Sparc backend