diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:41 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-24 18:21:41 +0000 |
| commit | 9d1cd8e8689cb12d257265d43a79917ac332efbe (patch) | |
| tree | 92b139dfc9be1fbcf918e70a0c0a87b9e084aa71 /lib | |
| parent | 187225db529de6f63e844038cab578f06261a22f (diff) | |
| download | llvm-9d1cd8e8689cb12d257265d43a79917ac332efbe.tar.gz llvm-9d1cd8e8689cb12d257265d43a79917ac332efbe.tar.bz2 llvm-9d1cd8e8689cb12d257265d43a79917ac332efbe.tar.xz | |
Merging r201097:
------------------------------------------------------------------------
r201097 | thomas.stellard | 2014-02-10 08:58:30 -0800 (Mon, 10 Feb 2014) | 9 lines
R600/SI: Initialize M0 and emit S_WQM_B64 whenever DS instructions are
used
DS instructions that access local memory can only uses addresses that
are less than or equal to the value of M0. When M0 is uninitialized,
then we experience undefined behavior.
This patch also changes the behavior to emit S_WQM_B64 on pixel shaders
no matter what kind of DS instruction is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@204648 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/R600/SILowerControlFlow.cpp | 30 |
1 files changed, 22 insertions, 8 deletions
diff --git a/lib/Target/R600/SILowerControlFlow.cpp b/lib/Target/R600/SILowerControlFlow.cpp index d52f558774..ef867d3669 100644 --- a/lib/Target/R600/SILowerControlFlow.cpp +++ b/lib/Target/R600/SILowerControlFlow.cpp @@ -109,6 +109,23 @@ FunctionPass *llvm::createSILowerControlFlowPass(TargetMachine &tm) { return new SILowerControlFlowPass(tm); } +static bool isDS(unsigned Opcode) { + switch(Opcode) { + default: return false; + case AMDGPU::DS_ADD_U32_RTN: + case AMDGPU::DS_SUB_U32_RTN: + case AMDGPU::DS_WRITE_B32: + case AMDGPU::DS_WRITE_B8: + case AMDGPU::DS_WRITE_B16: + case AMDGPU::DS_READ_B32: + case AMDGPU::DS_READ_I8: + case AMDGPU::DS_READ_U8: + case AMDGPU::DS_READ_I16: + case AMDGPU::DS_READ_U16: + return true; + } +} + bool SILowerControlFlowPass::shouldSkip(MachineBasicBlock *From, MachineBasicBlock *To) { @@ -435,6 +452,11 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { Next = llvm::next(I); MachineInstr &MI = *I; + if (isDS(MI.getOpcode())) { + NeedM0 = true; + NeedWQM = true; + } + switch (MI.getOpcode()) { default: break; case AMDGPU::SI_IF: @@ -495,14 +517,6 @@ bool SILowerControlFlowPass::runOnMachineFunction(MachineFunction &MF) { IndirectDst(MI); break; - case AMDGPU::DS_READ_B32: - NeedWQM = true; - // Fall through - case AMDGPU::DS_WRITE_B32: - case AMDGPU::DS_ADD_U32_RTN: - NeedM0 = true; - break; - case AMDGPU::V_INTERP_P1_F32: case AMDGPU::V_INTERP_P2_F32: case AMDGPU::V_INTERP_MOV_F32: |