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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-26 19:25:47 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2011-05-26 19:25:47 +0000 |
| commit | a5e62019d771fd0b01311cc0136e64b66b299eb1 (patch) | |
| tree | 6a81d1f10d427fa7ef294c0453dcabad5d0c57f6 /lib | |
| parent | 4f5716ab88269a396e98ce1426372221534dcb6a (diff) | |
| download | llvm-a5e62019d771fd0b01311cc0136e64b66b299eb1.tar.gz llvm-a5e62019d771fd0b01311cc0136e64b66b299eb1.tar.bz2 llvm-a5e62019d771fd0b01311cc0136e64b66b299eb1.tar.xz | |
Fix some dwarf register numbers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132136 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/MBlaze/MBlazeRegisterInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/Mips/MipsRegisterInfo.td | 2 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.td | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/MBlaze/MBlazeRegisterInfo.td b/lib/Target/MBlaze/MBlazeRegisterInfo.td index 1a695a74bc..caca407411 100644 --- a/lib/Target/MBlaze/MBlazeRegisterInfo.td +++ b/lib/Target/MBlaze/MBlazeRegisterInfo.td @@ -43,7 +43,7 @@ let Namespace = "MBlaze" in { def R1 : MBlazeGPRReg< 1, "r1">, DwarfRegNum<[1]>; def R2 : MBlazeGPRReg< 2, "r2">, DwarfRegNum<[2]>; def R3 : MBlazeGPRReg< 3, "r3">, DwarfRegNum<[3]>; - def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[5]>; + def R4 : MBlazeGPRReg< 4, "r4">, DwarfRegNum<[4]>; def R5 : MBlazeGPRReg< 5, "r5">, DwarfRegNum<[5]>; def R6 : MBlazeGPRReg< 6, "r6">, DwarfRegNum<[6]>; def R7 : MBlazeGPRReg< 7, "r7">, DwarfRegNum<[7]>; diff --git a/lib/Target/Mips/MipsRegisterInfo.td b/lib/Target/Mips/MipsRegisterInfo.td index 341646b7d5..59ad841ebe 100644 --- a/lib/Target/Mips/MipsRegisterInfo.td +++ b/lib/Target/Mips/MipsRegisterInfo.td @@ -55,7 +55,7 @@ let Namespace = "Mips" in { def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; - def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>; + def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td index 26391657fd..da98ef070a 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.td +++ b/lib/Target/PowerPC/PPCRegisterInfo.td @@ -256,7 +256,7 @@ def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>; def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; // VRsave register -def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>; +def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; // Carry bit. In the architecture this is really bit 0 of the XER register // (which really is SPR register 1); this is the only bit interesting to a |