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author | Chris Lattner <sabre@nondot.org> | 2006-04-05 22:27:14 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-04-05 22:27:14 +0000 |
commit | d8242b49b24a46f685599834b6ca33dfbeba9382 (patch) | |
tree | 784666135db15210802a6f9301fa33b5a48f31aa /lib | |
parent | 20a86db26a94ca6ca61baa11176c07b8c61e4b01 (diff) | |
download | llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.gz llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.bz2 llvm-d8242b49b24a46f685599834b6ca33dfbeba9382.tar.xz |
Add all of the data stream intrinsics and instructions. woo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27442 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/PowerPC/PPCInstrAltivec.td | 21 | ||||
-rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 22 | ||||
-rw-r--r-- | lib/Target/PowerPC/README_ALTIVEC.txt | 7 |
3 files changed, 43 insertions, 7 deletions
diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td index 4c297bd178..6cac3ec40d 100644 --- a/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/lib/Target/PowerPC/PPCInstrAltivec.td @@ -93,6 +93,15 @@ class VX2_Int<bits<11> xo, string opc, Intrinsic IntID> def IMPLICIT_DEF_VRRC : Pseudo<(ops VRRC:$rD), "; $rD = IMPLICIT_DEF_VRRC", [(set VRRC:$rD, (v4f32 (undef)))]>; +let noResults = 1 in { +def DSS : DSS_Form<822, (ops u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), + "dss $STRM, $A", LdStGeneral /*FIXME*/, []>; +def DST : DSS_Form<342, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +def DSTST : DSS_Form<374, (ops u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB), + "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>; +} + def MFVSCR : VXForm_4<1540, (ops VRRC:$vD), "mfvcr $vD", LdStGeneral, [(set VRRC:$vD, (int_ppc_altivec_mfvscr))]>; @@ -431,6 +440,18 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), // Additional Altivec Patterns // +// DS* intrinsics. +def : Pat<(int_ppc_altivec_dss imm:$STRM), (DSS 0, imm:$STRM, 0, 0)>; +def : Pat<(int_ppc_altivec_dssall), (DSS 1, 0, 0, 0)>; +def : Pat<(int_ppc_altivec_dst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dstst GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 0, imm:$STRM, GPRC:$rA, GPRC:$rB)>; +def : Pat<(int_ppc_altivec_dststt GPRC:$rA, GPRC:$rB, imm:$STRM), + (DSTST 1, imm:$STRM, GPRC:$rA, GPRC:$rB)>; + // Undef/Zero. def : Pat<(v16i8 (undef)), (v16i8 (IMPLICIT_DEF_VRRC))>; def : Pat<(v8i16 (undef)), (v8i16 (IMPLICIT_DEF_VRRC))>; diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index c3a78e65bf..10ac79b1c2 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -325,6 +325,26 @@ class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr, : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> { } +// DSS_Form - Form X instruction, used for altivec dss* instructions. +class DSS_Form<bits<10> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<31, OL, asmstr, itin> { + bits<1> T; + bits<2> STRM; + bits<5> A; + bits<5> B; + + let Pattern = pattern; + + let Inst{6} = T; + let Inst{7-8} = 0; + let Inst{9-10} = STRM; + let Inst{11-15} = A; + let Inst{16-20} = B; + let Inst{21-30} = xo; + let Inst{31} = 0; +} + // 1.7.7 XL-Form class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, InstrItinClass itin> @@ -589,6 +609,8 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, let Inst{31} = RC; } + + // E-1 VA-Form // VAForm_1 - DACB ordering. diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt index 0a338dac6a..78505120f7 100644 --- a/lib/Target/PowerPC/README_ALTIVEC.txt +++ b/lib/Target/PowerPC/README_ALTIVEC.txt @@ -47,13 +47,6 @@ altivec instructions. Examples //===----------------------------------------------------------------------===// -Missing intrinsics: - -ds* -vsel (some aliases only accessible using builtins) - -//===----------------------------------------------------------------------===// - FABS/FNEG can be codegen'd with the appropriate and/xor of -0.0. //===----------------------------------------------------------------------===// |