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| author | Owen Anderson <resistor@mac.com> | 2009-08-10 22:56:29 +0000 |
|---|---|---|
| committer | Owen Anderson <resistor@mac.com> | 2009-08-10 22:56:29 +0000 |
| commit | e50ed30282bb5b4a9ed952580523f2dda16215ac (patch) | |
| tree | fa8e46b304328a852135fef969e13d47e51196d0 /lib | |
| parent | a8c6908995c39094fc071e5c629c40773197d571 (diff) | |
| download | llvm-e50ed30282bb5b4a9ed952580523f2dda16215ac.tar.gz llvm-e50ed30282bb5b4a9ed952580523f2dda16215ac.tar.bz2 llvm-e50ed30282bb5b4a9ed952580523f2dda16215ac.tar.xz | |
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
81 files changed, 6370 insertions, 6370 deletions
diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp index d6137a538b..7a1eeb23d2 100644 --- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp +++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp @@ -33,8 +33,8 @@ CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm, // HandleByVal - Allocate a stack slot large enough to pass an argument by // value. The size and alignment information of the argument is encoded in its // parameter attribute. -void CCState::HandleByVal(unsigned ValNo, MVT ValVT, - MVT LocVT, CCValAssign::LocInfo LocInfo, +void CCState::HandleByVal(unsigned ValNo, EVT ValVT, + EVT LocVT, CCValAssign::LocInfo LocInfo, int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags) { unsigned Align = ArgFlags.getByValAlign(); @@ -65,12 +65,12 @@ CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins, unsigned NumArgs = Ins.size(); for (unsigned i = 0; i != NumArgs; ++i) { - MVT ArgVT = Ins[i].VT; + EVT ArgVT = Ins[i].VT; ISD::ArgFlagsTy ArgFlags = Ins[i].Flags; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG cerr << "Formal argument #" << i << " has unhandled type " - << ArgVT.getMVTString(); + << ArgVT.getEVTString(); #endif llvm_unreachable(0); } @@ -83,12 +83,12 @@ void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, CCAssignFn Fn) { // Determine which register each value should be copied into. for (unsigned i = 0, e = Outs.size(); i != e; ++i) { - MVT VT = Outs[i].Val.getValueType(); + EVT VT = Outs[i].Val.getValueType(); ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG cerr << "Return operand #" << i << " has unhandled type " - << VT.getMVTString(); + << VT.getEVTString(); #endif llvm_unreachable(0); } @@ -102,12 +102,12 @@ void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, CCAssignFn Fn) { unsigned NumOps = Outs.size(); for (unsigned i = 0; i != NumOps; ++i) { - MVT ArgVT = Outs[i].Val.getValueType(); + EVT ArgVT = Outs[i].Val.getValueType(); ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG cerr << "Call operand #" << i << " has unhandled type " - << ArgVT.getMVTString(); + << ArgVT.getEVTString(); #endif llvm_unreachable(0); } @@ -116,17 +116,17 @@ void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, /// AnalyzeCallOperands - Same as above except it takes vectors of types /// and argument flags. -void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, +void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs, SmallVectorImpl<ISD::ArgFlagsTy> &Flags, CCAssignFn Fn) { unsigned NumOps = ArgVTs.size(); for (unsigned i = 0; i != NumOps; ++i) { - MVT ArgVT = ArgVTs[i]; + EVT ArgVT = ArgVTs[i]; ISD::ArgFlagsTy ArgFlags = Flags[i]; if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) { #ifndef NDEBUG cerr << "Call operand #" << i << " has unhandled type " - << ArgVT.getMVTString(); + << ArgVT.getEVTString(); #endif llvm_unreachable(0); } @@ -138,12 +138,12 @@ void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs, void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, CCAssignFn Fn) { for (unsigned i = 0, e = Ins.size(); i != e; ++i) { - MVT VT = Ins[i].VT; + EVT VT = Ins[i].VT; ISD::ArgFlagsTy Flags = Ins[i].Flags; if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) { #ifndef NDEBUG cerr << "Call result #" << i << " has unhandled type " - << VT.getMVTString(); + << VT.getEVTString(); #endif llvm_unreachable(0); } @@ -152,11 +152,11 @@ void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins, /// AnalyzeCallResult - Same as above except it's specialized for calls which /// produce a single value. -void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) { +void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) { if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) { #ifndef NDEBUG cerr << "Call result has unhandled type " - << VT.getMVTString(); + << VT.getEVTString(); #endif llvm_unreachable(0); } diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 6446ed9cdb..6119411d36 100644 --- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -215,12 +215,12 @@ namespace { SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare = false); - SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, + SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, DebugLoc DL, bool foldBooleans = true); SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, unsigned HiOp); - SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); - SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); + SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); + SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); SDValue BuildSDIV(SDNode *N); SDValue BuildUDIV(SDNode *N); SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); @@ -253,7 +253,7 @@ namespace { /// getShiftAmountTy - Returns a type large enough to hold any valid /// shift amount - before type legalization these can be huge. - MVT getShiftAmountTy() { + EVT getShiftAmountTy() { return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); } @@ -331,7 +331,7 @@ CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { static char isNegatibleForFree(SDValue Op, bool LegalOperations, unsigned Depth = 0) { // No compile time optimizations on this type. - if (Op.getValueType() == MVT::ppcf128) + if (Op.getValueType() == EVT::ppcf128) return 0; // fneg is removable even if it has multiple uses. @@ -497,7 +497,7 @@ static bool isOneUseSetCC(SDValue N) { SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, SDValue N0, SDValue N1) { - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { if (isa<ConstantSDNode>(N1)) { // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) @@ -833,12 +833,12 @@ SDValue DAGCombiner::combine(SDNode *N) { /// otherwise return a null sd operand. static SDValue getInputChainForNode(SDNode *N) { if (unsigned NumOps = N->getNumOperands()) { - if (N->getOperand(0).getValueType() == MVT::Other) + if (N->getOperand(0).getValueType() == EVT::Other) return N->getOperand(0); - else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) + else if (N->getOperand(NumOps-1).getValueType() == EVT::Other) return N->getOperand(NumOps-1); for (unsigned i = 1; i < NumOps-1; ++i) - if (N->getOperand(i).getValueType() == MVT::Other) + if (N->getOperand(i).getValueType() == EVT::Other) return N->getOperand(i); } return SDValue(); @@ -911,7 +911,7 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) { } else { // New and improved token factor. Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), - MVT::Other, &Ops[0], Ops.size()); + EVT::Other, &Ops[0], Ops.size()); } // Don't add users to work list. @@ -935,7 +935,7 @@ SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { static SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, SelectionDAG &DAG) { - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); SDValue N00 = N0.getOperand(0); SDValue N01 = N0.getOperand(1); ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); @@ -959,7 +959,7 @@ SDValue DAGCombiner::visitADD(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // fold vector ops if (VT.isVector()) { @@ -1082,13 +1082,13 @@ SDValue DAGCombiner::visitADDC(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // If the flag result is dead, turn this into an ADD. if (N->hasNUsesOfValue(0, 1)) return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + N->getDebugLoc(), EVT::Flag)); // canonicalize constant to RHS. if (N0C && !N1C) @@ -1097,7 +1097,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) { // fold (addc x, 0) -> x + no carry out if (N1C && N1C->isNullValue()) return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + N->getDebugLoc(), EVT::Flag)); // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. APInt LHSZero, LHSOne; @@ -1114,7 +1114,7 @@ SDValue DAGCombiner::visitADDC(SDNode *N) { (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), DAG.getNode(ISD::CARRY_FALSE, - N->getDebugLoc(), MVT::Flag)); + N->getDebugLoc(), EVT::Flag)); } return SDValue(); @@ -1144,7 +1144,7 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // fold vector ops if (VT.isVector()) { @@ -1217,7 +1217,7 @@ SDValue DAGCombiner::visitMUL(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // fold vector ops if (VT.isVector()) { @@ -1310,7 +1310,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -1397,7 +1397,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -1417,7 +1417,7 @@ SDValue DAGCombiner::visitUDIV(SDNode *N) { if (N1.getOpcode() == ISD::SHL) { if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { if (SHC->getAPIntValue().isPowerOf2()) { - MVT ADDVT = N1.getOperand(1).getValueType(); + EVT ADDVT = N1.getOperand(1).getValueType(); SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, N1.getOperand(1), DAG.getConstant(SHC->getAPIntValue() @@ -1449,7 +1449,7 @@ SDValue DAGCombiner::visitSREM(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (srem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) @@ -1491,7 +1491,7 @@ SDValue DAGCombiner::visitUREM(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (urem c1, c2) -> c1%c2 if (N0C && N1C && !N1C->isNullValue()) @@ -1543,7 +1543,7 @@ SDValue DAGCombiner::visitMULHS(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (mulhs x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1564,7 +1564,7 @@ SDValue DAGCombiner::visitMULHU(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (mulhu x, 0) -> 0 if (N1C && N1C->isNullValue()) @@ -1667,7 +1667,7 @@ SDValue DAGCombiner::visitUDIVREM(SDNode *N) { /// two operands of the same opcode, try to simplify it. SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); // For each of OP in AND/OR/XOR: @@ -1713,7 +1713,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { SDValue LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N1.getValueType(); + EVT VT = N1.getValueType(); unsigned BitWidth = VT.getSizeInBits(); // fold vector ops @@ -1824,7 +1824,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { // fold (zext_inreg (extload x)) -> (zextload x) if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT EVT = LN0->getMemoryVT(); + EVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); @@ -1846,7 +1846,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT EVT = LN0->getMemoryVT(); + EVT EVT = LN0->getMemoryVT(); // If we zero all the possible extended bits, then we can turn this into // a zextload if we are running before legalize or the operation is legal. unsigned BitWidth = N1.getValueSizeInBits(); @@ -1873,24 +1873,24 @@ SDValue DAGCombiner::visitAND(SDNode *N) { LN0->isUnindexed() && N0.hasOneUse() && // Do not change the width of a volatile load. !LN0->isVolatile()) { - MVT EVT = MVT::Other; + EVT ExtVT = EVT::Other; uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) - EVT = MVT::getIntegerVT(ActiveBits); + ExtVT = EVT::getIntegerVT(ActiveBits); - MVT LoadedVT = LN0->getMemoryVT(); + EVT LoadedVT = LN0->getMemoryVT(); // Do not generate loads of non-round integer types since these can // be expensive (and would be wrong if the type is not byte sized). - if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && - (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { - MVT PtrType = N0.getOperand(1).getValueType(); + if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && + (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { + EVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to add an offset to the pointer to // load the correct bytes. For little endian systems, we merely need to // read fewer bytes from the same pointer. unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; - unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; + unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8; unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; unsigned Alignment = LN0->getAlignment(); SDValue NewPtr = LN0->getBasePtr(); @@ -1905,7 +1905,7 @@ SDValue DAGCombiner::visitAND(SDNode *N) { SDValue Load = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), - EVT, LN0->isVolatile(), Alignment); + ExtVT, LN0->isVolatile(), Alignment); AddToWorkList(N); CombineTo(N0.getNode(), Load, Load.getValue(1)); return SDValue(N, 0); // Return N so it doesn't get rechecked! @@ -1922,7 +1922,7 @@ SDValue DAGCombiner::visitOR(SDNode *N) { SDValue LL, LR, RL, RR, CC0, CC1; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N1.getValueType(); + EVT VT = N1.getValueType(); // fold vector ops if (VT.isVector()) { @@ -2062,7 +2062,7 @@ static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { // a rot[lr]. SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { // Must be a legal type. Expanded 'n promoted things won't work with rotates. - MVT VT = LHS.getValueType(); + EVT VT = LHS.getValueType(); if (!TLI.isTypeLegal(VT)) return 0; // The target must have at least one rotate flavor. @@ -2223,7 +2223,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { SDValue LHS, RHS, CC; ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // fold vector ops if (VT.isVector()) { @@ -2284,7 +2284,7 @@ SDValue DAGCombiner::visitXOR(SDNode *N) { } // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc - if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && + if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 && (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { @@ -2391,7 +2391,7 @@ SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) return SDValue(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // If this is a signed shift right, and the high bit is modified by the // logical operation, do not perform the transformation. The highBitSet @@ -2421,7 +2421,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); unsigned OpSizeInBits = VT.getSizeInBits(); // fold (shl c1, c2) -> c1<<c2 @@ -2446,7 +2446,7 @@ SDValue DAGCombiner::visitSHL(SDNode *N) { N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { SDValue N101 = N1.getOperand(0).getOperand(1); if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { - MVT TruncVT = N1.getValueType(); + EVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); APInt TruncC = N101C->getAPIntValue(); TruncC.trunc(TruncVT.getSizeInBits()); @@ -2513,7 +2513,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); // fold (sra c1, c2) -> (sra c1, c2) if (N0C && N1C) @@ -2534,7 +2534,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { // sext_inreg. if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); - MVT EVT = MVT::getIntegerVT(LowBits); + EVT EVT = EVT::getIntegerVT(LowBits); if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0.getOperand(0), DAG.getValueType(EVT)); @@ -2561,8 +2561,8 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { if (N01C && N1C) { // Determine what the truncate's result bitsize and type would be. unsigned VTValSize = VT.getSizeInBits(); - MVT TruncVT = - MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); + EVT TruncVT = + EVT::getIntegerVT(VTValSize - N1C->getZExtValue()); // Determine the residual right-shift amount. signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); @@ -2592,7 +2592,7 @@ SDValue DAGCombiner::visitSRA(SDNode *N) { N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { SDValue N101 = N1.getOperand(0).getOperand(1); if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { - MVT TruncVT = N1.getValueType(); + EVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); APInt TruncC = N101C->getAPIntValue(); TruncC.trunc(TruncVT.getSizeInBits()); @@ -2623,7 +2623,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); - MVT VT = N0.getValueType(); + EVT VT = N0.getValueType(); unsigned OpSizeInBits = VT.getSizeInBits(); // fold (srl c1, c2) -> c1 >>u c2 @@ -2657,7 +2657,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { // Shifting in all undef bits? - MVT SmallVT = N0.getOperand(0).getValueType(); + EVT SmallVT = N0.getOperand(0).getValueType(); if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) return DAG.getUNDEF(VT); @@ -2716,7 +2716,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { SDValue N101 = N1.getOperand(0).getOperand(1); if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { - MVT TruncVT = N1.getValueType(); + EVT TruncVT = N1.getValueType(); SDValue N100 = N1.getOperand(0).getOperand(0); APInt TruncC = N101C->getAPIntValue(); TruncC.trunc(TruncVT.getSizeInBits()); @@ -2740,7 +2740,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) { SDValue DAGCombiner::visitCTLZ(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (ctlz c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2750,7 +2750,7 @@ SDValue DAGCombiner::visitCTLZ(SDNode *N) { SDValue DAGCombiner::visitCTTZ(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (cttz c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2760,7 +2760,7 @@ SDValue DAGCombiner::visitCTTZ(SDNode *N) { SDValue DAGCombiner::visitCTPOP(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (ctpop c1) -> c2 if (isa<ConstantSDNode>(N0)) @@ -2775,8 +2775,8 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); - MVT VT = N->getValueType(0); - MVT VT0 = N0.getValueType(); + EVT VT = N->getValueType(0); + EVT VT0 = N0.getValueType(); // fold (select C, X, X) -> X if (N1 == N2) @@ -2788,11 +2788,11 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { if (N0C && N0C->isNullValue()) return N2; // fold (select C, 1, X) -> (or C, X) - if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) + if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1) return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); // fold (select C, 0, 1) -> (xor C, 1) if (VT.isInteger() && - (VT0 == MVT::i1 || + (VT0 == EVT::i1 || (VT0.isInteger() && TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { @@ -2808,27 +2808,27 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); } // fold (select C, 0, X) -> (and (not C), X) - if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { + if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) { SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); } // fold (select C, X, 1) -> (or (not C), X) - if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { + if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) { SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); AddToWorkList(NOTNode.getNode()); return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); } // fold (select C, X, 0) -> (and C, X) - if (VT == MVT::i1 && N2C && N2C->isNullValue()) + if (VT == EVT::i1 && N2C && N2C->isNullValue()) return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); // fold (select X, X, Y) -> (or X, Y) // fold (select X, 1, Y) -> (or X, Y) - if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) + if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); // fold (select X, Y, X) -> (and X, Y) // fold (select X, Y, 0) -> (and X, Y) - if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) + if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); // If we can fold this based on the true/false value, do so. @@ -2838,10 +2838,10 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) { // fold selects based on a setcc into other things, such as min/max/abs if (N0.getOpcode() == ISD::SETCC) { // FIXME: - // Check against MVT::Other for SELECT_CC, which is a workaround for targets + // Check against EVT::Other for SELECT_CC, which is a workaround for targets // having to say they don't support SELECT_CC on every type the DAG knows // about, since there is no way to mark an opcode illegal at all value types - if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && + if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) && TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, N0.getOperand(0), N0.getOperand(1), @@ -2962,7 +2962,7 @@ static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (sext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -3071,7 +3071,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT EVT = LN0->getMemoryVT(); + EVT EVT = LN0->getMemoryVT(); if ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, @@ -3127,7 +3127,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (zext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -3231,7 +3231,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT EVT = LN0->getMemoryVT(); + EVT EVT = LN0->getMemoryVT(); if ((!LegalOperations && !LN0->isVolatile()) || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, @@ -3262,7 +3262,7 @@ SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (aext c1) -> c1 if (isa<ConstantSDNode>(N0)) @@ -3367,7 +3367,7 @@ SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT EVT = LN0->getMemoryVT(); + EVT EVT = LN0->getMemoryVT(); SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), VT, LN0->getChain(), LN0->getBasePtr(), LN0->getSrcValue(), @@ -3437,8 +3437,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { unsigned Opc = N->getOpcode(); ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); - MVT EVT = VT; + EVT VT = N->getValueType(0); + EVT ExtVT = VT; // This transformation isn't valid for vector loads. if (VT.isVector()) @@ -3448,12 +3448,12 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { // extended to VT. if (Opc == ISD::SIGN_EXTEND_INREG) { ExtType = ISD::SEXTLOAD; - EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); - if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) + ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) return SDValue(); } - unsigned EVTBits = EVT.getSizeInBits(); + unsigned EVTBits = ExtVT.getSizeInBits(); unsigned ShAmt = 0; if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { @@ -3469,18 +3469,18 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { // Do not generate loads of non-round integer types since these can // be expensive (and would be wrong if the type is not byte sized). - if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && + if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && // Do not change the width of a volatile load. !cast<LoadSDNode>(N0)->isVolatile()) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); - MVT PtrType = N0.getOperand(1).getValueType(); + EVT PtrType = N0.getOperand(1).getValueType(); // For big endian targets, we need to adjust the offset to the pointer to // load the correct bytes. if (TLI.isBigEndian()) { unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); - unsigned EVTStoreBits = EVT.getStoreSizeInBits(); + unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; } @@ -3497,7 +3497,7 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { LN0->isVolatile(), NewAlign) : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, - EVT, LN0->isVolatile(), NewAlign); + ExtVT, LN0->isVolatile(), NewAlign); // Replace the old load's chain with the new load's chain. WorkListRemover DeadNodes(*this); @@ -3514,8 +3514,8 @@ SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); - MVT VT = N->getValueType(0); - MVT EVT = cast<VTSDNode>(N1)->getVT(); + EVT VT = N->getValueType(0); + EVT EVT = cast<VTSDNode>(N1)->getVT(); unsigned VTBits = VT.getSizeInBits(); unsigned EVTBits = EVT.getSizeInBits(); @@ -3610,7 +3610,7 @@ SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // noop truncate if (N0.getValueType() == N->getValueType(0)) @@ -3660,14 +3660,14 @@ static SDNode *getBuildPairElt(SDNode *N, unsigned i) { /// CombineConsecutiveLoads - build_pair (load, load) -> load /// if load locations are consecutive. -SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { +SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { assert(N->getOpcode() == ISD::BUILD_PAIR); LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) return SDValue(); - MVT LD1VT = LD1->getValueType(0); + EVT LD1VT = LD1->getValueType(0); const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); if (ISD::isNON_EXTLoad(LD2) && @@ -3679,7 +3679,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { unsigned Align = LD1->getAlignment(); unsigned NewAlign = TLI.getTargetData()-> - getABITypeAlignment(VT.getTypeForMVT()); + getABITypeAlignment(VT.getTypeForEVT()); if (NewAlign <= Align && (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) @@ -3693,7 +3693,7 @@ SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // If the input is a BUILD_VECTOR with all constant elements, fold this now. // Only do this before legalize, since afterward the target may be depending @@ -3711,7 +3711,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { break; } - MVT DestEltVT = N->getValueType(0).getVectorElementType(); + EVT DestEltVT = N->getValueType(0).getVectorElementType(); assert(!DestEltVT.isVector() && "Element type of vector ValueType must not be vector!"); if (isSimple) @@ -3737,7 +3737,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { LoadSDNode *LN0 = cast<LoadSDNode>(N0); unsigned Align = TLI.getTargetData()-> - getABITypeAlignment(VT.getTypeForMVT()); + getABITypeAlignment(VT.getTypeForEVT()); unsigned OrigAlign = LN0->getAlignment(); if (Align <= OrigAlign) { @@ -3780,7 +3780,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { isa<ConstantFPSDNode>(N0.getOperand(0)) && VT.isInteger() && !VT.isVector()) { unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); - MVT IntXVT = MVT::getIntegerVT(OrigXWidth); + EVT IntXVT = EVT::getIntegerVT(OrigXWidth); if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), IntXVT, N0.getOperand(1)); @@ -3828,7 +3828,7 @@ SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { } SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); return CombineConsecutiveLoads(N, VT); } @@ -3836,8 +3836,8 @@ SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the /// destination element value type. SDValue DAGCombiner:: -ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { - MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); +ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { + EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); // If this is already the right type, we're done. if (SrcEltVT == DstEltVT) return SDValue(BV, 0); @@ -3859,7 +3859,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { DstEltVT, Op)); AddToWorkList(Ops.back().getNode()); } - MVT VT = MVT::getVectorVT(DstEltVT, + EVT VT = EVT::getVectorVT(DstEltVT, BV->getValueType(0).getVectorNumElements()); return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, &Ops[0], Ops.size()); @@ -3871,8 +3871,8 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { if (SrcEltVT.isFloatingPoint()) { // Convert the input float vector to a int vector where the elements are the // same sizes. - assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); - MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); + assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!"); + EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits()); BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); SrcEltVT = IntVT; } @@ -3880,8 +3880,8 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { // Now we know the input is an integer vector. If the output is a FP type, // convert to integer first, then to FP of the right size. if (DstEltVT.isFloatingPoint()) { - assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); - MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); + assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!"); + EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits()); SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); // Next, convert to FP elements of the same size. @@ -3917,7 +3917,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); } - MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); + EVT VT = EVT::getVectorVT(DstEltVT, Ops.size()); return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, &Ops[0], Ops.size()); } @@ -3926,7 +3926,7 @@ ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { // turns into multiple outputs. bool isS2V = ISD::isScalarToVector(BV); unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; - MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); + EVT VT = EVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); SmallVector<SDValue, 8> Ops; for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { @@ -3963,7 +3963,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -3972,7 +3972,7 @@ SDValue DAGCombiner::visitFADD(SDNode *N) { } // fold (fadd c1, c2) -> (fadd c1, c2) - if (N0CFP && N1CFP && VT != MVT::ppcf128) + if (N0CFP && N1CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); // canonicalize constant to RHS if (N0CFP && !N1CFP) @@ -4004,7 +4004,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -4013,7 +4013,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) { } // fold (fsub c1, c2) -> c1-c2 - if (N0CFP && N1CFP && VT != MVT::ppcf128) + if (N0CFP && N1CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); // fold (fsub A, 0) -> A if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) @@ -4038,7 +4038,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -4047,7 +4047,7 @@ SDValue DAGCombiner::visitFMUL(SDNode *N) { } // fold (fmul c1, c2) -> c1*c2 - if (N0CFP && N1CFP && VT != MVT::ppcf128) + if (N0CFP && N1CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); // canonicalize constant to RHS if (N0CFP && !N1CFP) @@ -4093,7 +4093,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold vector ops if (VT.isVector()) { @@ -4102,7 +4102,7 @@ SDValue DAGCombiner::visitFDIV(SDNode *N) { } // fold (fdiv c1, c2) -> c1/c2 - if (N0CFP && N1CFP && VT != MVT::ppcf128) + if (N0CFP && N1CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); @@ -4126,10 +4126,10 @@ SDValue DAGCombiner::visitFREM(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (frem c1, c2) -> fmod(c1,c2) - if (N0CFP && N1CFP && VT != MVT::ppcf128) + if (N0CFP && N1CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); return SDValue(); @@ -4140,9 +4140,9 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); - if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold + if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); if (N1CFP) { @@ -4188,11 +4188,11 @@ SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); - MVT VT = N->getValueType(0); - MVT OpVT = N0.getValueType(); + EVT VT = N->getValueType(0); + EVT OpVT = N0.getValueType(); // fold (sint_to_fp c1) -> c1fp - if (N0C && OpVT != MVT::ppcf128) + if (N0C && OpVT != EVT::ppcf128) return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); // If the input is a legal type, and SINT_TO_FP is not legal on this target, @@ -4210,11 +4210,11 @@ SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); - MVT VT = N->getValueType(0); - MVT OpVT = N0.getValueType(); + EVT VT = N->getValueType(0); + EVT OpVT = N0.getValueType(); // fold (uint_to_fp c1) -> c1fp - if (N0C && OpVT != MVT::ppcf128) + if (N0C && OpVT != EVT::ppcf128) return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); // If the input is a legal type, and UINT_TO_FP is not legal on this target, @@ -4232,7 +4232,7 @@ SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (fp_to_sint c1fp) -> c1 if (N0CFP) @@ -4244,10 +4244,10 @@ SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (fp_to_uint c1fp) -> c1 - if (N0CFP && VT != MVT::ppcf128) + if (N0CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); return SDValue(); @@ -4257,10 +4257,10 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (fp_round c1fp) -> c1fp - if (N0CFP && N0.getValueType() != MVT::ppcf128) + if (N0CFP && N0.getValueType() != EVT::ppcf128) return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); // fold (fp_round (fp_extend x)) -> x @@ -4290,8 +4290,8 @@ SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { SDValue N0 = N->getOperand(0); - MVT VT = N->getValueType(0); - MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + EVT VT = N->getValueType(0); + EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); // fold (fp_round_inreg c1fp) -> c1fp @@ -4306,7 +4306,7 @@ SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. if (N->hasOneUse() && @@ -4314,7 +4314,7 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { return SDValue(); // fold (fp_extend c1fp) -> c1fp - if (N0CFP && VT != MVT::ppcf128) + if (N0CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the @@ -4363,7 +4363,7 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) { N0.getOperand(0).getValueType().isInteger() && !N0.getOperand(0).getValueType().isVector()) { SDValue Int = N0.getOperand(0); - MVT IntVT = Int.getValueType(); + EVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); @@ -4379,10 +4379,10 @@ SDValue DAGCombiner::visitFNEG(SDNode *N) { SDValue DAGCombiner::visitFABS(SDNode *N) { SDValue N0 = N->getOperand(0); ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // fold (fabs c1) -> fabs(c1) - if (N0CFP && VT != MVT::ppcf128) + if (N0CFP && VT != EVT::ppcf128) return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); // fold (fabs (fabs x)) -> (fabs x) if (N0.getOpcode() == ISD::FABS) @@ -4398,7 +4398,7 @@ SDValue DAGCombiner::visitFABS(SDNode *N) { N0.getOperand(0).getValueType().isInteger() && !N0.getOperand(0).getValueType().isVector()) { SDValue Int = N0.getOperand(0); - MVT IntVT = Int.getValueType(); + EVT IntVT = Int.getValueType(); if (IntVT.isInteger() && !IntVT.isVector()) { Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); @@ -4422,12 +4422,12 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) { return Chain; // unconditional branch if (N1C && N1C->getAPIntValue() == 1) - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); + return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2); // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal // on the target. if (N1.getOpcode() == ISD::SETCC && - TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { - return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, + TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) { + return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other, Chain, N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2); } @@ -4475,7 +4475,7 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) { removeFromWorkList(N1.getNode()); DAG.DeleteNode(N1.getNode()); return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), - MVT::Other, Chain, SetCC, N2); + EVT::Other, Chain, SetCC, N2); } } } @@ -4500,7 +4500,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) { // fold br_cc true, dest -> br dest (unconditional branch) if (SCCC && !SCCC->isNullValue()) - return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, + return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, N->getOperand(0), N->getOperand(4)); // fold br_cc false, dest -> unconditional fall through if (SCCC && SCCC->isNullValue()) @@ -4508,7 +4508,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) { // fold to a simpler setcc if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) - return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, + return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other, N->getOperand(0), Simp.getOperand(2), Simp.getOperand(0), Simp.getOperand(1), N->getOperand(4)); @@ -4528,7 +4528,7 @@ bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { bool isLoad = true; SDValue Ptr; - MVT VT; + EVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { if (LD->isIndexed()) return false; @@ -4653,7 +4653,7 @@ bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { bool isLoad = true; SDValue Ptr; - MVT VT; + EVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { if (LD->isIndexed()) return false; @@ -4843,7 +4843,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { // the updated indexed value in case of indexed loads), change uses of the // chain value into uses of the chain input (i.e. delete the dead load). if (!LD->isVolatile()) { - if (N->getValueType(1) == MVT::Other) { + if (N->getValueType(1) == EVT::Other) { // Unindexed loads. if (N->hasNUsesOfValue(0, 0)) { // It's not safe to use the two value CombineTo variant here. e.g. @@ -4867,7 +4867,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { } } else { // Indexed loads. - assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); + assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?"); if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { SDValue Undef = DAG.getUNDEF(N->getValueType(0)); DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); @@ -4926,7 +4926,7 @@ SDValue DAGCombiner::visitLOAD(SDNode *N) { // Create token factor to keep old chain connected. SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), - MVT::Other, Chain, ReplLoad.getValue(1)); + EVT::Other, Chain, ReplLoad.getValue(1)); // Replace uses with load result and token factor. Don't add users // to work list. @@ -4954,7 +4954,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { SDValue Chain = ST->getChain(); SDValue Value = ST->getValue(); SDValue Ptr = ST->getBasePtr(); - MVT VT = Value.getValueType(); + EVT VT = Value.getValueType(); if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) return SDValue(); @@ -4981,12 +4981,12 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { unsigned ShAmt = Imm.countTrailingZeros(); unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; unsigned NewBW = NextPowerOf2(MSB - ShAmt); - MVT NewVT = MVT::getIntegerVT(NewBW); + EVT NewVT = EVT::getIntegerVT(NewBW); while (NewBW < BitWidth && !(TLI.isOperationLegalOrCustom(Opc, NewVT) && TLI.isNarrowingProfitable(VT, NewVT))) { NewBW = NextPowerOf2(NewBW); - NewVT = MVT::getIntegerVT(NewBW); + NewVT = EVT::getIntegerVT(NewBW); } if (NewBW >= BitWidth) return SDValue(); @@ -5008,7 +5008,7 @@ SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); if (NewAlign < - TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT())) + TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT())) return SDValue(); SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), @@ -5061,9 +5061,9 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && ST->isUnindexed()) { unsigned OrigAlign = ST->getAlignment(); - MVT SVT = Value.getOperand(0).getValueType(); + EVT SVT = Value.getOperand(0).getValueType(); unsigned Align = TLI.getTargetData()-> - getABITypeAlignment(SVT.getTypeForMVT()); + getABITypeAlignment(SVT.getTypeForEVT()); if (Align <= OrigAlign && ((!LegalOperations && !ST->isVolatile()) || TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) @@ -5082,40 +5082,40 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue Tmp; switch (CFP->getValueType(0).getSimpleVT()) { default: llvm_unreachable("Unknown FP type"); - case MVT::f80: // We don't do this for these yet. - case MVT::f128: - case MVT::ppcf128: + case EVT::f80: // We don't do this for these yet. + case EVT::f128: + case EVT::ppcf128: break; - case MVT::f32: - if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && + case EVT::f32: + if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations && !ST->isVolatile()) || - TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { + TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) { Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). - bitcastToAPInt().getZExtValue(), MVT::i32); + bitcastToAPInt().getZExtValue(), EVT::i32); return DAG.getStore(Chain, N->getDebugLoc(), Tmp, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } break; - case MVT::f64: - if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && + case EVT::f64: + if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations && !ST->isVolatile()) || - TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { + TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) { Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). - getZExtValue(), MVT::i64); + getZExtValue(), EVT::i64); return DAG.getStore(Chain, N->getDebugLoc(), Tmp, Ptr, ST->getSrcValue(), ST->getSrcValueOffset(), ST->isVolatile(), ST->getAlignment()); } else if (!ST->isVolatile() && - TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { + TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) { // Many FP stores are not made apparent until after legalize, e.g. for // argument passing. Since this is so common, custom legalize the // 64-bit integer store into two 32-bit stores. uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); - SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); - SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); + SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32); + SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32); if (TLI.isBigEndian()) std::swap(Lo, Hi); int SVOffset = ST->getSrcValueOffset(); @@ -5133,7 +5133,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, Ptr, ST->getSrcValue(), SVOffset, isVolatile, Alignment); - return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, + return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other, St0, St1); } @@ -5163,7 +5163,7 @@ SDValue DAGCombiner::visitSTORE(SDNode *N) { // Create token to keep both nodes around. SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), - MVT::Other, Chain, ReplStore); + EVT::Other, Chain, ReplStore); // Don't add users to work list. return CombineTo(N, Token, false); @@ -5248,8 +5248,8 @@ SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { // BUILD_VECTOR with undef elements and the inserted element. if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && isa<ConstantSDNode>(EltNo)) { - MVT VT = InVec.getValueType(); - MVT EVT = VT.getVectorElementType(); + EVT VT = InVec.getValueType(); + EVT EVT = VT.getVectorElementType(); unsigned NElts = VT.getVectorNumElements(); SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); @@ -5269,7 +5269,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { // If the operand is wider than the vector element type then it is implicitly // truncated. Make that explicit here. - MVT EltVT = InVec.getValueType().getVectorElementType(); + EVT EltVT = InVec.getValueType().getVectorElementType(); SDValue InOp = InVec.getOperand(0); if (InOp.getValueType() != EltVT) return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); @@ -5289,18 +5289,18 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); bool NewLoad = false; bool BCNumEltsChanged = false; - MVT VT = InVec.getValueType(); - MVT EVT = VT.getVectorElementType(); - MVT LVT = EVT; + EVT VT = InVec.getValueType(); + EVT ExtVT = VT.getVectorElementType(); + EVT LVT = ExtVT; if (InVec.getOpcode() == ISD::BIT_CONVERT) { - MVT BCVT = InVec.getOperand(0).getValueType(); - if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) + EVT BCVT = InVec.getOperand(0).getValueType(); + if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) return SDValue(); if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) BCNumEltsChanged = true; InVec = InVec.getOperand(0); - EVT = BCVT.getVectorElementType(); + ExtVT = BCVT.getVectorElementType(); NewLoad = true; } @@ -5309,7 +5309,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { if (ISD::isNormalLoad(InVec.getNode())) { LN0 = cast<LoadSDNode>(InVec); } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && - InVec.getOperand(0).getValueType() == EVT && + InVec.getOperand(0).getValueType() == ExtVT && ISD::isNormalLoad(InVec.getOperand(0).getNode())) { LN0 = cast<LoadSDNode>(InVec.getOperand(0)); } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { @@ -5343,7 +5343,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { // Check the resultant load doesn't need a higher alignment than the // original load. unsigned NewAlign = - TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT()); + TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT()); if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) return SDValue(); @@ -5354,7 +5354,7 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDValue NewPtr = LN0->getBasePtr(); if (Elt) { unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; - MVT PtrType = NewPtr.getValueType(); + EVT PtrType = NewPtr.getValueType(); if (TLI.isBigEndian()) PtrOff = VT.getSizeInBits() / 8 - PtrOff; NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, @@ -5371,8 +5371,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { unsigned NumInScalars = N->getNumOperands(); - MVT VT = N->getValueType(0); - MVT EltType = VT.getVectorElementType(); + EVT VT = N->getValueType(0); + EVT EltType = VT.getVectorElementType(); // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from @@ -5469,7 +5469,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { return SDValue(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); unsigned NumElts = VT.getVectorNumElements(); SDValue N0 = N->getOperand(0); @@ -5531,7 +5531,7 @@ SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { /// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> /// vector_shuffle V, Zero, <0, 4, 2, 4> SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); @@ -5554,12 +5554,12 @@ SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { } // Let's see if the target supports this vector_shuffle. - MVT RVT = RHS.getValueType(); + EVT RVT = RHS.getValueType(); if (!TLI.isVectorClearMaskLegal(Indices, RVT)) return SDValue(); // Return the new VECTOR_SHUFFLE node. - MVT EVT = RVT.getVectorElementType(); + EVT EVT = RVT.getVectorElementType(); SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), DAG.getConstant(0, EVT)); SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), @@ -5580,10 +5580,10 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { // things. Simplifying them may result in a loss of legality. if (LegalOperations) return SDValue(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); - MVT EltType = VT.getVectorElementType(); + EVT EltType = VT.getVectorElementType(); SDValue LHS = N->getOperand(0); SDValue RHS = N->getOperand(1); SDValue Shuffle = XformToShuffleWithZero(N); @@ -5626,7 +5626,7 @@ SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { } if (Ops.size() == LHS.getNumOperands()) { - MVT VT = LHS.getValueType(); + EVT VT = LHS.getValueType(); return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &Ops[0], Ops.size()); } @@ -5765,7 +5765,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, // (x ? y : y) -> y. if (N2 == N3) return N2; - MVT VT = N2.getValueType(); + EVT VT = N2.getValueType(); ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); @@ -5857,8 +5857,8 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, N2.getValueType().isInteger() && (N1C->isNullValue() || // (a < 0) ? b : 0 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 - MVT XType = N0.getValueType(); - MVT AType = N2.getValueType(); + EVT XType = N0.getValueType(); + EVT AType = N2.getValueType(); if (XType.bitsGE(AType)) { // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a // single-bit constant. @@ -5916,7 +5916,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), N2.getValueType(), SCC); } else { - SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); + SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC); Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), N2.getValueType(), SCC); } @@ -5937,7 +5937,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, // FIXME: Turn all of these into setcc if setcc if setcc is legal // otherwise, go ahead with the folds. if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { - MVT XType = N0.getValueType(); + EVT XType = N0.getValueType(); if (!LegalOperations || TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); @@ -5979,7 +5979,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { - MVT XType = N0.getValueType(); + EVT XType = N0.getValueType(); SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, DAG.getConstant(XType.getSizeInBits()-1, getShiftAmountTy())); @@ -5994,7 +5994,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { - MVT XType = N0.getValueType(); + EVT XType = N0.getValueType(); if (SubC->isNullValue() && XType.isInteger()) { SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, @@ -6013,7 +6013,7 @@ SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, } /// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. -SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, +SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, DebugLoc DL, bool foldBooleans) { TargetLowering::DAGCombinerInfo @@ -6223,7 +6223,7 @@ SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { } // Construct a custom tailored token factor. - SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, + SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other, &Aliases[0], Aliases.size()); // Make sure the old chain gets cleaned up. diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp index e3eed28593..f4edc1a30f 100644 --- a/lib/CodeGen/SelectionDAG/FastISel.cpp +++ b/lib/CodeGen/SelectionDAG/FastISel.cpp @@ -57,7 +57,7 @@ using namespace llvm; unsigned FastISel::getRegForValue(Value *V) { - MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); + EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true); // Don't handle non-simple values in FastISel. if (!RealVT.isSimple()) return 0; @@ -65,10 +65,10 @@ unsigned FastISel::getRegForValue(Value *V) { // Ignore illegal types. We must do this before looking up the value // in ValueMap because Arguments are given virtual registers regardless // of whether FastISel can handle them. - MVT::SimpleValueType VT = RealVT.getSimpleVT(); + EVT::SimpleValueType VT = RealVT.getSimpleVT(); if (!TLI.isTypeLegal(VT)) { - // Promote MVT::i1 to a legal type though, because it's common and easy. - if (VT == MVT::i1) + // Promote EVT::i1 to a legal type though, because it's common and easy. + if (VT == EVT::i1) VT = TLI.getTypeToTransformTo(VT).getSimpleVT(); else return 0; @@ -98,7 +98,7 @@ unsigned FastISel::getRegForValue(Value *V) { if (!Reg) { const APFloat &Flt = CF->getValueAPF(); - MVT IntVT = TLI.getPointerTy(); + EVT IntVT = TLI.getPointerTy(); uint64_t x[2]; uint32_t IntBitWidth = IntVT.getSizeInBits(); @@ -174,8 +174,8 @@ unsigned FastISel::getRegForGEPIndex(Value *Idx) { return 0; // If the index is smaller or larger than intptr_t, truncate or extend it. - MVT PtrVT = TLI.getPointerTy(); - MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false); + EVT PtrVT = TLI.getPointerTy(); + EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false); if (IdxVT.bitsLT(PtrVT)) IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(), ISD::SIGN_EXTEND, IdxN); @@ -189,8 +189,8 @@ unsigned FastISel::getRegForGEPIndex(Value *Idx) { /// which has an opcode which directly corresponds to the given ISD opcode. /// bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { - MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !VT.isSimple()) + EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true); + if (VT == EVT::Other || !VT.isSimple()) // Unhandled type. Halt "fast" selection and bail. return false; @@ -199,9 +199,9 @@ bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) { // under the assumption that i64 won't be used if the target doesn't // support it. if (!TLI.isTypeLegal(VT)) { - // MVT::i1 is special. Allow AND, OR, or XOR because they + // EVT::i1 is special. Allow AND, OR, or XOR because they // don't require additional zeroing, which makes them easy. - if (VT == MVT::i1 && + if (VT == EVT::i1 && (ISDOpcode == ISD::AND || ISDOpcode == ISD::OR || ISDOpcode == ISD::XOR)) VT = TLI.getTypeToTransformTo(VT); @@ -261,7 +261,7 @@ bool FastISel::SelectGetElementPtr(User *I) { return false; const Type *Ty = I->getOperand(0)->getType(); - MVT::SimpleValueType VT = TLI.getPointerTy(); + EVT::SimpleValueType VT = TLI.getPointerTy(); for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end(); OI != E; ++OI) { Value *Idx = *OI; @@ -432,7 +432,7 @@ bool FastISel::SelectCall(User *I) { return true; } case Intrinsic::eh_exception: { - MVT VT = TLI.getValueType(I->getType()); + EVT VT = TLI.getValueType(I->getType()); switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) { default: break; case TargetLowering::Expand: { @@ -452,12 +452,12 @@ bool FastISel::SelectCall(User *I) { } case Intrinsic::eh_selector_i32: case Intrinsic::eh_selector_i64: { - MVT VT = TLI.getValueType(I->getType()); + EVT VT = TLI.getValueType(I->getType()); switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) { default: break; case TargetLowering::Expand: { - MVT VT = (IID == Intrinsic::eh_selector_i32 ? - MVT::i32 : MVT::i64); + EVT VT = (IID == Intrinsic::eh_selector_i32 ? + EVT::i32 : EVT::i64); if (MMI) { if (MBB->isLandingPad()) @@ -494,11 +494,11 @@ bool FastISel::SelectCall(User *I) { } bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { - MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(I->getType()); + EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(I->getType()); - if (SrcVT == MVT::Other || !SrcVT.isSimple() || - DstVT == MVT::Other || !DstVT.isSimple()) + if (SrcVT == EVT::Other || !SrcVT.isSimple() || + DstVT == EVT::Other || !DstVT.isSimple()) // Unhandled type. Halt "fast" selection and bail. return false; @@ -506,7 +506,7 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { // it may be i1 if we're doing a truncate because that's // easy and somewhat common. if (!TLI.isTypeLegal(DstVT)) - if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE) + if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE) // Unhandled type. Halt "fast" selection and bail. return false; @@ -514,7 +514,7 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { // it may be i1 if we're doing zero-extension because that's // easy and somewhat common. if (!TLI.isTypeLegal(SrcVT)) - if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND) + if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND) // Unhandled type. Halt "fast" selection and bail. return false; @@ -524,14 +524,14 @@ bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) { return false; // If the operand is i1, arrange for the high bits in the register to be zero. - if (SrcVT == MVT::i1) { + if (SrcVT == EVT::i1) { SrcVT = TLI.getTypeToTransformTo(SrcVT); InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg); if (!InputReg) return false; } // If the result is i1, truncate to the target's type for i1 first. - if (DstVT == MVT::i1) + if (DstVT == EVT::i1) DstVT = TLI.getTypeToTransformTo(DstVT); unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(), @@ -556,11 +556,11 @@ bool FastISel::SelectBitCast(User *I) { } // Bitcasts of other values become reg-reg copies or BIT_CONVERT operators. - MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(I->getType()); + EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(I->getType()); - if (SrcVT == MVT::Other || !SrcVT.isSimple() || - DstVT == MVT::Other || !DstVT.isSimple() || + if (SrcVT == EVT::Other || !SrcVT.isSimple() || + DstVT == EVT::Other || !DstVT.isSimple() || !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) // Unhandled type. Halt "fast" selection and bail. return false; @@ -710,8 +710,8 @@ FastISel::SelectOperator(User *I, unsigned Opcode) { case Instruction::IntToPtr: // Deliberate fall-through. case Instruction::PtrToInt: { - MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(I->getType()); + EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(I->getType()); if (DstVT.bitsGT(SrcVT)) return SelectCast(I, ISD::ZERO_EXTEND); if (DstVT.bitsLT(SrcVT)) @@ -759,45 +759,45 @@ FastISel::FastISel(MachineFunction &mf, FastISel::~FastISel() {} -unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType) { return 0; } -unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, unsigned /*Op0*/) { return 0; } -unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, unsigned /*Op0*/, unsigned /*Op0*/) { return 0; } -unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, uint64_t /*Imm*/) { return 0; } -unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, ConstantFP * /*FPImm*/) { return 0; } -unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, unsigned /*Op0*/, uint64_t /*Imm*/) { return 0; } -unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, unsigned /*Op0*/, ConstantFP * /*FPImm*/) { return 0; } -unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, +unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType, ISD::NodeType, unsigned /*Op0*/, unsigned /*Op1*/, uint64_t /*Imm*/) { @@ -808,9 +808,9 @@ unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType, /// to emit an instruction with an immediate operand using FastEmit_ri. /// If that fails, it materializes the immediate into a register and try /// FastEmit_rr instead. -unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, +unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode, unsigned Op0, uint64_t Imm, - MVT::SimpleValueType ImmType) { + EVT::SimpleValueType ImmType) { // First check if immediate type is legal. If not, we can't use the ri form. unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm); if (ResultReg != 0) @@ -825,9 +825,9 @@ unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode, /// to emit an instruction with a floating-point immediate operand using /// FastEmit_rf. If that fails, it materializes the immediate into a register /// and try FastEmit_rr instead. -unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, +unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode, unsigned Op0, ConstantFP *FPImm, - MVT::SimpleValueType ImmType) { + EVT::SimpleValueType ImmType) { // First check if immediate type is legal. If not, we can't use the rf form. unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm); if (ResultReg != 0) @@ -843,7 +843,7 @@ unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode, // be replaced by code that creates a load from a constant-pool entry, // which will require some target-specific work. const APFloat &Flt = FPImm->getValueAPF(); - MVT IntVT = TLI.getPointerTy(); + EVT IntVT = TLI.getPointerTy(); uint64_t x[2]; uint32_t IntBitWidth = IntVT.getSizeInBits(); @@ -988,7 +988,7 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode, return ResultReg; } -unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, +unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT, unsigned Op0, uint32_t Idx) { const TargetRegisterClass* RC = MRI.getRegClass(Op0); @@ -1009,6 +1009,6 @@ unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT, /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op /// with all but the least significant bit set to zero. -unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) { +unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) { return FastEmit_ri(VT, VT, ISD::AND, Op, 1); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 4be5b3d663..de445ed261 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -100,13 +100,13 @@ public: /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. - LegalizeAction getTypeAction(MVT VT) const { + LegalizeAction getTypeAction(EVT VT) const { return (LegalizeAction)ValueTypeActions.getTypeAction(VT); } /// isTypeLegal - Return true if this type is legal on this target. /// - bool isTypeLegal(MVT VT) const { + bool isTypeLegal(EVT VT) const { return getTypeAction(VT) == Legal; } @@ -133,14 +133,14 @@ private: /// performs the same shuffe in terms of order or result bytes, but on a type /// whose vector element type is narrower than the original shuffle type. /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> - SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, + SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, SDValue N1, SDValue N2, SmallVectorImpl<int> &Mask) const; bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest, SmallPtrSet<SDNode*, 32> &NodesLeadingTo); - void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, + void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, DebugLoc dl); SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); @@ -151,18 +151,18 @@ private: RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64, RTLIB::Libcall Call_I128); - SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl); + SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); SDValue ExpandBUILD_VECTOR(SDNode *Node); SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); SDValue ExpandDBG_STOPPOINT(SDNode *Node); void ExpandDYNAMIC_STACKALLOC(SDNode *Node, SmallVectorImpl<SDValue> &Results); SDValue ExpandFCOPYSIGN(SDNode *Node); - SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT, + SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, DebugLoc dl); - SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned, + SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, DebugLoc dl); - SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned, + SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, DebugLoc dl); SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); @@ -181,10 +181,10 @@ private: /// whose vector element type is narrower than the original shuffle type. /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> SDValue -SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl, +SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, SDValue N1, SDValue N2, SmallVectorImpl<int> &Mask) const { - MVT EltVT = NVT.getVectorElementType(); + EVT EltVT = NVT.getVectorElementType(); unsigned NumMaskElts = VT.getVectorNumElements(); unsigned NumDestElts = NVT.getVectorNumElements(); unsigned NumEltsGrowth = NumDestElts / NumMaskElts; @@ -213,7 +213,7 @@ SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, CodeGenOpt::Level ol) : TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol), ValueTypeActions(TLI.getValueTypeActions()) { - assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && + assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); } @@ -254,19 +254,19 @@ static SDNode *FindCallEndFromCallStart(SDNode *Node) { // The chain is usually at the end. SDValue TheChain(Node, Node->getNumValues()-1); - if (TheChain.getValueType() != MVT::Other) { + if (TheChain.getValueType() != EVT::Other) { // Sometimes it's at the beginning. TheChain = SDValue(Node, 0); - if (TheChain.getValueType() != MVT::Other) { + if (TheChain.getValueType() != EVT::Other) { // Otherwise, hunt for it. for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i) - if (Node->getValueType(i) == MVT::Other) { + if (Node->getValueType(i) == EVT::Other) { TheChain = SDValue(Node, i); break; } // Otherwise, we walked into a node without a chain. - if (TheChain.getValueType() != MVT::Other) + if (TheChain.getValueType() != EVT::Other) return 0; } } @@ -290,7 +290,7 @@ static SDNode *FindCallStartFromCallEnd(SDNode *Node) { assert(Node && "Didn't find callseq_start for a call??"); if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; - assert(Node->getOperand(0).getValueType() == MVT::Other && + assert(Node->getOperand(0).getValueType() == EVT::Other && "Node doesn't have a token chain argument!"); return FindCallStartFromCallEnd(Node->getOperand(0).getNode()); } @@ -344,24 +344,24 @@ static SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP, // double. This shrinks FP constants and canonicalizes them for targets where // an FP extending load is the same cost as a normal load (such as on the x87 // fp stack or PPC FP unit). - MVT VT = CFP->getValueType(0); + EVT VT = CFP->getValueType(0); ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); if (!UseCP) { - assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); + assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion"); return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), - (VT == MVT::f64) ? MVT::i64 : MVT::i32); + (VT == EVT::f64) ? EVT::i64 : EVT::i32); } - MVT OrigVT = VT; - MVT SVT = VT; - while (SVT != MVT::f32) { - SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1); + EVT OrigVT = VT; + EVT SVT = VT; + while (SVT != EVT::f32) { + SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1); if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) && // Only do this if the target has a native EXTLOAD instruction from // smaller type. TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && TLI.ShouldShrinkFPConstant(OrigVT)) { - const Type *SType = SVT.getTypeForMVT(); + const Type *SType = SVT.getTypeForEVT(); LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); VT = SVT; Extend = true; @@ -386,13 +386,13 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, SDValue Chain = ST->getChain(); SDValue Ptr = ST->getBasePtr(); SDValue Val = ST->getValue(); - MVT VT = Val.getValueType(); + EVT VT = Val.getValueType(); int Alignment = ST->getAlignment(); int SVOffset = ST->getSrcValueOffset(); DebugLoc dl = ST->getDebugLoc(); if (ST->getMemoryVT().isFloatingPoint() || ST->getMemoryVT().isVector()) { - MVT intVT = MVT::getIntegerVT(VT.getSizeInBits()); + EVT intVT = EVT::getIntegerVT(VT.getSizeInBits()); if (TLI.isTypeLegal(intVT)) { // Expand to a bitconvert of the value to the integer type of the // same size, then a (misaligned) int store. @@ -403,9 +403,9 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, } else { // Do a (aligned) store to a stack slot, then copy from the stack slot // to the final destination using (unaligned) integer loads and stores. - MVT StoredVT = ST->getMemoryVT(); - MVT RegVT = - TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits())); + EVT StoredVT = ST->getMemoryVT(); + EVT RegVT = + TLI.getRegisterType(EVT::getIntegerVT(StoredVT.getSizeInBits())); unsigned StoredBytes = StoredVT.getSizeInBits() / 8; unsigned RegBytes = RegVT.getSizeInBits() / 8; unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; @@ -439,7 +439,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, // The last store may be partial. Do a truncating store. On big-endian // machines this requires an extending load from the stack slot to ensure // that the bits are in the right place. - MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset)); + EVT MemVT = EVT::getIntegerVT(8 * (StoredBytes - Offset)); // Load from the stack slot. SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, @@ -450,7 +450,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, MemVT, ST->isVolatile(), MinAlign(ST->getAlignment(), Offset))); // The order of the stores doesn't matter - say it with a TokenFactor. - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0], Stores.size()); } } @@ -458,8 +458,8 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, !ST->getMemoryVT().isVector() && "Unaligned store of unknown type."); // Get the half-size VT - MVT NewStoredVT = - (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); + EVT NewStoredVT = + (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1); int NumBits = NewStoredVT.getSizeInBits(); int IncrementSize = NumBits / 8; @@ -480,7 +480,7 @@ SDValue ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, ST->getSrcValue(), SVOffset + IncrementSize, NewStoredVT, ST->isVolatile(), Alignment); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2); } /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. @@ -490,11 +490,11 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, int SVOffset = LD->getSrcValueOffset(); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); - MVT VT = LD->getValueType(0); - MVT LoadedVT = LD->getMemoryVT(); + EVT VT = LD->getValueType(0); + EVT LoadedVT = LD->getMemoryVT(); DebugLoc dl = LD->getDebugLoc(); if (VT.isFloatingPoint() || VT.isVector()) { - MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits()); + EVT intVT = EVT::getIntegerVT(LoadedVT.getSizeInBits()); if (TLI.isTypeLegal(intVT)) { // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. @@ -510,7 +510,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, } else { // Copy the value to a (aligned) stack slot using (unaligned) integer // loads and stores, then do a (aligned) load from the stack slot. - MVT RegVT = TLI.getRegisterType(intVT); + EVT RegVT = TLI.getRegisterType(intVT); unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; unsigned RegBytes = RegVT.getSizeInBits() / 8; unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; @@ -540,7 +540,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, } // The last copy may be partial. Do an extending load. - MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset)); + EVT MemVT = EVT::getIntegerVT(8 * (LoadedBytes - Offset)); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, LD->getSrcValue(), SVOffset + Offset, MemVT, LD->isVolatile(), @@ -552,7 +552,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, NULL, 0, MemVT)); // The order of the stores doesn't matter - say it with a TokenFactor. - SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0], Stores.size()); // Finally, perform the original load only redirected to the stack slot. @@ -570,8 +570,8 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, // Compute the new VT that is half the size of the old one. This is an // integer MVT. unsigned NumBits = LoadedVT.getSizeInBits(); - MVT NewLoadedVT; - NewLoadedVT = MVT::getIntegerVT(NumBits/2); + EVT NewLoadedVT; + NewLoadedVT = EVT::getIntegerVT(NumBits/2); NumBits >>= 1; unsigned Alignment = LD->getAlignment(); @@ -607,7 +607,7 @@ SDValue ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); - SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); SDValue Ops[] = { Result, TF }; @@ -631,10 +631,10 @@ PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, // with a "move to register" or "extload into register" instruction, then // permute it into place, if the idx is a constant and if the idx is // supported by the target. - MVT VT = Tmp1.getValueType(); - MVT EltVT = VT.getVectorElementType(); - MVT IdxVT = Tmp3.getValueType(); - MVT PtrVT = TLI.getPointerTy(); + EVT VT = Tmp1.getValueType(); + EVT EltVT = VT.getVectorElementType(); + EVT IdxVT = Tmp3.getValueType(); + EVT PtrVT = TLI.getPointerTy(); SDValue StackPtr = DAG.CreateStackTemporary(VT); int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); @@ -665,7 +665,7 @@ ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { // SCALAR_TO_VECTOR requires that the type of the value being inserted // match the element type of the vector being created, except for // integers in which case the inserted value can be over width. - MVT EltVT = Vec.getValueType().getVectorElementType(); + EVT EltVT = Vec.getValueType().getVectorElementType(); if (Val.getValueType() == EltVT || (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, @@ -702,27 +702,27 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { bool isVolatile = ST->isVolatile(); DebugLoc dl = ST->getDebugLoc(); if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { - if (CFP->getValueType(0) == MVT::f32 && - getTypeAction(MVT::i32) == Legal) { + if (CFP->getValueType(0) == EVT::f32 && + getTypeAction(EVT::i32) == Legal) { Tmp3 = DAG.getConstant(CFP->getValueAPF(). bitcastToAPInt().zextOrTrunc(32), - MVT::i32); + EVT::i32); return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); - } else if (CFP->getValueType(0) == MVT::f64) { + } else if (CFP->getValueType(0) == EVT::f64) { // If this target supports 64-bit registers, do a single 64-bit store. - if (getTypeAction(MVT::i64) == Legal) { + if (getTypeAction(EVT::i64) == Legal) { Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). - zextOrTrunc(64), MVT::i64); + zextOrTrunc(64), EVT::i64); return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, isVolatile, Alignment); - } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) { + } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) { // Otherwise, if the target supports 32-bit registers, use 2 32-bit // stores. If the target supports neither 32- nor 64-bits, this // xform is certainly not worth it. const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); - SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32); - SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); + SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32); + SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32); if (TLI.isBigEndian()) std::swap(Lo, Hi); Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(), @@ -732,7 +732,7 @@ SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4, isVolatile, MinAlign(Alignment, 4U)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } } } @@ -777,7 +777,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { case ISD::INTRINSIC_VOID: case ISD::VAARG: case ISD::STACKSAVE: - Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); + Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other); break; case ISD::SINT_TO_FP: case ISD::UINT_TO_FP: @@ -787,7 +787,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { break; case ISD::FP_ROUND_INREG: case ISD::SIGN_EXTEND_INREG: { - MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); + EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); Action = TLI.getOperationAction(Node->getOpcode(), InnerType); break; } @@ -797,7 +797,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : Node->getOpcode() == ISD::SETCC ? 2 : 1; unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; - MVT OpVT = Node->getOperand(CompareOperand).getValueType(); + EVT OpVT = Node->getOperand(CompareOperand).getValueType(); ISD::CondCode CCCode = cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); Action = TLI.getCondCodeAction(CCCode, OpVT); @@ -882,7 +882,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { case ISD::BR_CC: case ISD::BRCOND: // Branches tweak the chain to include LastCALLSEQ_END - Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0], + Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0], LastCALLSEQ_END); Ops[0] = LegalizeOp(Ops[0]); LastCALLSEQ_END = DAG.getEntryNode(); @@ -979,7 +979,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // Merge in the last call, to ensure that this call start after the last // call ended. if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) { - Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Tmp1, LastCALLSEQ_END); Tmp1 = LegalizeOp(Tmp1); } @@ -1026,7 +1026,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain. // Do not try to legalize the target-specific arguments (#1+), except for // an optional flag input. - if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){ + if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){ if (Tmp1 != Node->getOperand(0)) { SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end()); Ops[0] = Tmp1; @@ -1058,7 +1058,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { ISD::LoadExtType ExtType = LD->getExtensionType(); if (ExtType == ISD::NON_EXTLOAD) { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset()); Tmp3 = Result.getValue(0); Tmp4 = Result.getValue(1); @@ -1070,7 +1070,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(LD->getMemoryVT().getTypeForEVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, TLI); @@ -1092,7 +1092,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // Only promote a load of vector type to another. assert(VT.isVector() && "Cannot promote this load!"); // Change base type to a different vector type. - MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); + EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), @@ -1108,7 +1108,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { AddLegalizedOperand(SDValue(Node, 1), Tmp4); return Op.getResNo() ? Tmp4 : Tmp3; } else { - MVT SrcVT = LD->getMemoryVT(); + EVT SrcVT = LD->getMemoryVT(); unsigned SrcWidth = SrcVT.getSizeInBits(); int SVOffset = LD->getSrcValueOffset(); unsigned Alignment = LD->getAlignment(); @@ -1122,12 +1122,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // tells the optimizers that those bits are undefined. It would be // nice to have an effective generic way of getting these benefits... // Until such a way is found, don't insist on promoting i1 here. - (SrcVT != MVT::i1 || - TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { + (SrcVT != EVT::i1 || + TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) { // Promote to a byte-sized load if not loading an integral number of // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. unsigned NewWidth = SrcVT.getStoreSizeInBits(); - MVT NVT = MVT::getIntegerVT(NewWidth); + EVT NVT = EVT::getIntegerVT(NewWidth); SDValue Ch; // The extra bits are guaranteed to be zero, since we stored them that @@ -1165,8 +1165,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Load size not an integral number of bytes!"); - MVT RoundVT = MVT::getIntegerVT(RoundWidth); - MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); + EVT RoundVT = EVT::getIntegerVT(RoundWidth); + EVT ExtraVT = EVT::getIntegerVT(ExtraWidth); SDValue Lo, Hi, Ch; unsigned IncrementSize; @@ -1189,7 +1189,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); // Move the top bits to the right place. @@ -1218,7 +1218,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); // Move the top bits to the right place. @@ -1253,7 +1253,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(LD->getMemoryVT().getTypeForEVT()); if (LD->getAlignment() < ABIAlignment){ Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()), DAG, TLI); @@ -1267,7 +1267,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { break; case TargetLowering::Expand: // f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND - if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) { + if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) { SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); @@ -1323,7 +1323,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2, ST->getOffset()); - MVT VT = Tmp3.getValueType(); + EVT VT = Tmp3.getValueType(); switch (TLI.getOperationAction(ISD::STORE, VT)) { default: llvm_unreachable("This action is not supported yet!"); case TargetLowering::Legal: @@ -1331,7 +1331,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(ST->getMemoryVT().getTypeForEVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, TLI); @@ -1355,14 +1355,14 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } else { Tmp3 = LegalizeOp(ST->getValue()); - MVT StVT = ST->getMemoryVT(); + EVT StVT = ST->getMemoryVT(); unsigned StWidth = StVT.getSizeInBits(); if (StWidth != StVT.getStoreSizeInBits()) { // Promote to a byte-sized store with upper bits zero if not // storing an integral number of bytes. For example, promote // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) - MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits()); + EVT NVT = EVT::getIntegerVT(StVT.getStoreSizeInBits()); Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT); Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(), SVOffset, NVT, isVolatile, Alignment); @@ -1376,8 +1376,8 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { assert(ExtraWidth < RoundWidth); assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && "Store size not an integral number of bytes!"); - MVT RoundVT = MVT::getIntegerVT(RoundWidth); - MVT ExtraVT = MVT::getIntegerVT(ExtraWidth); + EVT RoundVT = EVT::getIntegerVT(RoundWidth); + EVT ExtraVT = EVT::getIntegerVT(ExtraWidth); SDValue Lo, Hi; unsigned IncrementSize; @@ -1416,7 +1416,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { } // The order of the stores doesn't matter. - Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } else { if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() || Tmp2 != ST->getBasePtr()) @@ -1430,7 +1430,7 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) { // expand it. if (!TLI.allowsUnalignedMemoryAccesses()) { unsigned ABIAlignment = TLI.getTargetData()-> - getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(ST->getMemoryVT().getTypeForEVT()); if (ST->getAlignment() < ABIAlignment) Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG, TLI); @@ -1498,8 +1498,8 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { // aligned object on the stack, store each element into it, then load // the result as a vector. // Create the stack frame object. - MVT VT = Node->getValueType(0); - MVT OpVT = Node->getOperand(0).getValueType(); + EVT VT = Node->getValueType(0); + EVT OpVT = Node->getOperand(0).getValueType(); DebugLoc dl = Node->getDebugLoc(); SDValue FIPtr = DAG.CreateStackTemporary(VT); int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); @@ -1524,7 +1524,7 @@ SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { SDValue StoreChain; if (!Stores.empty()) // Not all undef elements? - StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0], Stores.size()); else StoreChain = DAG.getEntryNode(); @@ -1537,28 +1537,28 @@ SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { DebugLoc dl = Node->getDebugLoc(); SDValue Tmp1 = Node->getOperand(0); SDValue Tmp2 = Node->getOperand(1); - assert((Tmp2.getValueType() == MVT::f32 || - Tmp2.getValueType() == MVT::f64) && + assert((Tmp2.getValueType() == EVT::f32 || + Tmp2.getValueType() == EVT::f64) && "Ugly special-cased code!"); // Get the sign bit of the RHS. SDValue SignBit; - MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32; + EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32; if (isTypeLegal(IVT)) { SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2); } else { assert(isTypeLegal(TLI.getPointerTy()) && - (TLI.getPointerTy() == MVT::i32 || - TLI.getPointerTy() == MVT::i64) && + (TLI.getPointerTy() == EVT::i32 || + TLI.getPointerTy() == EVT::i64) && "Legal type for load?!"); SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType()); SDValue StorePtr = StackPtr, LoadPtr = StackPtr; SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0); - if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian()) + if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian()) LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), LoadPtr, DAG.getIntPtrConstant(4)); SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(), - Ch, LoadPtr, NULL, 0, MVT::i32); + Ch, LoadPtr, NULL, 0, EVT::i32); } SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), @@ -1577,8 +1577,8 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { DebugLoc dl = Node->getDebugLoc(); DwarfWriter *DW = DAG.getDwarfWriter(); bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC, - MVT::Other); - bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other); + EVT::Other); + bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other); const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node); GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit()); @@ -1592,9 +1592,9 @@ SDValue SelectionDAGLegalize::ExpandDBG_STOPPOINT(SDNode* Node) { // A bit self-referential to have DebugLoc on Debug_Loc nodes, but it // won't hurt anything. if (useDEBUG_LOC) { - return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0), - DAG.getConstant(Line, MVT::i32), - DAG.getConstant(Col, MVT::i32), + return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0), + DAG.getConstant(Line, EVT::i32), + DAG.getConstant(Col, EVT::i32), DAG.getSrcValue(CU.getGV())); } else { unsigned ID = DW->RecordSourceLine(Line, Col, CU); @@ -1611,7 +1611,7 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" " not tell us which reg is the stack pointer!"); DebugLoc dl = Node->getDebugLoc(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDValue Tmp1 = SDValue(Node, 0); SDValue Tmp2 = SDValue(Node, 1); SDValue Tmp3 = Node->getOperand(2); @@ -1644,11 +1644,11 @@ void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, /// condition code CC on the current target. This routine assumes LHS and rHS /// have already been legalized by LegalizeSetCCOperands. It expands SETCC with /// illegal condition code into AND / OR of multiple SETCC values. -void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, +void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, DebugLoc dl) { - MVT OpVT = LHS.getValueType(); + EVT OpVT = LHS.getValueType(); ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); switch (TLI.getCondCodeAction(CCCode, OpVT)) { default: llvm_unreachable("Unknown condition code action!"); @@ -1690,13 +1690,13 @@ void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT, /// a load from the stack slot to DestVT, extending it if needed. /// The resultant code need not be legal. SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, - MVT SlotVT, - MVT DestVT, + EVT SlotVT, + EVT DestVT, DebugLoc dl) { // Create the stack frame object. unsigned SrcAlign = TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). - getTypeForMVT()); + getTypeForEVT()); SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); @@ -1707,7 +1707,7 @@ SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, unsigned SlotSize = SlotVT.getSizeInBits(); unsigned DestSize = DestVT.getSizeInBits(); unsigned DestAlign = - TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT()); + TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT()); // Emit a store to the stack slot. Use a truncstore if the input value is // later than DestVT. @@ -1755,9 +1755,9 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { unsigned NumElems = Node->getNumOperands(); SDValue Value1, Value2; DebugLoc dl = Node->getDebugLoc(); - MVT VT = Node->getValueType(0); - MVT OpVT = Node->getOperand(0).getValueType(); - MVT EltVT = VT.getVectorElementType(); + EVT VT = Node->getValueType(0); + EVT OpVT = Node->getOperand(0).getValueType(); + EVT EltVT = VT.getVectorElementType(); // If the only non-undef value is the low element, turn this into a // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. @@ -1801,7 +1801,7 @@ SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); } else { assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); - const Type *OpNTy = OpVT.getTypeForMVT(); + const Type *OpNTy = OpVT.getTypeForEVT(); CV.push_back(UndefValue::get(OpNTy)); } } @@ -1854,8 +1854,8 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { - MVT ArgVT = Node->getOperand(i).getValueType(); - const Type *ArgTy = ArgVT.getTypeForMVT(); + EVT ArgVT = Node->getOperand(i).getValueType(); + const Type *ArgTy = ArgVT.getTypeForEVT(); Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; Entry.isSExt = isSigned; Entry.isZExt = !isSigned; @@ -1865,7 +1865,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, TLI.getPointerTy()); // Splice the libcall in wherever FindInputOutputChains tells us to. - const Type *RetTy = Node->getValueType(0).getTypeForMVT(); + const Type *RetTy = Node->getValueType(0).getTypeForEVT(); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 0, CallingConv::C, false, @@ -1888,10 +1888,10 @@ SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { default: llvm_unreachable("Unexpected request for libcall!"); - case MVT::f32: LC = Call_F32; break; - case MVT::f64: LC = Call_F64; break; - case MVT::f80: LC = Call_F80; break; - case MVT::ppcf128: LC = Call_PPCF128; break; + case EVT::f32: LC = Call_F32; break; + case EVT::f64: LC = Call_F64; break; + case EVT::f80: LC = Call_F80; break; + case EVT::ppcf128: LC = Call_PPCF128; break; } return ExpandLibCall(LC, Node, false); } @@ -1904,10 +1904,10 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, RTLIB::Libcall LC; switch (Node->getValueType(0).getSimpleVT()) { default: llvm_unreachable("Unexpected request for libcall!"); - case MVT::i16: LC = Call_I16; break; - case MVT::i32: LC = Call_I32; break; - case MVT::i64: LC = Call_I64; break; - case MVT::i128: LC = Call_I128; break; + case EVT::i16: LC = Call_I16; break; + case EVT::i32: LC = Call_I32; break; + case EVT::i64: LC = Call_I64; break; + case EVT::i128: LC = Call_I128; break; } return ExpandLibCall(LC, Node, isSigned); } @@ -1918,13 +1918,13 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, /// legal for the target. SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0, - MVT DestVT, + EVT DestVT, DebugLoc dl) { - if (Op0.getValueType() == MVT::i32) { + if (Op0.getValueType() == EVT::i32) { // simple 32-bit [signed|unsigned] integer to float/double expansion // Get the stack frame index of a 8 byte buffer. - SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); + SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64); // word offset constant for Hi/Lo address computation SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); @@ -1939,8 +1939,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Op0Mapped; if (isSigned) { // constant used to invert sign bit (signed to unsigned mapping) - SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); - Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); + SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32); + Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit); } else { Op0Mapped = Op0; } @@ -1948,28 +1948,28 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op0Mapped, Lo, NULL, 0); // initial hi portion of constructed double - SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); + SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32); // store the hi of the constructed double - biased exponent SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0); // load the constructed double - SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0); + SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0); // FP constant to bias correct the final result SDValue Bias = DAG.getConstantFP(isSigned ? BitsToDouble(0x4330000080000000ULL) : BitsToDouble(0x4330000000000000ULL), - MVT::f64); + EVT::f64); // subtract the bias - SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias); // final result SDValue Result; // handle final rounding - if (DestVT == MVT::f64) { + if (DestVT == EVT::f64) { // do nothing Result = Sub; - } else if (DestVT.bitsLT(MVT::f64)) { + } else if (DestVT.bitsLT(EVT::f64)) { Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (DestVT.bitsGT(MVT::f64)) { + } else if (DestVT.bitsGT(EVT::f64)) { Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); } return Result; @@ -1990,10 +1990,10 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, uint64_t FF; switch (Op0.getValueType().getSimpleVT()) { default: llvm_unreachable("Unsupported integer type!"); - case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) - case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) - case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) - case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) + case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) + case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) + case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) + case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) } if (TLI.isLittleEndian()) FF <<= 32; Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF); @@ -2003,8 +2003,8 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); Alignment = std::min(Alignment, 4u); SDValue FudgeInReg; - if (DestVT == MVT::f32) - FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, + if (DestVT == EVT::f32) + FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, false, Alignment); else { @@ -2012,7 +2012,7 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, DAG.getEntryNode(), CPIdx, PseudoSourceValue::getConstantPool(), 0, - MVT::f32, false, Alignment)); + EVT::f32, false, Alignment)); } return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); @@ -2024,17 +2024,17 @@ SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP /// operation that takes a larger input. SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, - MVT DestVT, + EVT DestVT, bool isSigned, DebugLoc dl) { // First step, figure out the appropriate *INT_TO_FP operation to use. - MVT NewInTy = LegalOp.getValueType(); + EVT NewInTy = LegalOp.getValueType(); unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1); + NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1); assert(NewInTy.isInteger() && "Ran out of possibilities!"); // If the target supports SINT_TO_FP of this type, use it. @@ -2066,17 +2066,17 @@ SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT /// operation that returns a larger result. SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, - MVT DestVT, + EVT DestVT, bool isSigned, DebugLoc dl) { // First step, figure out the appropriate FP_TO*INT operation to use. - MVT NewOutTy = DestVT; + EVT NewOutTy = DestVT; unsigned OpToUse = 0; // Scan for the appropriate larger type to use. while (1) { - NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); + NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1); assert(NewOutTy.isInteger() && "Ran out of possibilities!"); if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { @@ -2104,16 +2104,16 @@ SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. /// SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { - MVT VT = Op.getValueType(); - MVT SHVT = TLI.getShiftAmountTy(); + EVT VT = Op.getValueType(); + EVT SHVT = TLI.getShiftAmountTy(); SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; switch (VT.getSimpleVT()) { default: llvm_unreachable("Unhandled Expand type in BSWAP!"); - case MVT::i16: + case EVT::i16: Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); - case MVT::i32: + case EVT::i32: Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); @@ -2123,7 +2123,7 @@ SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); - case MVT::i64: + case EVT::i64: Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); @@ -2160,8 +2160,8 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL, 0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL }; - MVT VT = Op.getValueType(); - MVT ShVT = TLI.getShiftAmountTy(); + EVT VT = Op.getValueType(); + EVT ShVT = TLI.getShiftAmountTy(); unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { //x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8]) @@ -2187,8 +2187,8 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, // return popcount(~x); // // but see also: http://www.hackersdelight.org/HDcode/nlz.cc - MVT VT = Op.getValueType(); - MVT ShVT = TLI.getShiftAmountTy(); + EVT VT = Op.getValueType(); + EVT ShVT = TLI.getShiftAmountTy(); unsigned len = VT.getSizeInBits(); for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); @@ -2203,7 +2203,7 @@ SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, // unless the target has ctlz but not ctpop, in which case we use: // { return 32 - nlz(~x & (x-1)); } // see also http://www.hackersdelight.org/HDcode/ntz.cc - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, DAG.getNOT(dl, Op, VT), DAG.getNode(ISD::SUB, dl, VT, Op, @@ -2261,7 +2261,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, Results.push_back(Node->getOperand(i)); break; case ISD::UNDEF: { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); if (VT.isInteger()) Results.push_back(DAG.getConstant(0, VT)); else if (VT.isFloatingPoint()) @@ -2297,7 +2297,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, case ISD::SIGN_EXTEND_INREG: { // NOTE: we could fall back on load/store here too for targets without // SAR. However, it is doubtful that any exist. - MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); + EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); unsigned BitsDiff = Node->getValueType(0).getSizeInBits() - ExtraVT.getSizeInBits(); SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy()); @@ -2314,7 +2314,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, // NOTE: there is a choice here between constantly creating new stack // slots and always reusing the same one. We currently always create // new ones, as reuse may inhibit scheduling. - MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); + EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, Node->getValueType(0), dl); Results.push_back(Tmp1); @@ -2328,8 +2328,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; case ISD::FP_TO_UINT: { SDValue True, False; - MVT VT = Node->getOperand(0).getValueType(); - MVT NVT = Node->getValueType(0); + EVT VT = Node->getOperand(0).getValueType(); + EVT NVT = Node->getValueType(0); const uint64_t zero[] = {0, 0}; APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero)); APInt x = APInt::getSignBit(NVT.getSizeInBits()); @@ -2350,14 +2350,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, } case ISD::VAARG: { const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); Tmp1 = Node->getOperand(0); Tmp2 = Node->getOperand(1); SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0); // Increment the pointer, VAList, to the next vaarg Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, DAG.getConstant(TLI.getTargetData()-> - getTypeAllocSize(VT.getTypeForMVT()), + getTypeAllocSize(VT.getTypeForEVT()), TLI.getPointerTy())); // Store the incremented VAList to the legalized pointer Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0); @@ -2405,8 +2405,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, SmallVector<int, 8> Mask; cast<ShuffleVectorSDNode>(Node)->getMask(Mask); - MVT VT = Node->getValueType(0); - MVT EltVT = VT.getVectorElementType(); + EVT VT = Node->getValueType(0); + EVT EltVT = VT.getVectorElementType(); unsigned NumElems = VT.getVectorNumElements(); SmallVector<SDValue, 8> Ops; for (unsigned i = 0; i != NumElems; ++i) { @@ -2429,7 +2429,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; } case ISD::EXTRACT_ELEMENT: { - MVT OpTy = Node->getOperand(0).getValueType(); + EVT OpTy = Node->getOperand(0).getValueType(); if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { // 1 -> Hi Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), @@ -2478,7 +2478,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; case ISD::FABS: { // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); Tmp1 = Node->getOperand(0); Tmp2 = DAG.getConstantFP(0.0, VT); Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), @@ -2593,7 +2593,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; } case ISD::SUB: { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && TLI.isOperationLegalOrCustom(ISD::XOR, VT) && "Don't know how to expand this subtraction!"); @@ -2605,7 +2605,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, } case ISD::UREM: case ISD::SREM: { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDVTList VTs = DAG.getVTList(VT, VT); bool isSigned = Node->getOpcode() == ISD::SREM; unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; @@ -2633,7 +2633,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, case ISD::SDIV: { bool isSigned = Node->getOpcode() == ISD::SDIV; unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDVTList VTs = DAG.getVTList(VT, VT); if (TLI.isOperationLegalOrCustom(DivRemOpc, VT)) Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), @@ -2651,7 +2651,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, case ISD::MULHS: { unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : ISD::SMUL_LOHI; - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDVTList VTs = DAG.getVTList(VT, VT); assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && "If this wasn't legal, it shouldn't have been created!"); @@ -2661,7 +2661,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; } case ISD::MUL: { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDVTList VTs = DAG.getVTList(VT, VT); // See if multiply or divide can be lowered using two-result operations. // We just need the low half of the multiply; try both the signed @@ -2700,7 +2700,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, ISD::ADD : ISD::SUB, dl, LHS.getValueType(), LHS, RHS); Results.push_back(Sum); - MVT OType = Node->getValueType(1); + EVT OType = Node->getValueType(1); SDValue Zero = DAG.getConstant(0, LHS.getValueType()); @@ -2741,7 +2741,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, } case ISD::UMULO: case ISD::SMULO: { - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDValue LHS = Node->getOperand(0); SDValue RHS = Node->getOperand(1); SDValue BottomHalf; @@ -2757,8 +2757,8 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, RHS); TopHalf = BottomHalf.getValue(1); - } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) { - MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2); + } else if (TLI.isTypeLegal(EVT::getIntegerVT(VT.getSizeInBits() * 2))) { + EVT WideVT = EVT::getIntegerVT(VT.getSizeInBits() * 2); LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); @@ -2787,7 +2787,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, break; } case ISD::BUILD_PAIR: { - MVT PairTy = Node->getValueType(0); + EVT PairTy = Node->getValueType(0); Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, @@ -2816,14 +2816,14 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, SDValue Table = Node->getOperand(1); SDValue Index = Node->getOperand(2); - MVT PTy = TLI.getPointerTy(); + EVT PTy = TLI.getPointerTy(); MachineFunction &MF = DAG.getMachineFunction(); unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize(); Index= DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(EntrySize, PTy)); SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); - MVT MemVT = MVT::getIntegerVT(EntrySize * 8); + EVT MemVT = EVT::getIntegerVT(EntrySize * 8); SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, PseudoSourceValue::getJumpTable(), 0, MemVT); Addr = LD; @@ -2834,7 +2834,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, TLI.getPICJumpTableRelocBase(Table, DAG)); } - Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); + Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr); Results.push_back(Tmp1); break; } @@ -2844,12 +2844,12 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, Tmp1 = Node->getOperand(0); Tmp2 = Node->getOperand(1); if (Tmp2.getOpcode() == ISD::SETCC) { - Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, + Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1, Tmp2.getOperand(2), Tmp2.getOperand(0), Tmp2.getOperand(1), Node->getOperand(2)); } else { - Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, + Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1, DAG.getCondCode(ISD::SETNE), Tmp2, DAG.getConstant(0, Tmp2.getValueType()), Node->getOperand(2)); @@ -2870,7 +2870,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, // Otherwise, SETCC for the given comparison type must be completely // illegal; expand it into a SELECT_CC. - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); Results.push_back(Tmp1); @@ -2929,13 +2929,13 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node, } void SelectionDAGLegalize::PromoteNode(SDNode *Node, SmallVectorImpl<SDValue> &Results) { - MVT OVT = Node->getValueType(0); + EVT OVT = Node->getValueType(0); if (Node->getOpcode() == ISD::UINT_TO_FP || Node->getOpcode() == ISD::SINT_TO_FP || Node->getOpcode() == ISD::SETCC) { OVT = Node->getOperand(0).getValueType(); } - MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); + EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); DebugLoc dl = Node->getDebugLoc(); SDValue Tmp1, Tmp2, Tmp3; switch (Node->getOpcode()) { diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 5957e3a503..ebaf2fb4cc 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -25,16 +25,16 @@ using namespace llvm; /// GetFPLibCall - Return the right libcall for the given floating point type. -static RTLIB::Libcall GetFPLibCall(MVT VT, +static RTLIB::Libcall GetFPLibCall(EVT VT, RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, RTLIB::Libcall Call_PPCF128) { return - VT == MVT::f32 ? Call_F32 : - VT == MVT::f64 ? Call_F64 : - VT == MVT::f80 ? Call_F80 : - VT == MVT::ppcf128 ? Call_PPCF128 : + VT == EVT::f32 ? Call_F32 : + VT == EVT::f64 ? Call_F64 : + VT == EVT::f80 ? Call_F80 : + VT == EVT::ppcf128 ? Call_PPCF128 : RTLIB::UNKNOWN_LIBCALL; } @@ -126,7 +126,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_EXTRACT_VECTOR_ELT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned Size = NVT.getSizeInBits(); // Mask = ~(1 << (Size-1)) @@ -137,7 +137,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -149,7 +149,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::CEIL_F32, @@ -164,8 +164,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { SDValue RHS = BitConvertToInteger(N->getOperand(1)); DebugLoc dl = N->getDebugLoc(); - MVT LVT = LHS.getValueType(); - MVT RVT = RHS.getValueType(); + EVT LVT = LHS.getValueType(); + EVT RVT = RHS.getValueType(); unsigned LSize = LVT.getSizeInBits(); unsigned RSize = RVT.getSizeInBits(); @@ -200,7 +200,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::COS_F32, @@ -211,7 +211,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -223,7 +223,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::EXP_F32, @@ -234,7 +234,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::EXP2_F32, @@ -245,7 +245,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::FLOOR_F32, @@ -256,7 +256,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::LOG_F32, @@ -267,7 +267,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::LOG2_F32, @@ -278,7 +278,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::LOG10_F32, @@ -289,7 +289,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -301,7 +301,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::NEARBYINT_F32, @@ -312,7 +312,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); // Expand Y = FNEG(X) -> Y = SUB -0.0, X SDValue Ops[2] = { DAG.getConstantFP(-0.0, N->getValueType(0)), GetSoftenedFloat(N->getOperand(0)) }; @@ -325,7 +325,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0)); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!"); @@ -333,7 +333,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0)); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!"); @@ -341,7 +341,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -353,9 +353,9 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) { - assert(N->getOperand(1).getValueType() == MVT::i32 && + assert(N->getOperand(1).getValueType() == EVT::i32 && "Unsupported power type!"); - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::POWI_F32, @@ -366,7 +366,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -378,7 +378,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::RINT_F32, @@ -389,7 +389,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::SIN_F32, @@ -400,7 +400,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::SQRT_F32, @@ -411,7 +411,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), GetSoftenedFloat(N->getOperand(1)) }; return MakeLibCall(GetFPLibCall(N->getValueType(0), @@ -423,7 +423,7 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Op = GetSoftenedFloat(N->getOperand(0)); return MakeLibCall(GetFPLibCall(N->getValueType(0), RTLIB::TRUNC_F32, @@ -435,8 +435,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) { LoadSDNode *L = cast<LoadSDNode>(N); - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); DebugLoc dl = N->getDebugLoc(); SDValue NewL; @@ -486,8 +486,8 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_UNDEF(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) { SDValue Chain = N->getOperand(0); // Get the chain. SDValue Ptr = N->getOperand(1); // Get the pointer. - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); DebugLoc dl = N->getDebugLoc(); SDValue NewVAARG; @@ -501,18 +501,18 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) { SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) { bool Signed = N->getOpcode() == ISD::SINT_TO_FP; - MVT SVT = N->getOperand(0).getValueType(); - MVT RVT = N->getValueType(0); - MVT NVT = MVT(); + EVT SVT = N->getOperand(0).getValueType(); + EVT RVT = N->getValueType(0); + EVT NVT = EVT(); DebugLoc dl = N->getDebugLoc(); // If the input is not legal, eg: i1 -> fp, then it needs to be promoted to // a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly // match. Look for an appropriate libcall. RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE; - t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) { - NVT = (MVT::SimpleValueType)t; + for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE; + t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) { + NVT = (EVT::SimpleValueType)t; // The source needs to big enough to hold the operand. if (NVT.bitsGE(SVT)) LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT); @@ -574,70 +574,70 @@ void DAGTypeLegalizer::SoftenSetCCOperands(SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, DebugLoc dl) { SDValue LHSInt = GetSoftenedFloat(NewLHS); SDValue RHSInt = GetSoftenedFloat(NewRHS); - MVT VT = NewLHS.getValueType(); + EVT VT = NewLHS.getValueType(); - assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!"); + assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!"); // Expand into one or more soft-fp libcall(s). RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; switch (CCCode) { case ISD::SETEQ: case ISD::SETOEQ: - LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; break; case ISD::SETNE: case ISD::SETUNE: - LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; + LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64; break; case ISD::SETGE: case ISD::SETOGE: - LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; break; case ISD::SETLT: case ISD::SETOLT: - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; break; case ISD::SETLE: case ISD::SETOLE: - LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; break; case ISD::SETGT: case ISD::SETOGT: - LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; break; case ISD::SETUO: - LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; + LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; break; case ISD::SETO: - LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; + LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64; break; default: - LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; + LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64; switch (CCCode) { case ISD::SETONE: // SETONE = SETOLT | SETOGT - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; + LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; // Fallthrough case ISD::SETUGT: - LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; + LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64; break; case ISD::SETUGE: - LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; + LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64; break; case ISD::SETULT: - LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; + LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64; break; case ISD::SETULE: - LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; + LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64; break; case ISD::SETUEQ: - LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; + LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64; break; default: assert(false && "Do not know how to soften this setcc!"); } } - MVT RetVT = MVT::i32; // FIXME: is this the correct return type? + EVT RetVT = EVT::i32; // FIXME: is this the correct return type? SDValue Ops[2] = { LHSInt, RHSInt }; NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl); NewRHS = DAG.getConstant(0, RetVT); @@ -659,8 +659,8 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_BIT_CONVERT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) { - MVT SVT = N->getOperand(0).getValueType(); - MVT RVT = N->getValueType(0); + EVT SVT = N->getOperand(0).getValueType(); + EVT RVT = N->getValueType(0); RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall"); @@ -688,7 +688,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_BR_CC(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) { - MVT RVT = N->getValueType(0); + EVT RVT = N->getValueType(0); RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!"); SDValue Op = GetSoftenedFloat(N->getOperand(0)); @@ -696,7 +696,7 @@ SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) { } SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) { - MVT RVT = N->getValueType(0); + EVT RVT = N->getValueType(0); RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!"); SDValue Op = GetSoftenedFloat(N->getOperand(0)); @@ -829,7 +829,7 @@ void DAGTypeLegalizer::ExpandFloatResult(SDNode *N, unsigned ResNo) { void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); assert(NVT.getSizeInBits() == integerPartWidth && "Do not know how to expand this float constant!"); APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt(); @@ -841,7 +841,7 @@ void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo, SDValue &Hi) { - assert(N->getValueType(0) == MVT::ppcf128 && + assert(N->getValueType(0) == EVT::ppcf128 && "Logic only correct for ppcf128!"); DebugLoc dl = N->getDebugLoc(); SDValue Tmp; @@ -981,7 +981,7 @@ void DAGTypeLegalizer::ExpandFloatRes_FNEG(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0)); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); } @@ -1066,7 +1066,7 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, SDValue Ptr = LD->getBasePtr(); DebugLoc dl = N->getDebugLoc(); - MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); assert(NVT.isByteSized() && "Expanded type not byte sized!"); assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?"); @@ -1088,31 +1088,31 @@ void DAGTypeLegalizer::ExpandFloatRes_LOAD(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, SDValue &Hi) { - assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!"); - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!"); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); SDValue Src = N->getOperand(0); - MVT SrcVT = Src.getValueType(); + EVT SrcVT = Src.getValueType(); bool isSigned = N->getOpcode() == ISD::SINT_TO_FP; DebugLoc dl = N->getDebugLoc(); // First do an SINT_TO_FP, whether the original was signed or unsigned. // When promoting partial word types to i32 we must honor the signedness, // though. - if (SrcVT.bitsLE(MVT::i32)) { + if (SrcVT.bitsLE(EVT::i32)) { // The integer can be represented exactly in an f64. Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, - MVT::i32, Src); + EVT::i32, Src); Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT); Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src); } else { RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (SrcVT.bitsLE(MVT::i64)) { + if (SrcVT.bitsLE(EVT::i64)) { Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, - MVT::i64, Src); + EVT::i64, Src); LC = RTLIB::SINTTOFP_I64_PPCF128; - } else if (SrcVT.bitsLE(MVT::i128)) { - Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src); + } else if (SrcVT.bitsLE(EVT::i128)) { + Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src); LC = RTLIB::SINTTOFP_I128_PPCF128; } assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!"); @@ -1137,20 +1137,20 @@ void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo, switch (SrcVT.getSimpleVT()) { default: assert(false && "Unsupported UINT_TO_FP!"); - case MVT::i32: + case EVT::i32: Parts = TwoE32; break; - case MVT::i64: + case EVT::i64: Parts = TwoE64; break; - case MVT::i128: + case EVT::i128: Parts = TwoE128; break; } Lo = DAG.getNode(ISD::FADD, dl, VT, Hi, DAG.getConstantFP(APFloat(APInt(128, 2, Parts)), - MVT::ppcf128)); + EVT::ppcf128)); Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT), Lo, Hi, DAG.getCondCode(ISD::SETLT)); GetPairElements(Lo, Lo, Hi); @@ -1222,8 +1222,8 @@ void DAGTypeLegalizer::FloatExpandSetCCOperands(SDValue &NewLHS, GetExpandedFloat(NewLHS, LHSLo, LHSHi); GetExpandedFloat(NewRHS, RHSLo, RHSHi); - MVT VT = NewLHS.getValueType(); - assert(VT == MVT::ppcf128 && "Unsupported setcc type!"); + EVT VT = NewLHS.getValueType(); + assert(VT == EVT::ppcf128 && "Unsupported setcc type!"); // FIXME: This generated code sucks. We want to generate // FCMPU crN, hi1, hi2 @@ -1264,7 +1264,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_BR_CC(SDNode *N) { } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) { - assert(N->getOperand(0).getValueType() == MVT::ppcf128 && + assert(N->getOperand(0).getValueType() == EVT::ppcf128 && "Logic only correct for ppcf128!"); SDValue Lo, Hi; GetExpandedFloat(N->getOperand(0), Lo, Hi); @@ -1274,19 +1274,19 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) { } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { - MVT RVT = N->getValueType(0); + EVT RVT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on // PPC (the libcall is not available). FIXME: Do this in a less hacky way. - if (RVT == MVT::i32) { - assert(N->getOperand(0).getValueType() == MVT::ppcf128 && + if (RVT == EVT::i32) { + assert(N->getOperand(0).getValueType() == EVT::ppcf128 && "Logic only correct for ppcf128!"); - SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128, - N->getOperand(0), DAG.getValueType(MVT::f64)); - Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res, + SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128, + N->getOperand(0), DAG.getValueType(EVT::f64)); + Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res, DAG.getIntPtrConstant(1)); - return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res); + return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res); } RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); @@ -1295,29 +1295,29 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { } SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) { - MVT RVT = N->getValueType(0); + EVT RVT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on // PPC (the libcall is not available). FIXME: Do this in a less hacky way. - if (RVT == MVT::i32) { - assert(N->getOperand(0).getValueType() == MVT::ppcf128 && + if (RVT == EVT::i32) { + assert(N->getOperand(0).getValueType() == EVT::ppcf128 && "Logic only correct for ppcf128!"); const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; APFloat APF = APFloat(APInt(128, 2, TwoE31)); - SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128); + SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128); // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X // FIXME: generated code sucks. - return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp, - DAG.getNode(ISD::ADD, dl, MVT::i32, - DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, + return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp, + DAG.getNode(ISD::ADD, dl, EVT::i32, + DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, DAG.getNode(ISD::FSUB, dl, - MVT::ppcf128, + EVT::ppcf128, N->getOperand(0), Tmp)), - DAG.getConstant(0x80000000, MVT::i32)), + DAG.getConstant(0x80000000, EVT::i32)), DAG.getNode(ISD::FP_TO_SINT, dl, - MVT::i32, N->getOperand(0)), + EVT::i32, N->getOperand(0)), DAG.getCondCode(ISD::SETGE)); } @@ -1372,7 +1372,7 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_STORE(SDNode *N, unsigned OpNo) { SDValue Chain = ST->getChain(); SDValue Ptr = ST->getBasePtr(); - MVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType()); + EVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType()); assert(NVT.isByteSized() && "Expanded type not byte sized!"); assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?"); diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 5be0706641..b1b2ae3e5c 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -162,10 +162,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_Atomic2(AtomicSDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { SDValue InOp = N->getOperand(0); - MVT InVT = InOp.getValueType(); - MVT NInVT = TLI.getTypeToTransformTo(InVT); - MVT OutVT = N->getValueType(0); - MVT NOutVT = TLI.getTypeToTransformTo(OutVT); + EVT InVT = InOp.getValueType(); + EVT NInVT = TLI.getTypeToTransformTo(InVT); + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(OutVT); DebugLoc dl = N->getDebugLoc(); switch (getTypeAction(InVT)) { @@ -202,7 +202,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { std::swap(Lo, Hi); InOp = DAG.getNode(ISD::ANY_EXTEND, dl, - MVT::getIntegerVT(NOutVT.getSizeInBits()), + EVT::getIntegerVT(NOutVT.getSizeInBits()), JoinIntegers(Lo, Hi)); return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp); } @@ -218,8 +218,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - MVT OVT = N->getValueType(0); - MVT NVT = Op.getValueType(); + EVT OVT = N->getValueType(0); + EVT NVT = Op.getValueType(); DebugLoc dl = N->getDebugLoc(); unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); @@ -236,7 +236,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_PAIR(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // FIXME there is no actual debug info here DebugLoc dl = N->getDebugLoc(); // Zero extend things like i1, sign extend everything else. It shouldn't @@ -254,7 +254,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CONVERT_RNDSAT(SDNode *N) { CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU || CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) && "can only promote integers"); - MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0)); return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0), N->getOperand(1), N->getOperand(2), N->getOperand(3), N->getOperand(4), CvtCode); @@ -264,8 +264,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTLZ(SDNode *N) { // Zero extend to the promoted type and do the count there. SDValue Op = ZExtPromotedInteger(N->getOperand(0)); DebugLoc dl = N->getDebugLoc(); - MVT OVT = N->getValueType(0); - MVT NVT = Op.getValueType(); + EVT OVT = N->getValueType(0); + EVT NVT = Op.getValueType(); Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op); // Subtract off the extra leading bits in the bigger type. return DAG.getNode(ISD::SUB, dl, NVT, Op, @@ -281,8 +281,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTPOP(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { SDValue Op = GetPromotedInteger(N->getOperand(0)); - MVT OVT = N->getValueType(0); - MVT NVT = Op.getValueType(); + EVT OVT = N->getValueType(0); + EVT NVT = Op.getValueType(); DebugLoc dl = N->getDebugLoc(); // The count is the same in the promoted type except if the original // value was zero. This can be handled by setting the bit just off @@ -295,13 +295,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) { DebugLoc dl = N->getDebugLoc(); - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0), N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned NewOpc = N->getOpcode(); DebugLoc dl = N->getDebugLoc(); @@ -325,7 +325,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { @@ -352,7 +352,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType(); DebugLoc dl = N->getDebugLoc(); @@ -370,8 +370,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) { /// Promote the overflow flag of an overflowing arithmetic node. SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) { // Simply change the return type of the boolean result. - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); - MVT ValueVTs[] = { N->getValueType(0), NVT }; + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(1)); + EVT ValueVTs[] = { N->getValueType(0), NVT }; SDValue Ops[] = { N->getOperand(0), N->getOperand(1) }; SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(), DAG.getVTList(ValueVTs, 2), Ops, 2); @@ -391,8 +391,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SADDSUBO(SDNode *N, unsigned ResNo) { // sign extension of its truncation to the original type. SDValue LHS = SExtPromotedInteger(N->getOperand(0)); SDValue RHS = SExtPromotedInteger(N->getOperand(1)); - MVT OVT = N->getOperand(0).getValueType(); - MVT NVT = LHS.getValueType(); + EVT OVT = N->getOperand(0).getValueType(); + EVT NVT = LHS.getValueType(); DebugLoc dl = N->getDebugLoc(); // Do the arithmetic in the larger type. @@ -436,7 +436,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SELECT_CC(SDNode *N) { } SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { - MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); + EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType()); assert(isTypeLegal(SVT) && "Illegal SetCC type!"); DebugLoc dl = N->getDebugLoc(); @@ -445,7 +445,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) { N->getOperand(1), N->getOperand(2)); // Convert to the expected type. - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); assert(NVT.bitsLE(SVT) && "Integer type overpromoted?"); return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC); } @@ -481,14 +481,14 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) { // The input value must be properly zero extended. - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); SDValue Res = ZExtPromotedInteger(N->getOperand(0)); return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1)); } SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Res; switch (getTypeAction(N->getOperand(0).getValueType())) { @@ -514,8 +514,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) { // zero extension of its truncation to the original type. SDValue LHS = ZExtPromotedInteger(N->getOperand(0)); SDValue RHS = ZExtPromotedInteger(N->getOperand(1)); - MVT OVT = N->getOperand(0).getValueType(); - MVT NVT = LHS.getValueType(); + EVT OVT = N->getOperand(0).getValueType(); + EVT NVT = LHS.getValueType(); DebugLoc dl = N->getDebugLoc(); // Do the arithmetic in the larger type. @@ -549,10 +549,10 @@ SDValue DAGTypeLegalizer::PromoteIntRes_UNDEF(SDNode *N) { SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { SDValue Chain = N->getOperand(0); // Get the chain. SDValue Ptr = N->getOperand(1); // Get the pointer. - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); - MVT RegVT = TLI.getRegisterType(VT); + EVT RegVT = TLI.getRegisterType(VT); unsigned NumRegs = TLI.getNumRegisters(VT); // The argument is passed as NumRegs registers of type RegVT. @@ -567,7 +567,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) { std::reverse(Parts.begin(), Parts.end()); // Assemble the parts in the promoted type. - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); for (unsigned i = 1; i < NumRegs; ++i) { SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); @@ -718,7 +718,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { assert(OpNo == 1 && "only know how to promote condition"); // Promote all the way up to the canonical SetCC type. - MVT SVT = TLI.getSetCCResultType(MVT::Other); + EVT SVT = TLI.getSetCCResultType(EVT::Other); SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT); // The chain (Op#0) and basic block destination (Op#2) are always legal types. @@ -728,7 +728,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BRCOND(SDNode *N, unsigned OpNo) { SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) { // Since the result type is legal, the operands must promote to it. - MVT OVT = N->getOperand(0).getValueType(); + EVT OVT = N->getOperand(0).getValueType(); SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); SDValue Hi = GetPromotedInteger(N->getOperand(1)); assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); @@ -743,7 +743,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_VECTOR(SDNode *N) { // The vector type is legal but the element type is not. This implies // that the vector is a power-of-two in length and that the element // type does not have a strange size (eg: it is not i1). - MVT VecVT = N->getValueType(0); + EVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); assert(!(NumElts & 1) && "Legal vector of one illegal element?"); @@ -802,7 +802,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_MEMBARRIER(SDNode *N) { NewOps[0] = N->getOperand(0); for (unsigned i = 1; i < array_lengthof(NewOps); ++i) { SDValue Flag = GetPromotedInteger(N->getOperand(i)); - NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1); + NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1); } return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps, array_lengthof(NewOps)); @@ -819,7 +819,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) { assert(OpNo == 0 && "Only know how to promote condition"); // Promote all the way up to the canonical SetCC type. - MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); + EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType()); SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT); return DAG.UpdateNodeOperands(SDValue(N, 0), Cond, @@ -990,10 +990,10 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, SDValue InL, InH; GetExpandedInteger(N->getOperand(0), InL, InH); - MVT NVT = InL.getValueType(); + EVT NVT = InL.getValueType(); unsigned VTBits = N->getValueType(0).getSizeInBits(); unsigned NVTBits = NVT.getSizeInBits(); - MVT ShTy = N->getOperand(1).getValueType(); + EVT ShTy = N->getOperand(1).getValueType(); if (N->getOpcode() == ISD::SHL) { if (Amt > VTBits) { @@ -1009,7 +1009,7 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, TLI.isOperationLegalOrCustom(ISD::ADDC, TLI.getTypeToExpandTo(NVT))) { // Emit this X << 1 as X+X. - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); + SDVTList VTList = DAG.getVTList(NVT, EVT::Flag); SDValue LoOps[2] = { InL, InL }; Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); SDValue HiOps[3] = { InH, InH, Lo.getValue(1) }; @@ -1077,8 +1077,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, bool DAGTypeLegalizer:: ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Amt = N->getOperand(1); - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - MVT ShTy = Amt.getValueType(); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT ShTy = Amt.getValueType(); unsigned ShBits = ShTy.getSizeInBits(); unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && @@ -1155,8 +1155,8 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { bool DAGTypeLegalizer:: ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Amt = N->getOperand(1); - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); - MVT ShTy = Amt.getValueType(); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT ShTy = Amt.getValueType(); unsigned NVTBits = NVT.getSizeInBits(); assert(isPowerOf2_32(NVTBits) && "Expanded integer type size not a power of two!"); @@ -1230,14 +1230,14 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - MVT NVT = LHSL.getValueType(); + EVT NVT = LHSL.getValueType(); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; // Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support // them. TODO: Teach operation legalization how to expand unsupported // ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate - // a carry of type MVT::Flag, but there doesn't seem to be any way to + // a carry of type EVT::Flag, but there doesn't seem to be any way to // generate a value of this type in the expanded code sequence. bool hasCarry = TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ? @@ -1245,7 +1245,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUB(SDNode *N, TLI.getTypeToExpandTo(NVT)); if (hasCarry) { - SDVTList VTList = DAG.getVTList(NVT, MVT::Flag); + SDVTList VTList = DAG.getVTList(NVT, EVT::Flag); if (N->getOpcode() == ISD::ADD) { Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2); HiOps[2] = Lo.getValue(1); @@ -1290,7 +1290,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBC(SDNode *N, DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag); SDValue LoOps[2] = { LHSL, RHSL }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1316,7 +1316,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), LHSL, LHSH); GetExpandedInteger(N->getOperand(1), RHSL, RHSH); - SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag); + SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag); SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) }; SDValue HiOps[3] = { LHSH, RHSH }; @@ -1331,7 +1331,7 @@ void DAGTypeLegalizer::ExpandIntRes_ADDSUBE(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { @@ -1355,14 +1355,14 @@ void DAGTypeLegalizer::ExpandIntRes_AssertSext(SDNode *N, SDValue &Lo, SDValue &Hi) { DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT NVT = Lo.getValueType(); - MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + EVT NVT = Lo.getValueType(); + EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); unsigned NVTBits = NVT.getSizeInBits(); unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi, - DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); + DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits))); } else { Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT)); // The high part replicates the sign bit of Lo, make it explicit. @@ -1375,14 +1375,14 @@ void DAGTypeLegalizer::ExpandIntRes_AssertZext(SDNode *N, SDValue &Lo, SDValue &Hi) { DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT NVT = Lo.getValueType(); - MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + EVT NVT = Lo.getValueType(); + EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); unsigned NVTBits = NVT.getSizeInBits(); unsigned EVTBits = EVT.getSizeInBits(); if (NVTBits < EVTBits) { Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi, - DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits))); + DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits))); } else { Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT)); // The high part must be zero, make it explicit. @@ -1400,7 +1400,7 @@ void DAGTypeLegalizer::ExpandIntRes_BSWAP(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned NBitWidth = NVT.getSizeInBits(); const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue(); Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT); @@ -1412,7 +1412,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N, DebugLoc dl = N->getDebugLoc(); // ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32) GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT NVT = Lo.getValueType(); + EVT NVT = Lo.getValueType(); SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi, DAG.getConstant(0, NVT), ISD::SETNE); @@ -1431,7 +1431,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, DebugLoc dl = N->getDebugLoc(); // ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo) GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT NVT = Lo.getValueType(); + EVT NVT = Lo.getValueType(); Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo), DAG.getNode(ISD::CTPOP, dl, NVT, Hi)); Hi = DAG.getConstant(0, NVT); @@ -1442,7 +1442,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, DebugLoc dl = N->getDebugLoc(); // cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32) GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT NVT = Lo.getValueType(); + EVT NVT = Lo.getValueType(); SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo, DAG.getConstant(0, NVT), ISD::SETNE); @@ -1459,7 +1459,7 @@ void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, SDValue &Hi) { DebugLoc dl = N->getDebugLoc(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!"); @@ -1469,7 +1469,7 @@ void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo, SDValue &Hi) { DebugLoc dl = N->getDebugLoc(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); SDValue Op = N->getOperand(0); RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!"); @@ -1485,8 +1485,8 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!"); - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); SDValue Ch = N->getChain(); SDValue Ptr = N->getBasePtr(); ISD::LoadExtType ExtType = N->getExtensionType(); @@ -1498,7 +1498,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, assert(NVT.isByteSized() && "Expanded type not byte sized!"); if (N->getMemoryVT().bitsLE(NVT)) { - MVT EVT = N->getMemoryVT(); + EVT EVT = N->getMemoryVT(); Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, EVT, isVolatile, Alignment); @@ -1527,7 +1527,7 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, unsigned ExcessBits = N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); - MVT NEVT = MVT::getIntegerVT(ExcessBits); + EVT NEVT = EVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits()/8; @@ -1539,19 +1539,19 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); } else { // Big-endian - high bits are at low addresses. Favor aligned loads at // the cost of some bit-fiddling. - MVT EVT = N->getMemoryVT(); + EVT EVT = N->getMemoryVT(); unsigned EBytes = EVT.getStoreSizeInBits()/8; unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; // Load both the high bits and maybe some of the low bits. Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset, - MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), + EVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits), isVolatile, Alignment); // Increment the pointer to the other half. @@ -1560,12 +1560,12 @@ void DAGTypeLegalizer::ExpandIntRes_LOAD(LoadSDNode *N, // Load the rest of the low bits. Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset+IncrementSize, - MVT::getIntegerVT(ExcessBits), + EVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); if (ExcessBits < NVT.getSizeInBits()) { @@ -1599,8 +1599,8 @@ void DAGTypeLegalizer::ExpandIntRes_Logical(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT NVT = TLI.getTypeToTransformTo(VT); DebugLoc dl = N->getDebugLoc(); bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT); @@ -1673,13 +1673,13 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, // If nothing else, we can make a libcall. RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::MUL_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::MUL_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::MUL_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::MUL_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!"); @@ -1689,17 +1689,17 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::SDIV_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::SDIV_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::SDIV_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::SDIV_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); @@ -1709,7 +1709,7 @@ void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); // If we can emit an efficient shift operation, do so now. Check to see if @@ -1735,7 +1735,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, // Next check to see if the target supports this SHL_PARTS operation or if it // will custom expand it. - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT NVT = TLI.getTypeToTransformTo(VT); TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT); if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || Action == TargetLowering::Custom) { @@ -1744,7 +1744,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, GetExpandedInteger(N->getOperand(0), LHSL, LHSH); SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) }; - MVT VT = LHSL.getValueType(); + EVT VT = LHSL.getValueType(); Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3); Hi = Lo.getValue(1); return; @@ -1755,34 +1755,34 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, bool isSigned; if (N->getOpcode() == ISD::SHL) { isSigned = false; /*sign irrelevant*/ - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::SHL_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::SHL_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::SHL_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::SHL_I128; } else if (N->getOpcode() == ISD::SRL) { isSigned = false; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::SRL_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::SRL_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::SRL_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::SRL_I128; } else { assert(N->getOpcode() == ISD::SRA && "Unknown shift!"); isSigned = true; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::SRA_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::SRA_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::SRA_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::SRA_I128; } @@ -1798,7 +1798,7 @@ void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { @@ -1821,7 +1821,7 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N, unsigned ExcessBits = Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerVT(ExcessBits))); + DAG.getValueType(EVT::getIntegerVT(ExcessBits))); } } @@ -1829,7 +1829,7 @@ void DAGTypeLegalizer:: ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { DebugLoc dl = N->getDebugLoc(); GetExpandedInteger(N->getOperand(0), Lo, Hi); - MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); + EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); if (EVT.bitsLE(Lo.getValueType())) { // sext_inreg the low part if needed. @@ -1847,23 +1847,23 @@ ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) { unsigned ExcessBits = EVT.getSizeInBits() - Lo.getValueType().getSizeInBits(); Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi, - DAG.getValueType(MVT::getIntegerVT(ExcessBits))); + DAG.getValueType(EVT::getIntegerVT(ExcessBits))); } } void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::SREM_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::SREM_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::SREM_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::SREM_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); @@ -1873,7 +1873,7 @@ void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0)); Hi = DAG.getNode(ISD::SRL, dl, @@ -1884,17 +1884,17 @@ void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::UDIV_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::UDIV_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::UDIV_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::UDIV_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!"); @@ -1904,17 +1904,17 @@ void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; - if (VT == MVT::i16) + if (VT == EVT::i16) LC = RTLIB::UREM_I16; - else if (VT == MVT::i32) + else if (VT == EVT::i32) LC = RTLIB::UREM_I32; - else if (VT == MVT::i64) + else if (VT == EVT::i64) LC = RTLIB::UREM_I64; - else if (VT == MVT::i128) + else if (VT == EVT::i128) LC = RTLIB::UREM_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!"); @@ -1924,7 +1924,7 @@ void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N, void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); SDValue Op = N->getOperand(0); if (Op.getValueType().bitsLE(NVT)) { @@ -1943,7 +1943,7 @@ void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N, SplitInteger(Res, Lo, Hi); unsigned ExcessBits = Op.getValueType().getSizeInBits() - NVT.getSizeInBits(); - Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits)); + Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(ExcessBits)); } } @@ -2016,7 +2016,7 @@ void DAGTypeLegalizer::IntegerExpandSetCCOperands(SDValue &NewLHS, GetExpandedInteger(NewLHS, LHSLo, LHSHi); GetExpandedInteger(NewRHS, RHSLo, RHSHi); - MVT VT = NewLHS.getValueType(); + EVT VT = NewLHS.getValueType(); if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) { if (RHSLo == RHSHi) { @@ -2174,7 +2174,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_Shift(SDNode *N) { SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) { SDValue Op = N->getOperand(0); - MVT DstVT = N->getValueType(0); + EVT DstVT = N->getValueType(0); RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Don't know how to expand this SINT_TO_FP!"); @@ -2188,8 +2188,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!"); assert(OpNo == 1 && "Can only expand the stored value so far"); - MVT VT = N->getOperand(1).getValueType(); - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getOperand(1).getValueType(); + EVT NVT = TLI.getTypeToTransformTo(VT); SDValue Ch = N->getChain(); SDValue Ptr = N->getBasePtr(); int SVOffset = N->getSrcValueOffset(); @@ -2213,7 +2213,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { unsigned ExcessBits = N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits(); - MVT NEVT = MVT::getIntegerVT(ExcessBits); + EVT NEVT = EVT::getIntegerVT(ExcessBits); // Increment the pointer to the other half. unsigned IncrementSize = NVT.getSizeInBits()/8; @@ -2222,17 +2222,17 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, NEVT, isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } else { // Big-endian - high bits are at low addresses. Favor aligned stores at // the cost of some bit-fiddling. GetExpandedInteger(N->getValue(), Lo, Hi); - MVT EVT = N->getMemoryVT(); - unsigned EBytes = EVT.getStoreSizeInBits()/8; + EVT ExtVT = N->getMemoryVT(); + unsigned EBytes = ExtVT.getStoreSizeInBits()/8; unsigned IncrementSize = NVT.getSizeInBits()/8; unsigned ExcessBits = (EBytes - IncrementSize)*8; - MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits); + EVT HiVT = EVT::getIntegerVT(ExtVT.getSizeInBits() - ExcessBits); if (ExcessBits < NVT.getSizeInBits()) { // Transfer high bits from the top of Lo to the bottom of Hi. @@ -2255,9 +2255,9 @@ SDValue DAGTypeLegalizer::ExpandIntOp_STORE(StoreSDNode *N, unsigned OpNo) { // Store the lowest ExcessBits bits in the second half. Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(), SVOffset+IncrementSize, - MVT::getIntegerVT(ExcessBits), + EVT::getIntegerVT(ExcessBits), isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } } @@ -2270,8 +2270,8 @@ SDValue DAGTypeLegalizer::ExpandIntOp_TRUNCATE(SDNode *N) { SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { SDValue Op = N->getOperand(0); - MVT SrcVT = Op.getValueType(); - MVT DstVT = N->getValueType(0); + EVT SrcVT = Op.getValueType(); + EVT DstVT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){ @@ -2288,11 +2288,11 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { const uint64_t F32TwoE128 = 0x7F800000ULL; APInt FF(32, 0); - if (SrcVT == MVT::i32) + if (SrcVT == EVT::i32) FF = APInt(32, F32TwoE32); - else if (SrcVT == MVT::i64) + else if (SrcVT == EVT::i64) FF = APInt(32, F32TwoE64); - else if (SrcVT == MVT::i128) + else if (SrcVT == EVT::i128) FF = APInt(32, F32TwoE128); else assert(false && "Unsupported UINT_TO_FP!"); @@ -2323,7 +2323,7 @@ SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) { // Load the value out, extending it from f32 to the destination float type. // FIXME: Avoid the extend by constructing the right constant pool? SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(), - FudgePtr, NULL, 0, MVT::f32, + FudgePtr, NULL, 0, EVT::f32, false, Alignment); return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp index 4e4c69a102..db08823b03 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp @@ -211,7 +211,7 @@ bool DAGTypeLegalizer::run() { // Scan the values produced by the node, checking to see if any result // types are illegal. for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) { - MVT ResultVT = N->getValueType(i); + EVT ResultVT = N->getValueType(i); switch (getTypeAction(ResultVT)) { default: assert(false && "Unknown action!"); @@ -264,7 +264,7 @@ ScanOperands: if (IgnoreNodeResults(N->getOperand(i).getNode())) continue; - MVT OpVT = N->getOperand(i).getValueType(); + EVT OpVT = N->getOperand(i).getValueType(); switch (getTypeAction(OpVT)) { default: assert(false && "Unknown action!"); @@ -861,7 +861,7 @@ void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) { SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) { unsigned BitWidth = Op.getValueType().getSizeInBits(); return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(), - MVT::getIntegerVT(BitWidth), Op); + EVT::getIntegerVT(BitWidth), Op); } /// BitConvertVectorToIntegerVector - Convert to a vector of integers of the @@ -869,14 +869,14 @@ SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) { SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) { assert(Op.getValueType().isVector() && "Only applies to vectors!"); unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits(); - MVT EltNVT = MVT::getIntegerVT(EltWidth); + EVT EltNVT = EVT::getIntegerVT(EltWidth); unsigned NumElts = Op.getValueType().getVectorNumElements(); return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(), - MVT::getVectorVT(EltNVT, NumElts), Op); + EVT::getVectorVT(EltNVT, NumElts), Op); } SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op, - MVT DestVT) { + EVT DestVT) { DebugLoc dl = Op.getDebugLoc(); // Create the stack frame object. Make sure it is aligned for both // the source and destination types. @@ -895,7 +895,7 @@ SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op, /// The last parameter being TRUE means we are dealing with a /// node with illegal result types. The second parameter denotes the type of /// illegal ResNo in that case. -bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult) { +bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) { // See if the target wants to custom lower this node. if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom) return false; @@ -920,14 +920,14 @@ bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult) { /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type /// which is split into two not necessarily identical pieces. -void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) { +void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) { // Currently all types are split in half. if (!InVT.isVector()) { LoVT = HiVT = TLI.getTypeToTransformTo(InVT); } else { unsigned NumElements = InVT.getVectorNumElements(); assert(!(NumElements & 1) && "Splitting vector, but not in half!"); - LoVT = HiVT = MVT::getVectorVT(InVT.getVectorElementType(), NumElements/2); + LoVT = HiVT = EVT::getVectorVT(InVT.getVectorElementType(), NumElements/2); } } @@ -936,14 +936,14 @@ void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) { void DAGTypeLegalizer::GetPairElements(SDValue Pair, SDValue &Lo, SDValue &Hi) { DebugLoc dl = Pair.getDebugLoc(); - MVT NVT = TLI.getTypeToTransformTo(Pair.getValueType()); + EVT NVT = TLI.getTypeToTransformTo(Pair.getValueType()); Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair, DAG.getIntPtrConstant(0)); Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair, DAG.getIntPtrConstant(1)); } -SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT, +SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index) { DebugLoc dl = Index.getDebugLoc(); // Make sure the index type is big enough to compute in. @@ -965,9 +965,9 @@ SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) { // Arbitrarily use dlHi for result DebugLoc DebugLoc dlHi = Hi.getDebugLoc(); DebugLoc dlLo = Lo.getDebugLoc(); - MVT LVT = Lo.getValueType(); - MVT HVT = Hi.getValueType(); - MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); + EVT LVT = Lo.getValueType(); + EVT HVT = Hi.getValueType(); + EVT NVT = EVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits()); Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); @@ -999,7 +999,7 @@ SDValue DAGTypeLegalizer::LibCallify(RTLIB::Libcall LC, SDNode *N, /// MakeLibCall - Generate a libcall taking the given operands as arguments and /// returning a result of type RetVT. -SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, +SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl) { TargetLowering::ArgListTy Args; @@ -1008,7 +1008,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, TargetLowering::ArgListEntry Entry; for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; - Entry.Ty = Entry.Node.getValueType().getTypeForMVT(); + Entry.Ty = Entry.Node.getValueType().getTypeForEVT(); Entry.isSExt = isSigned; Entry.isZExt = !isSigned; Args.push_back(Entry); @@ -1016,7 +1016,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), TLI.getPointerTy()); - const Type *RetTy = RetVT.getTypeForMVT(); + const Type *RetTy = RetVT.getTypeForEVT(); std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, false, 0, CallingConv::C, false, @@ -1028,7 +1028,7 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT, /// PromoteTargetBoolean - Promote the given target boolean to a target boolean /// of the given type. A target boolean is an integer value, not necessarily of /// type i1, the bits of which conform to getBooleanContents. -SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) { +SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) { DebugLoc dl = Bool.getDebugLoc(); ISD::NodeType ExtendCode; switch (TLI.getBooleanContents()) { @@ -1054,7 +1054,7 @@ SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) { /// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT /// bits in Hi. void DAGTypeLegalizer::SplitInteger(SDValue Op, - MVT LoVT, MVT HiVT, + EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi) { DebugLoc dl = Op.getDebugLoc(); assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() == @@ -1069,7 +1069,7 @@ void DAGTypeLegalizer::SplitInteger(SDValue Op, /// type half the size of Op's. void DAGTypeLegalizer::SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi) { - MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2); + EVT HalfVT = EVT::getIntegerVT(Op.getValueType().getSizeInBits()/2); SplitInteger(Op, HalfVT, HalfVT, Lo, Hi); } diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 0dd82c4b43..8801ceec90 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -74,7 +74,7 @@ private: TargetLowering::ValueTypeActionImpl ValueTypeActions; /// getTypeAction - Return how we should legalize values of this type. - LegalizeAction getTypeAction(MVT VT) const { + LegalizeAction getTypeAction(EVT VT) const { switch (ValueTypeActions.getTypeAction(VT)) { default: assert(false && "Unknown legalize action!"); @@ -109,7 +109,7 @@ private: } /// isTypeLegal - Return true if this type is legal on this target. - bool isTypeLegal(MVT VT) const { + bool isTypeLegal(EVT VT) const { return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal; } @@ -159,7 +159,7 @@ public: explicit DAGTypeLegalizer(SelectionDAG &dag) : TLI(dag.getTargetLoweringInfo()), DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { - assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && + assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); } @@ -185,19 +185,19 @@ private: // Common routines. SDValue BitConvertToInteger(SDValue Op); SDValue BitConvertVectorToIntegerVector(SDValue Op); - SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT); - bool CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult); - SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index); + SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT); + bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult); + SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index); SDValue JoinIntegers(SDValue Lo, SDValue Hi); SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned); - SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT, + SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl); - SDValue PromoteTargetBoolean(SDValue Bool, MVT VT); + SDValue PromoteTargetBoolean(SDValue Bool, EVT VT); void ReplaceValueWith(SDValue From, SDValue To); void ReplaceValueWithHelper(SDValue From, SDValue To); void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi); - void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT, + void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT, SDValue &Lo, SDValue &Hi); //===--------------------------------------------------------------------===// @@ -224,7 +224,7 @@ private: /// SExtPromotedInteger - Get a promoted operand and sign extend it to the /// final size. SDValue SExtPromotedInteger(SDValue Op) { - MVT OldVT = Op.getValueType(); + EVT OldVT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op, @@ -234,7 +234,7 @@ private: /// ZExtPromotedInteger - Get a promoted operand and zero extend it to the /// final size. SDValue ZExtPromotedInteger(SDValue Op) { - MVT OldVT = Op.getValueType(); + EVT OldVT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); Op = GetPromotedInteger(Op); return DAG.getZeroExtendInReg(Op, dl, OldVT); @@ -641,7 +641,7 @@ private: SDValue BasePtr, const Value *SV, int SVOffset, unsigned Alignment, bool isVolatile, unsigned LdWidth, - MVT ResType, DebugLoc dl); + EVT ResType, DebugLoc dl); /// Helper genWidenVectorStores - Helper function to generate a set of /// stores to store a widen vector into non widen memory @@ -664,7 +664,7 @@ private: /// Modifies a vector input (widen or narrows) to a vector of NVT. The /// input vector must have the same element type as NVT. - SDValue ModifyToType(SDValue InOp, MVT WidenVT); + SDValue ModifyToType(SDValue InOp, EVT WidenVT); //===--------------------------------------------------------------------===// @@ -686,7 +686,7 @@ private: /// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type /// which is split (or expanded) into two not necessarily identical pieces. - void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT); + void GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT); /// GetPairElements - Use ISD::EXTRACT_ELEMENT nodes to extract the low and /// high parts of the given value. diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp index 080342687a..8533866a07 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp @@ -34,10 +34,10 @@ using namespace llvm; void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT OutVT = N->getValueType(0); - MVT NOutVT = TLI.getTypeToTransformTo(OutVT); + EVT OutVT = N->getValueType(0); + EVT NOutVT = TLI.getTypeToTransformTo(OutVT); SDValue InOp = N->getOperand(0); - MVT InVT = InOp.getValueType(); + EVT InVT = InOp.getValueType(); DebugLoc dl = N->getDebugLoc(); // Handle some special cases efficiently. @@ -76,7 +76,7 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo, case WidenVector: { assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BIT_CONVERT"); InOp = GetWidenedVector(InOp); - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), InVT.getVectorNumElements()/2); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, DAG.getIntPtrConstant(0)); @@ -93,7 +93,7 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo, if (InVT.isVector() && OutVT.isInteger()) { // Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand // is legal but the result is not. - MVT NVT = MVT::getVectorVT(NOutVT, 2); + EVT NVT = EVT::getVectorVT(NOutVT, 2); if (isTypeLegal(NVT)) { SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp); @@ -115,7 +115,7 @@ void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo, // Create the stack frame object. Make sure it is aligned for both // the source and expanded destination types. unsigned Alignment = - TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForMVT()); + TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT()); SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment); int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); const Value *SV = PseudoSourceValue::getFixedStack(SPFI); @@ -167,11 +167,11 @@ void DAGTypeLegalizer::ExpandRes_EXTRACT_VECTOR_ELT(SDNode *N, SDValue &Lo, // Convert to a vector of the expanded element type, for example // <3 x i64> -> <6 x i32>. - MVT OldVT = N->getValueType(0); - MVT NewVT = TLI.getTypeToTransformTo(OldVT); + EVT OldVT = N->getValueType(0); + EVT NewVT = TLI.getTypeToTransformTo(OldVT); SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::getVectorVT(NewVT, 2*OldElts), + EVT::getVectorVT(NewVT, 2*OldElts), OldVec); // Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector. @@ -198,7 +198,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, DebugLoc dl = N->getDebugLoc(); LoadSDNode *LD = cast<LoadSDNode>(N); - MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0)); SDValue Chain = LD->getChain(); SDValue Ptr = LD->getBasePtr(); int SVOffset = LD->getSrcValueOffset(); @@ -220,7 +220,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, // Build a factor node to remember that this load is independent of the // other one. - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); // Handle endianness of the load. @@ -233,7 +233,7 @@ void DAGTypeLegalizer::ExpandRes_NormalLoad(SDNode *N, SDValue &Lo, } void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue Chain = N->getOperand(0); SDValue Ptr = N->getOperand(1); DebugLoc dl = N->getDebugLoc(); @@ -263,8 +263,8 @@ SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) { // instead, but only if the new vector type is legal (otherwise there // is no point, and it might create expansion loops). For example, on // x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32. - MVT OVT = N->getOperand(0).getValueType(); - MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2); + EVT OVT = N->getOperand(0).getValueType(); + EVT NVT = EVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2); if (isTypeLegal(NVT)) { SDValue Parts[2]; @@ -284,10 +284,10 @@ SDValue DAGTypeLegalizer::ExpandOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) { // The vector type is legal but the element type needs expansion. - MVT VecVT = N->getValueType(0); + EVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); - MVT OldVT = N->getOperand(0).getValueType(); - MVT NewVT = TLI.getTypeToTransformTo(OldVT); + EVT OldVT = N->getOperand(0).getValueType(); + EVT NewVT = TLI.getTypeToTransformTo(OldVT); DebugLoc dl = N->getDebugLoc(); assert(OldVT == VecVT.getVectorElementType() && @@ -308,7 +308,7 @@ SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) { } SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::getVectorVT(NewVT, NewElts.size()), + EVT::getVectorVT(NewVT, NewElts.size()), &NewElts[0], NewElts.size()); // Convert the new vector to the old vector type. @@ -323,20 +323,20 @@ SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) { // The vector type is legal but the element type needs expansion. - MVT VecVT = N->getValueType(0); + EVT VecVT = N->getValueType(0); unsigned NumElts = VecVT.getVectorNumElements(); DebugLoc dl = N->getDebugLoc(); SDValue Val = N->getOperand(1); - MVT OldEVT = Val.getValueType(); - MVT NewEVT = TLI.getTypeToTransformTo(OldEVT); + EVT OldEVT = Val.getValueType(); + EVT NewEVT = TLI.getTypeToTransformTo(OldEVT); assert(OldEVT == VecVT.getVectorElementType() && "Inserted element type doesn't match vector element type!"); // Bitconvert to a vector of twice the length with elements of the expanded // type, insert the expanded vector elements, and then convert back. - MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2); + EVT NewVecVT = EVT::getVectorVT(NewEVT, NumElts*2); SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl, NewVecVT, N->getOperand(0)); @@ -358,7 +358,7 @@ SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) { DebugLoc dl = N->getDebugLoc(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); assert(VT.getVectorElementType() == N->getOperand(0).getValueType() && "SCALAR_TO_VECTOR operand type doesn't match vector element type!"); unsigned NumElts = VT.getVectorNumElements(); @@ -376,7 +376,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) { DebugLoc dl = N->getDebugLoc(); StoreSDNode *St = cast<StoreSDNode>(N); - MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType()); + EVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType()); SDValue Chain = St->getChain(); SDValue Ptr = St->getBasePtr(); int SVOffset = St->getSrcValueOffset(); @@ -402,7 +402,7 @@ SDValue DAGTypeLegalizer::ExpandOp_NormalStore(SDNode *N, unsigned OpNo) { SVOffset + IncrementSize, isVolatile, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } @@ -462,7 +462,7 @@ void DAGTypeLegalizer::SplitRes_SELECT_CC(SDNode *N, SDValue &Lo, } void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getUNDEF(LoVT); diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 58a09276da..aa647fde1b 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -129,7 +129,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { if (!HasVectorValue) return TranslateLegalizeResults(Op, Result); - MVT QueryType; + EVT QueryType; switch (Op.getOpcode()) { default: return TranslateLegalizeResults(Op, Result); @@ -231,10 +231,10 @@ SDValue VectorLegalizer::PromoteVectorOp(SDValue Op) { // Vector "promotion" is basically just bitcasting and doing the operation // in a different type. For example, x86 promotes ISD::AND on v2i32 to // v1i64. - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't promote a vector with multiple results!"); - MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); + EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 4> Operands(Op.getNumOperands()); @@ -260,11 +260,11 @@ SDValue VectorLegalizer::ExpandFNEG(SDValue Op) { } SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned NumElems = VT.getVectorNumElements(); - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2); - MVT TmpEltVT = LHS.getValueType().getVectorElementType(); + EVT TmpEltVT = LHS.getValueType().getVectorElementType(); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 8> Ops(NumElems); for (unsigned i = 0; i < NumElems; ++i) { @@ -287,11 +287,11 @@ SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) { /// the operation be expanded. "Unroll" the vector, splitting out the scalars /// and operating on each element individually. SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); assert(Op.getNode()->getNumValues() == 1 && "Can't unroll a vector with multiple results!"); unsigned NE = VT.getVectorNumElements(); - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); DebugLoc dl = Op.getDebugLoc(); SmallVector<SDValue, 8> Scalars; @@ -299,14 +299,14 @@ SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) { for (unsigned i = 0; i != NE; ++i) { for (unsigned j = 0; j != Op.getNumOperands(); ++j) { SDValue Operand = Op.getOperand(j); - MVT OperandVT = Operand.getValueType(); + EVT OperandVT = Operand.getValueType(); if (OperandVT.isVector()) { // A vector operand; extract a single element. - MVT OperandEltVT = OperandVT.getVectorElementType(); + EVT OperandEltVT = OperandVT.getVectorElementType(); Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, OperandEltVT, Operand, - DAG.getConstant(i, MVT::i32)); + DAG.getConstant(i, EVT::i32)); } else { // A scalar operand; just use it as is. Operands[j] = Operand; diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 9ec084663f..a10d167579 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -118,13 +118,13 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_BinOp(SDNode *N) { } SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) { - MVT NewVT = N->getValueType(0).getVectorElementType(); + EVT NewVT = N->getValueType(0).getVectorElementType(); return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), NewVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) { - MVT NewVT = N->getValueType(0).getVectorElementType(); + EVT NewVT = N->getValueType(0).getVectorElementType(); SDValue Op0 = GetScalarizedVector(N->getOperand(0)); return DAG.getConvertRndSat(NewVT, N->getDebugLoc(), Op0, DAG.getValueType(NewVT), @@ -150,7 +150,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_INSERT_VECTOR_ELT(SDNode *N) { // The value to insert may have a wider type than the vector element type, // so be sure to truncate it to the element type if necessary. SDValue Op = N->getOperand(1); - MVT EltVT = N->getValueType(0).getVectorElementType(); + EVT EltVT = N->getValueType(0).getVectorElementType(); if (Op.getValueType() != EltVT) // FIXME: Can this happen for floating point types? Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op); @@ -177,7 +177,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_LOAD(LoadSDNode *N) { SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { // Get the dest type - it doesn't always match the input type, e.g. int_to_fp. - MVT DestVT = N->getValueType(0).getVectorElementType(); + EVT DestVT = N->getValueType(0).getVectorElementType(); SDValue Op = GetScalarizedVector(N->getOperand(0)); return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op); } @@ -185,7 +185,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) { SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) { // If the operand is wider than the vector element type then it is implicitly // truncated. Make that explicit here. - MVT EltVT = N->getValueType(0).getVectorElementType(); + EVT EltVT = N->getValueType(0).getVectorElementType(); SDValue InOp = N->getOperand(0); if (InOp.getValueType() != EltVT) return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp); @@ -213,7 +213,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_SETCC(SDNode *N) { DebugLoc DL = N->getDebugLoc(); // Turn it into a scalar SETCC. - return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2)); + return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2)); } SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) { @@ -232,8 +232,8 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VECTOR_SHUFFLE(SDNode *N) { SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { SDValue LHS = GetScalarizedVector(N->getOperand(0)); SDValue RHS = GetScalarizedVector(N->getOperand(1)); - MVT NVT = N->getValueType(0).getVectorElementType(); - MVT SVT = TLI.getSetCCResultType(LHS.getValueType()); + EVT NVT = N->getValueType(0).getVectorElementType(); + EVT SVT = TLI.getSetCCResultType(LHS.getValueType()); DebugLoc DL = N->getDebugLoc(); // Turn it into a scalar SETCC. @@ -247,16 +247,16 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) { if (TLI.getBooleanContents() != TargetLowering::ZeroOrNegativeOneBooleanContent) Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res, - DAG.getValueType(MVT::i1)); + DAG.getValueType(EVT::i1)); // Truncate to the final type. return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res); } // The SETCC result type is smaller than the vector element type. - // If the SetCC result is not sign-extended, chop it down to MVT::i1. + // If the SetCC result is not sign-extended, chop it down to EVT::i1. if (TLI.getBooleanContents() != TargetLowering::ZeroOrNegativeOneBooleanContent) - Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res); + Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res); // Sign extend to the final type. return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res); } @@ -472,12 +472,12 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, SDValue &Hi) { // We know the result is a vector. The input may be either a vector or a // scalar value. - MVT LoVT, HiVT; + EVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); DebugLoc dl = N->getDebugLoc(); SDValue InOp = N->getOperand(0); - MVT InVT = InOp.getValueType(); + EVT InVT = InOp.getValueType(); // Handle some special cases efficiently. switch (getTypeAction(InVT)) { @@ -512,8 +512,8 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, } // In the general case, convert the input to an integer and split it by hand. - MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits()); - MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits()); + EVT LoIntVT = EVT::getIntegerVT(LoVT.getSizeInBits()); + EVT HiIntVT = EVT::getIntegerVT(HiVT.getSizeInBits()); if (TLI.isBigEndian()) std::swap(LoIntVT, HiIntVT); @@ -527,7 +527,7 @@ void DAGTypeLegalizer::SplitVecRes_BIT_CONVERT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); unsigned LoNumElts = LoVT.getVectorNumElements(); @@ -549,7 +549,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, return; } - MVT LoVT, HiVT; + EVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors); @@ -561,7 +561,7 @@ void DAGTypeLegalizer::SplitVecRes_CONCAT_VECTORS(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); @@ -574,11 +574,11 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, // Split the input. SDValue VLo, VHi; - MVT InVT = N->getOperand(0).getValueType(); + EVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { default: llvm_unreachable("Unexpected type action!"); case Legal: { - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), DAG.getIntPtrConstant(0)); @@ -594,7 +594,7 @@ void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo, // the two types must have different lengths. Use the widened result // and extract from it to do the split. SDValue InOp = GetWidenedVector(N->getOperand(0)); - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, DAG.getIntPtrConstant(0)); @@ -617,10 +617,10 @@ void DAGTypeLegalizer::SplitVecRes_EXTRACT_SUBVECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) { SDValue Vec = N->getOperand(0); SDValue Idx = N->getOperand(1); - MVT IdxVT = Idx.getValueType(); + EVT IdxVT = Idx.getValueType(); DebugLoc dl = N->getDebugLoc(); - MVT LoVT, HiVT; + EVT LoVT, HiVT; GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx); @@ -658,8 +658,8 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, } // Spill the vector to the stack. - MVT VecVT = Vec.getValueType(); - MVT EltVT = VecVT.getVectorElementType(); + EVT VecVT = Vec.getValueType(); + EVT EltVT = VecVT.getVectorElementType(); SDValue StackPtr = DAG.CreateStackTemporary(VecVT); SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0); @@ -667,7 +667,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, // so use a truncating store. SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx); unsigned Alignment = - TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT()); + TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT()); Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT); // Load the Lo part from the stack slot. @@ -685,7 +685,7 @@ void DAGTypeLegalizer::SplitVecRes_INSERT_VECTOR_ELT(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0)); @@ -695,7 +695,7 @@ void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo, void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue &Hi) { assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!"); - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = LD->getDebugLoc(); GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT); @@ -705,11 +705,11 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, SDValue Offset = DAG.getUNDEF(Ptr.getValueType()); const Value *SV = LD->getSrcValue(); int SVOffset = LD->getSrcValueOffset(); - MVT MemoryVT = LD->getMemoryVT(); + EVT MemoryVT = LD->getMemoryVT(); unsigned Alignment = LD->getAlignment(); bool isVolatile = LD->isVolatile(); - MVT LoMemVT, HiMemVT; + EVT LoMemVT, HiMemVT; GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset, @@ -725,7 +725,7 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, // Build a factor node to remember that this load is independent of the // other one. - Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), + Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1), Hi.getValue(1)); // Legalized the chain result - switch anything that used the old chain to @@ -734,14 +734,14 @@ void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo, } void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc DL = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); // Split the input. - MVT InVT = N->getOperand(0).getValueType(); + EVT InVT = N->getOperand(0).getValueType(); SDValue LL, LH, RL, RH; - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0), DAG.getIntPtrConstant(0)); @@ -760,16 +760,16 @@ void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) { void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, SDValue &Hi) { // Get the dest types - they may not match the input types, e.g. int_to_fp. - MVT LoVT, HiVT; + EVT LoVT, HiVT; DebugLoc dl = N->getDebugLoc(); GetSplitDestVTs(N->getValueType(0), LoVT, HiVT); // Split the input. - MVT InVT = N->getOperand(0).getValueType(); + EVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { default: llvm_unreachable("Unexpected type action!"); case Legal: { - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), DAG.getIntPtrConstant(0)); @@ -785,7 +785,7 @@ void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo, // the two types must have different lengths. Use the widened result // and extract from it to do the split. SDValue InOp = GetWidenedVector(N->getOperand(0)); - MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(), + EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(), LoVT.getVectorNumElements()); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp, DAG.getIntPtrConstant(0)); @@ -806,7 +806,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, DebugLoc dl = N->getDebugLoc(); GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]); GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]); - MVT NewVT = Inputs[0].getValueType(); + EVT NewVT = Inputs[0].getValueType(); unsigned NewElts = NewVT.getVectorNumElements(); // If Lo or Hi uses elements from at most two of the four input vectors, then @@ -864,7 +864,7 @@ void DAGTypeLegalizer::SplitVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N, } if (useBuildVector) { - MVT EltVT = NewVT.getVectorElementType(); + EVT EltVT = NewVT.getVectorElementType(); SmallVector<SDValue, 16> SVOps; // Extract the input elements by hand. @@ -969,13 +969,13 @@ bool DAGTypeLegalizer::SplitVectorOperand(SDNode *N, unsigned OpNo) { SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) { // The result has a legal vector type, but the input needs splitting. - MVT ResVT = N->getValueType(0); + EVT ResVT = N->getValueType(0); SDValue Lo, Hi; DebugLoc dl = N->getDebugLoc(); GetSplitVector(N->getOperand(0), Lo, Hi); - MVT InVT = Lo.getValueType(); + EVT InVT = Lo.getValueType(); - MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(), + EVT OutVT = EVT::getVectorVT(ResVT.getVectorElementType(), InVT.getVectorNumElements()); Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo); @@ -1003,7 +1003,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { // We know that the extracted result type is legal. For now, assume the index // is a constant. - MVT SubVT = N->getValueType(0); + EVT SubVT = N->getValueType(0); SDValue Idx = N->getOperand(1); DebugLoc dl = N->getDebugLoc(); SDValue Lo, Hi; @@ -1025,7 +1025,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) { SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { SDValue Vec = N->getOperand(0); SDValue Idx = N->getOperand(1); - MVT VecVT = Vec.getValueType(); + EVT VecVT = Vec.getValueType(); if (isa<ConstantSDNode>(Idx)) { uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); @@ -1044,7 +1044,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) { } // Store the vector to the stack. - MVT EltVT = VecVT.getVectorElementType(); + EVT EltVT = VecVT.getVectorElementType(); DebugLoc dl = N->getDebugLoc(); SDValue StackPtr = DAG.CreateStackTemporary(VecVT); int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); @@ -1066,13 +1066,13 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { SDValue Ch = N->getChain(); SDValue Ptr = N->getBasePtr(); int SVOffset = N->getSrcValueOffset(); - MVT MemoryVT = N->getMemoryVT(); + EVT MemoryVT = N->getMemoryVT(); unsigned Alignment = N->getAlignment(); bool isVol = N->isVolatile(); SDValue Lo, Hi; GetSplitVector(N->getOperand(1), Lo, Hi); - MVT LoMemVT, HiMemVT; + EVT LoMemVT, HiMemVT; GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT); unsigned IncrementSize = LoMemVT.getSizeInBits()/8; @@ -1097,7 +1097,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_STORE(StoreSDNode *N, unsigned OpNo) { Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize, isVol, MinAlign(Alignment, IncrementSize)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi); } @@ -1197,7 +1197,7 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) { // Binary op widening. - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue InOp1 = GetWidenedVector(N->getOperand(0)); SDValue InOp2 = GetWidenedVector(N->getOperand(1)); return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2); @@ -1207,12 +1207,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { SDValue InOp = N->getOperand(0); DebugLoc dl = N->getDebugLoc(); - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned WidenNumElts = WidenVT.getVectorNumElements(); - MVT InVT = InOp.getValueType(); - MVT InEltVT = InVT.getVectorElementType(); - MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts); + EVT InVT = InOp.getValueType(); + EVT InEltVT = InVT.getVectorElementType(); + EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts); unsigned Opcode = N->getOpcode(); unsigned InVTNumElts = InVT.getVectorNumElements(); @@ -1254,7 +1254,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { // Otherwise unroll into some nasty scalar code and rebuild the vector. SmallVector<SDValue, 16> Ops(WidenNumElts); - MVT EltVT = WidenVT.getVectorElementType(); + EVT EltVT = WidenVT.getVectorElementType(); unsigned MinElts = std::min(InVTNumElts, WidenNumElts); unsigned i; for (i=0; i < MinElts; ++i) @@ -1270,16 +1270,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_Convert(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue InOp = GetWidenedVector(N->getOperand(0)); SDValue ShOp = N->getOperand(1); - MVT ShVT = ShOp.getValueType(); + EVT ShVT = ShOp.getValueType(); if (getTypeAction(ShVT) == WidenVector) { ShOp = GetWidenedVector(ShOp); ShVT = ShOp.getValueType(); } - MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(), + EVT ShWidenVT = EVT::getVectorVT(ShVT.getVectorElementType(), WidenVT.getVectorNumElements()); if (ShVT != ShWidenVT) ShOp = ModifyToType(ShOp, ShWidenVT); @@ -1289,16 +1289,16 @@ SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) { // Unary op widening. - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); SDValue InOp = GetWidenedVector(N->getOperand(0)); return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp); } SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { SDValue InOp = N->getOperand(0); - MVT InVT = InOp.getValueType(); - MVT VT = N->getValueType(0); - MVT WidenVT = TLI.getTypeToTransformTo(VT); + EVT InVT = InOp.getValueType(); + EVT VT = N->getValueType(0); + EVT WidenVT = TLI.getTypeToTransformTo(VT); DebugLoc dl = N->getDebugLoc(); switch (getTypeAction(InVT)) { @@ -1338,13 +1338,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { // Determine new input vector type. The new input vector type will use // the same element type (if its a vector) or use the input type as a // vector. It is the same size as the type to widen to. - MVT NewInVT; + EVT NewInVT; unsigned NewNumElts = WidenSize / InSize; if (InVT.isVector()) { - MVT InEltVT = InVT.getVectorElementType(); - NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits()); + EVT InEltVT = InVT.getVectorElementType(); + NewInVT= EVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits()); } else { - NewInVT = MVT::getVectorVT(InVT, NewNumElts); + NewInVT = EVT::getVectorVT(InVT, NewNumElts); } if (TLI.isTypeLegal(NewInVT)) { @@ -1376,11 +1376,11 @@ SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { DebugLoc dl = N->getDebugLoc(); // Build a vector with undefined for the new nodes. - MVT VT = N->getValueType(0); - MVT EltVT = VT.getVectorElementType(); + EVT VT = N->getValueType(0); + EVT EltVT = VT.getVectorElementType(); unsigned NumElts = VT.getVectorNumElements(); - MVT WidenVT = TLI.getTypeToTransformTo(VT); + EVT WidenVT = TLI.getTypeToTransformTo(VT); unsigned WidenNumElts = WidenVT.getVectorNumElements(); SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end()); @@ -1392,8 +1392,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { - MVT InVT = N->getOperand(0).getValueType(); - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT InVT = N->getOperand(0).getValueType(); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); unsigned WidenNumElts = WidenVT.getVectorNumElements(); unsigned NumOperands = N->getNumOperands(); @@ -1442,7 +1442,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) { } // Fall back to use extracts and build vector. - MVT EltVT = WidenVT.getVectorElementType(); + EVT EltVT = WidenVT.getVectorElementType(); unsigned NumInElts = InVT.getVectorNumElements(); SmallVector<SDValue, 16> Ops(WidenNumElts); unsigned Idx = 0; @@ -1466,12 +1466,12 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { SDValue RndOp = N->getOperand(3); SDValue SatOp = N->getOperand(4); - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned WidenNumElts = WidenVT.getVectorNumElements(); - MVT InVT = InOp.getValueType(); - MVT InEltVT = InVT.getVectorElementType(); - MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts); + EVT InVT = InOp.getValueType(); + EVT InEltVT = InVT.getVectorElementType(); + EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts); SDValue DTyOp = DAG.getValueType(WidenVT); SDValue STyOp = DAG.getValueType(InWidenVT); @@ -1518,7 +1518,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { // Otherwise unroll into some nasty scalar code and rebuild the vector. SmallVector<SDValue, 16> Ops(WidenNumElts); - MVT EltVT = WidenVT.getVectorElementType(); + EVT EltVT = WidenVT.getVectorElementType(); DTyOp = DAG.getValueType(EltVT); STyOp = DAG.getValueType(InEltVT); @@ -1539,8 +1539,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_CONVERT_RNDSAT(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { - MVT VT = N->getValueType(0); - MVT WidenVT = TLI.getTypeToTransformTo(VT); + EVT VT = N->getValueType(0); + EVT WidenVT = TLI.getTypeToTransformTo(VT); unsigned WidenNumElts = WidenVT.getVectorNumElements(); SDValue InOp = N->getOperand(0); SDValue Idx = N->getOperand(1); @@ -1549,7 +1549,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { if (getTypeAction(InOp.getValueType()) == WidenVector) InOp = GetWidenedVector(InOp); - MVT InVT = InOp.getValueType(); + EVT InVT = InOp.getValueType(); ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx); if (CIdx) { @@ -1567,8 +1567,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) { // We could try widening the input to the right length but for now, extract // the original elements, fill the rest with undefs and build a vector. SmallVector<SDValue, 16> Ops(WidenNumElts); - MVT EltVT = VT.getVectorElementType(); - MVT IdxVT = Idx.getValueType(); + EVT EltVT = VT.getVectorElementType(); + EVT IdxVT = Idx.getValueType(); unsigned NumElts = VT.getVectorNumElements(); unsigned i; if (CIdx) { @@ -1600,8 +1600,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_INSERT_VECTOR_ELT(SDNode *N) { SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { LoadSDNode *LD = cast<LoadSDNode>(N); - MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0)); - MVT LdVT = LD->getMemoryVT(); + EVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0)); + EVT LdVT = LD->getMemoryVT(); DebugLoc dl = N->getDebugLoc(); assert(LdVT.isVector() && WidenVT.isVector()); @@ -1620,8 +1620,8 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { // For extension loads, we can not play the tricks of chopping legal // vector types and bit cast it to the right type. Instead, we unroll // the load and build a vector. - MVT EltVT = WidenVT.getVectorElementType(); - MVT LdEltVT = LdVT.getVectorElementType(); + EVT EltVT = WidenVT.getVectorElementType(); + EVT LdEltVT = LdVT.getVectorElementType(); unsigned NumElts = LdVT.getVectorNumElements(); // Load each element and widen @@ -1660,7 +1660,7 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { if (LdChain.size() == 1) NewChain = LdChain[0]; else - NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0], + NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0], LdChain.size()); // Modified the chain - switch anything that used the old chain to use @@ -1671,20 +1671,20 @@ SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) { - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(), WidenVT, N->getOperand(0)); } SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) { - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned WidenNumElts = WidenVT.getVectorNumElements(); SDValue Cond1 = N->getOperand(0); - MVT CondVT = Cond1.getValueType(); + EVT CondVT = Cond1.getValueType(); if (CondVT.isVector()) { - MVT CondEltVT = CondVT.getVectorElementType(); - MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts); + EVT CondEltVT = CondVT.getVectorElementType(); + EVT CondWidenVT = EVT::getVectorVT(CondEltVT, WidenNumElts); if (getTypeAction(CondVT) == WidenVector) Cond1 = GetWidenedVector(Cond1); @@ -1708,15 +1708,15 @@ SDValue DAGTypeLegalizer::WidenVecRes_SELECT_CC(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) { - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); return DAG.getUNDEF(WidenVT); } SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); - MVT WidenVT = TLI.getTypeToTransformTo(VT); + EVT WidenVT = TLI.getTypeToTransformTo(VT); unsigned NumElts = VT.getVectorNumElements(); unsigned WidenNumElts = WidenVT.getVectorNumElements(); @@ -1738,13 +1738,13 @@ SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) { } SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) { - MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); + EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0)); unsigned WidenNumElts = WidenVT.getVectorNumElements(); SDValue InOp1 = N->getOperand(0); - MVT InVT = InOp1.getValueType(); + EVT InVT = InOp1.getValueType(); assert(InVT.isVector() && "can not widen non vector type"); - MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts); + EVT WidenInVT = EVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts); InOp1 = GetWidenedVector(InOp1); SDValue InOp2 = GetWidenedVector(N->getOperand(1)); @@ -1812,15 +1812,15 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { // Since the result is legal and the input is illegal, it is unlikely // that we can fix the input to a legal type so unroll the convert // into some scalar code and create a nasty build vector. - MVT VT = N->getValueType(0); - MVT EltVT = VT.getVectorElementType(); + EVT VT = N->getValueType(0); + EVT EltVT = VT.getVectorElementType(); DebugLoc dl = N->getDebugLoc(); unsigned NumElts = VT.getVectorNumElements(); SDValue InOp = N->getOperand(0); if (getTypeAction(InOp.getValueType()) == WidenVector) InOp = GetWidenedVector(InOp); - MVT InVT = InOp.getValueType(); - MVT InEltVT = InVT.getVectorElementType(); + EVT InVT = InOp.getValueType(); + EVT InEltVT = InVT.getVectorElementType(); unsigned Opcode = N->getOpcode(); SmallVector<SDValue, 16> Ops(NumElts); @@ -1833,9 +1833,9 @@ SDValue DAGTypeLegalizer::WidenVecOp_Convert(SDNode *N) { } SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); SDValue InOp = GetWidenedVector(N->getOperand(0)); - MVT InWidenVT = InOp.getValueType(); + EVT InWidenVT = InOp.getValueType(); DebugLoc dl = N->getDebugLoc(); // Check if we can convert between two legal vector types and extract. @@ -1843,7 +1843,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) { unsigned Size = VT.getSizeInBits(); if (InWidenSize % Size == 0 && !VT.isVector()) { unsigned NewNumElts = InWidenSize / Size; - MVT NewVT = MVT::getVectorVT(VT, NewNumElts); + EVT NewVT = EVT::getVectorVT(VT, NewNumElts); if (TLI.isTypeLegal(NewVT)) { SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp, @@ -1858,13 +1858,13 @@ SDValue DAGTypeLegalizer::WidenVecOp_CONCAT_VECTORS(SDNode *N) { // If the input vector is not legal, it is likely that we will not find a // legal vector of the same size. Replace the concatenate vector with a // nasty build vector. - MVT VT = N->getValueType(0); - MVT EltVT = VT.getVectorElementType(); + EVT VT = N->getValueType(0); + EVT EltVT = VT.getVectorElementType(); DebugLoc dl = N->getDebugLoc(); unsigned NumElts = VT.getVectorNumElements(); SmallVector<SDValue, 16> Ops(NumElts); - MVT InVT = N->getOperand(0).getValueType(); + EVT InVT = N->getOperand(0).getValueType(); unsigned NumInElts = InVT.getVectorNumElements(); unsigned Idx = 0; @@ -1899,8 +1899,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { SDValue ValOp = GetWidenedVector(ST->getValue()); DebugLoc dl = N->getDebugLoc(); - MVT StVT = ST->getMemoryVT(); - MVT ValVT = ValOp.getValueType(); + EVT StVT = ST->getMemoryVT(); + EVT ValVT = ValOp.getValueType(); // It must be true that we the widen vector type is bigger than where // we need to store. assert(StVT.isVector() && ValOp.getValueType().isVector()); @@ -1911,8 +1911,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { // For truncating stores, we can not play the tricks of chopping legal // vector types and bit cast it to the right type. Instead, we unroll // the store. - MVT StEltVT = StVT.getVectorElementType(); - MVT ValEltVT = ValVT.getVectorElementType(); + EVT StEltVT = StVT.getVectorElementType(); + EVT ValEltVT = ValVT.getVectorElementType(); unsigned Increment = ValEltVT.getSizeInBits() / 8; unsigned NumElts = StVT.getVectorNumElements(); SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp, @@ -1941,7 +1941,7 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { return StChain[0]; else return DAG.getNode(ISD::TokenFactor, dl, - MVT::Other,&StChain[0],StChain.size()); + EVT::Other,&StChain[0],StChain.size()); } //===----------------------------------------------------------------------===// @@ -1958,8 +1958,8 @@ SDValue DAGTypeLegalizer::WidenVecOp_STORE(SDNode *N) { // Returns NewVecVT and NewEltVT - the vector type and its associated // element type. static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width, - MVT VecVT, - MVT& NewEltVT, MVT& NewVecVT) { + EVT VecVT, + EVT& NewEltVT, EVT& NewVecVT) { unsigned EltWidth = Width + 1; if (TLI.isTypeLegal(VecVT)) { // We start with the preferred with, making it a power of 2 and find a @@ -1969,9 +1969,9 @@ static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width, do { assert(EltWidth > 0); EltWidth = 1 << Log2_32(EltWidth - 1); - NewEltVT = MVT::getIntegerVT(EltWidth); + NewEltVT = EVT::getIntegerVT(EltWidth); unsigned NumElts = VecVT.getSizeInBits() / EltWidth; - NewVecVT = MVT::getVectorVT(NewEltVT, NumElts); + NewVecVT = EVT::getVectorVT(NewEltVT, NumElts); } while (!TLI.isTypeLegal(NewVecVT) || VecVT.getSizeInBits() != NewVecVT.getSizeInBits()); } else { @@ -1984,9 +1984,9 @@ static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width, do { assert(EltWidth > 0); EltWidth = 1 << Log2_32(EltWidth - 1); - NewEltVT = MVT::getIntegerVT(EltWidth); + NewEltVT = EVT::getIntegerVT(EltWidth); unsigned NumElts = VecVT.getSizeInBits() / EltWidth; - NewVecVT = MVT::getVectorVT(NewEltVT, NumElts); + NewVecVT = EVT::getVectorVT(NewEltVT, NumElts); } while (!TLI.isTypeLegal(NewEltVT) || VecVT.getSizeInBits() != NewVecVT.getSizeInBits()); } @@ -2000,7 +2000,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain, unsigned Alignment, bool isVolatile, unsigned LdWidth, - MVT ResType, + EVT ResType, DebugLoc dl) { // The strategy assumes that we can efficiently load powers of two widths. // The routines chops the vector into the largest power of 2 load and @@ -2011,7 +2011,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVector<SDValue, 16>& LdChain, // the load is nonvolatile, we an use a wider load for the value. // Find the vector type that can load from. - MVT NewEltVT, NewVecVT; + EVT NewEltVT, NewVecVT; unsigned NewEltVTWidth; FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT); NewEltVTWidth = NewEltVT.getSizeInBits(); @@ -2075,8 +2075,8 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, // want to store. This avoids requiring a stack convert. // Find a width of the element type we can store with - MVT WidenVT = ValOp.getValueType(); - MVT NewEltVT, NewVecVT; + EVT WidenVT = ValOp.getValueType(); + EVT NewEltVT, NewVecVT; FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT); unsigned NewEltVTWidth = NewEltVT.getSizeInBits(); @@ -2125,10 +2125,10 @@ void DAGTypeLegalizer::GenWidenVectorStores(SmallVector<SDValue, 16>& StChain, /// Modifies a vector input (widen or narrows) to a vector of NVT. The /// input vector must have the same element type as NVT. -SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) { +SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) { // Note that InOp might have been widened so it might already have // the right width or it might need be narrowed. - MVT InVT = InOp.getValueType(); + EVT InVT = InOp.getValueType(); assert(InVT.getVectorElementType() == NVT.getVectorElementType() && "input and widen element type must match"); DebugLoc dl = InOp.getDebugLoc(); @@ -2156,7 +2156,7 @@ SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) { // Fall back to extract and build. SmallVector<SDValue, 16> Ops(WidenNumElts); - MVT EltVT = NVT.getVectorElementType(); + EVT EltVT = NVT.getVectorElementType(); unsigned MinNumElts = std::min(WidenNumElts, InNumElts); unsigned Idx; for (Idx = 0; Idx < MinNumElts; ++Idx) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp index 515ec91af9..ee83f068e1 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp @@ -215,16 +215,16 @@ SUnit *ScheduleDAGFast::CopyAndMoveSuccessors(SUnit *SU) { SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT VT = N->getValueType(i); - if (VT == MVT::Flag) + EVT VT = N->getValueType(i); + if (VT == EVT::Flag) return NULL; - else if (VT == MVT::Other) + else if (VT == EVT::Other) TryUnfold = true; } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { const SDValue &Op = N->getOperand(i); - MVT VT = Op.getNode()->getValueType(Op.getResNo()); - if (VT == MVT::Flag) + EVT VT = Op.getNode()->getValueType(Op.getResNo()); + if (VT == EVT::Flag) return NULL; } @@ -420,7 +420,7 @@ void ScheduleDAGFast::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, +static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); @@ -534,7 +534,7 @@ void ScheduleDAGFast::ListScheduleBottomUp() { assert(LRegs.size() == 1 && "Can't handle this yet!"); unsigned Reg = LRegs[0]; SUnit *LRDef = LiveRegDefs[Reg]; - MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); + EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index 7c309901a4..5c7b8499e6 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -352,16 +352,16 @@ SUnit *ScheduleDAGRRList::CopyAndMoveSuccessors(SUnit *SU) { SUnit *NewSU; bool TryUnfold = false; for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT VT = N->getValueType(i); - if (VT == MVT::Flag) + EVT VT = N->getValueType(i); + if (VT == EVT::Flag) return NULL; - else if (VT == MVT::Other) + else if (VT == EVT::Other) TryUnfold = true; } for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { const SDValue &Op = N->getOperand(i); - MVT VT = Op.getNode()->getValueType(Op.getResNo()); - if (VT == MVT::Flag) + EVT VT = Op.getNode()->getValueType(Op.getResNo()); + if (VT == EVT::Flag) return NULL; } @@ -571,7 +571,7 @@ void ScheduleDAGRRList::InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, /// getPhysicalRegisterVT - Returns the ValueType of the physical register /// definition of the specified node. /// FIXME: Move to SelectionDAG? -static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, +static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); @@ -630,7 +630,7 @@ bool ScheduleDAGRRList::DelayForLiveRegsBottomUp(SUnit *SU, if (Node->getOpcode() == ISD::INLINEASM) { // Inline asm can clobber physical defs. unsigned NumOps = Node->getNumOperands(); - if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) + if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag) --NumOps; // Ignore the flag operand. for (unsigned i = 2; i != NumOps;) { @@ -754,7 +754,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() { assert(LRegs.size() == 1 && "Can't handle this yet!"); unsigned Reg = LRegs[0]; SUnit *LRDef = LiveRegDefs[Reg]; - MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); + EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII); const TargetRegisterClass *RC = TRI->getPhysicalRegisterRegClass(Reg, VT); const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC); @@ -1216,8 +1216,8 @@ static bool canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, if (!SUImpDefs) return false; for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) { - MVT VT = N->getValueType(i); - if (VT == MVT::Flag || VT == MVT::Other) + EVT VT = N->getValueType(i); + if (VT == EVT::Flag || VT == EVT::Other) continue; if (!N->hasAnyUseOfValue(i)) continue; diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 4e8e972cf9..4d2882a884 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -111,7 +111,7 @@ void ScheduleDAGSDNodes::BuildSchedUnits() { // Scan up to find flagged preds. SDNode *N = NI; while (N->getNumOperands() && - N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) { + N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) { N = N->getOperand(N->getNumOperands()-1).getNode(); assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NodeSUnit->NodeNum); @@ -119,7 +119,7 @@ void ScheduleDAGSDNodes::BuildSchedUnits() { // Scan down to find any flagged succs. N = NI; - while (N->getValueType(N->getNumValues()-1) == MVT::Flag) { + while (N->getValueType(N->getNumValues()-1) == EVT::Flag) { SDValue FlagVal(N, N->getNumValues()-1); // There are either zero or one users of the Flag result. @@ -189,9 +189,9 @@ void ScheduleDAGSDNodes::AddSchedEdges() { assert(OpSU && "Node has no SUnit!"); if (OpSU == SU) continue; // In the same group. - MVT OpVT = N->getOperand(i).getValueType(); - assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!"); - bool isChain = OpVT == MVT::Other; + EVT OpVT = N->getOperand(i).getValueType(); + assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!"); + bool isChain = OpVT == EVT::Other; unsigned PhysReg = 0; int Cost = 1; @@ -244,9 +244,9 @@ void ScheduleDAGSDNodes::ComputeLatency(SUnit *SU) { /// not go into the resulting MachineInstr). unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) { unsigned N = Node->getNumValues(); - while (N && Node->getValueType(N - 1) == MVT::Flag) + while (N && Node->getValueType(N - 1) == EVT::Flag) --N; - if (N && Node->getValueType(N - 1) == MVT::Other) + if (N && Node->getValueType(N - 1) == EVT::Other) --N; // Skip over chain result. return N; } @@ -266,9 +266,9 @@ unsigned ScheduleDAGSDNodes::CountOperands(SDNode *Node) { /// operand unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) { unsigned N = Node->getNumOperands(); - while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag) + while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag) --N; - if (N && Node->getOperand(N - 1).getValueType() == MVT::Other) + if (N && Node->getOperand(N - 1).getValueType() == EVT::Other) --N; // Ignore chain if it exists. return N; } diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp index 1d845a5b5e..d8736a12ad 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp @@ -69,8 +69,8 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, SDValue Op = User->getOperand(i); if (Op.getNode() != Node || Op.getResNo() != ResNo) continue; - MVT VT = Node->getValueType(Op.getResNo()); - if (VT == MVT::Other || VT == MVT::Flag) + EVT VT = Node->getValueType(Op.getResNo()); + if (VT == EVT::Other || VT == EVT::Flag) continue; Match = false; if (User->isMachineOpcode()) { @@ -95,7 +95,7 @@ EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone, bool IsCloned, break; } - MVT VT = Node->getValueType(ResNo); + EVT VT = Node->getValueType(ResNo); const TargetRegisterClass *SrcRC = 0, *DstRC = 0; SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT); @@ -238,8 +238,8 @@ ScheduleDAGSDNodes::AddRegisterOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, const TargetInstrDesc *II, DenseMap<SDValue, unsigned> &VRBaseMap) { - assert(Op.getValueType() != MVT::Other && - Op.getValueType() != MVT::Flag && + assert(Op.getValueType() != EVT::Other && + Op.getValueType() != EVT::Flag && "Chain and flag operands should occur at end of operand list!"); // Get/emit the operand. unsigned VReg = getVR(Op, VRBaseMap); @@ -322,8 +322,8 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op, MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0, ES->getTargetFlags())); } else { - assert(Op.getValueType() != MVT::Other && - Op.getValueType() != MVT::Flag && + assert(Op.getValueType() != EVT::Other && + Op.getValueType() != EVT::Flag && "Chain and flag operands should occur at end of operand list!"); AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap); } @@ -334,7 +334,7 @@ void ScheduleDAGSDNodes::AddOperand(MachineInstr *MI, SDValue Op, /// type matches the specified type. static const TargetRegisterClass* getSuperRegisterRegClass(const TargetRegisterClass *TRC, - unsigned SubIdx, MVT VT) { + unsigned SubIdx, EVT VT) { // Pick the register class of the superegister for this type for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(), E = TRC->superregclasses_end(); I != E; ++I) @@ -599,7 +599,7 @@ void ScheduleDAGSDNodes::EmitNode(SDNode *Node, bool IsClone, bool IsCloned, } case ISD::INLINEASM: { unsigned NumOps = Node->getNumOperands(); - if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag) + if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag) --NumOps; // Ignore the flag operand. // Create the inline asm machine instruction. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index bead83dc1d..712fedad4d 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -47,19 +47,19 @@ using namespace llvm; /// makeVTList - Return an instance of the SDVTList struct initialized with the /// specified members. -static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) { +static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) { SDVTList Res = {VTs, NumVTs}; return Res; } -static const fltSemantics *MVTToAPFloatSemantics(MVT VT) { +static const fltSemantics *EVTToAPFloatSemantics(EVT VT) { switch (VT.getSimpleVT()) { default: llvm_unreachable("Unknown FP format"); - case MVT::f32: return &APFloat::IEEEsingle; - case MVT::f64: return &APFloat::IEEEdouble; - case MVT::f80: return &APFloat::x87DoubleExtended; - case MVT::f128: return &APFloat::IEEEquad; - case MVT::ppcf128: return &APFloat::PPCDoubleDouble; + case EVT::f32: return &APFloat::IEEEsingle; + case EVT::f64: return &APFloat::IEEEdouble; + case EVT::f80: return &APFloat::x87DoubleExtended; + case EVT::f128: return &APFloat::IEEEquad; + case EVT::ppcf128: return &APFloat::PPCDoubleDouble; } } @@ -77,19 +77,19 @@ bool ConstantFPSDNode::isExactlyValue(const APFloat& V) const { return getValueAPF().bitwiseIsEqual(V); } -bool ConstantFPSDNode::isValueValidForType(MVT VT, +bool ConstantFPSDNode::isValueValidForType(EVT VT, const APFloat& Val) { assert(VT.isFloatingPoint() && "Can only convert between FP types"); // PPC long double cannot be converted to any other type. - if (VT == MVT::ppcf128 || + if (VT == EVT::ppcf128 || &Val.getSemantics() == &APFloat::PPCDoubleDouble) return false; // convert modifies in place, so make a copy. APFloat Val2 = APFloat(Val); bool losesInfo; - (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, + (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, &losesInfo); return !losesInfo; } @@ -502,7 +502,7 @@ encodeMemSDNodeFlags(int ConvType, ISD::MemIndexedMode AM, /// doNotCSE - Return true if CSE should not be performed for this node. static bool doNotCSE(SDNode *N) { - if (N->getValueType(0) == MVT::Flag) + if (N->getValueType(0) == EVT::Flag) return true; // Never CSE anything that produces a flag. switch (N->getOpcode()) { @@ -517,7 +517,7 @@ static bool doNotCSE(SDNode *N) { // Check that remaining values produced are not flags. for (unsigned i = 1, e = N->getNumValues(); i != e; ++i) - if (N->getValueType(i) == MVT::Flag) + if (N->getValueType(i) == EVT::Flag) return true; // Never CSE anything that produces a flag. return false; @@ -638,7 +638,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { break; } case ISD::VALUETYPE: { - MVT VT = cast<VTSDNode>(N)->getVT(); + EVT VT = cast<VTSDNode>(N)->getVT(); if (VT.isExtended()) { Erased = ExtendedValueTypeNodes.erase(VT); } else { @@ -656,7 +656,7 @@ bool SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) { // Verify that the node was actually in one of the CSE maps, unless it has a // flag result (which cannot be CSE'd) or is one of the special cases that are // not subject to CSE. - if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag && + if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag && !N->isMachineOpcode() && !doNotCSE(N)) { N->dump(this); cerr << "\n"; @@ -754,7 +754,7 @@ void SelectionDAG::VerifyNode(SDNode *N) { default: break; case ISD::BUILD_PAIR: { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); assert(N->getNumValues() == 1 && "Too many results!"); assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) && "Wrong return type!"); @@ -772,7 +772,7 @@ void SelectionDAG::VerifyNode(SDNode *N) { assert(N->getValueType(0).isVector() && "Wrong return type!"); assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() && "Wrong number of operands!"); - MVT EltVT = N->getValueType(0).getVectorElementType(); + EVT EltVT = N->getValueType(0).getVectorElementType(); for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I) assert((I->getValueType() == EltVT || (EltVT.isInteger() && I->getValueType().isInteger() && @@ -783,13 +783,13 @@ void SelectionDAG::VerifyNode(SDNode *N) { } } -/// getMVTAlignment - Compute the default alignment value for the +/// getEVTAlignment - Compute the default alignment value for the /// given type. /// -unsigned SelectionDAG::getMVTAlignment(MVT VT) const { - const Type *Ty = VT == MVT::iPTR ? +unsigned SelectionDAG::getEVTAlignment(EVT VT) const { + const Type *Ty = VT == EVT::iPTR ? PointerType::get(Type::Int8Ty, 0) : - VT.getTypeForMVT(); + VT.getTypeForEVT(); return TLI.getTargetData()->getABITypeAlignment(Ty); } @@ -798,7 +798,7 @@ unsigned SelectionDAG::getMVTAlignment(MVT VT) const { SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli) : TLI(tli), FLI(fli), DW(0), EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(), - getVTList(MVT::Other)), Root(getEntryNode()) { + getVTList(EVT::Other)), Root(getEntryNode()) { AllNodes.push_back(&EntryNode); } @@ -839,7 +839,7 @@ void SelectionDAG::clear() { Root = getEntryNode(); } -SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { +SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) { if (Op.getValueType() == VT) return Op; APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(), VT.getSizeInBits()); @@ -849,29 +849,29 @@ SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) { /// getNOT - Create a bitwise NOT operation as (XOR Val, -1). /// -SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) { - MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; +SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, EVT VT) { + EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; SDValue NegOne = getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); return getNode(ISD::XOR, DL, VT, Val, NegOne); } -SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) { - MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; +SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT) { + EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; assert((EltVT.getSizeInBits() >= 64 || (uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) && "getConstant with a uint64_t value that doesn't fit in the type!"); return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT); } -SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) { +SDValue SelectionDAG::getConstant(const APInt &Val, EVT VT, bool isT) { return getConstant(*ConstantInt::get(*Context, Val), VT, isT); } -SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) { +SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) { assert(VT.isInteger() && "Cannot create FP integer constant!"); - MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; + EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; assert(Val.getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); @@ -906,14 +906,14 @@ SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, bool isTarget) { } -SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) { +SDValue SelectionDAG::getConstantFP(const APFloat& V, EVT VT, bool isTarget) { return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget); } -SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ +SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){ assert(VT.isFloatingPoint() && "Cannot create integer FP constant!"); - MVT EltVT = + EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; // Do the map lookup using the actual bit pattern for the floating point @@ -946,24 +946,24 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){ return Result; } -SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) { - MVT EltVT = +SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) { + EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; - if (EltVT==MVT::f32) + if (EltVT==EVT::f32) return getConstantFP(APFloat((float)Val), VT, isTarget); else return getConstantFP(APFloat(Val), VT, isTarget); } SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, - MVT VT, int64_t Offset, + EVT VT, int64_t Offset, bool isTargetGA, unsigned char TargetFlags) { assert((TargetFlags == 0 || isTargetGA) && "Cannot set target flags on target-independent globals"); // Truncate (with sign-extension) the offset value to the pointer size. - MVT PTy = TLI.getPointerTy(); + EVT PTy = TLI.getPointerTy(); unsigned BitWidth = PTy.getSizeInBits(); if (BitWidth < 64) Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth)); @@ -996,7 +996,7 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, return SDValue(N, 0); } -SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { +SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0); @@ -1011,7 +1011,7 @@ SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) { return SDValue(N, 0); } -SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget, +SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget, unsigned char TargetFlags) { assert((TargetFlags == 0 || isTarget) && "Cannot set target flags on target-independent jump tables"); @@ -1030,7 +1030,7 @@ SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget, return SDValue(N, 0); } -SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, +SDValue SelectionDAG::getConstantPool(Constant *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) { @@ -1056,7 +1056,7 @@ SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT, } -SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, +SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT, unsigned Alignment, int Offset, bool isTarget, unsigned char TargetFlags) { @@ -1083,7 +1083,7 @@ SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT, SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0); + AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0); ID.AddPointer(MBB); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) @@ -1095,7 +1095,7 @@ SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) { return SDValue(N, 0); } -SDValue SelectionDAG::getValueType(MVT VT) { +SDValue SelectionDAG::getValueType(EVT VT) { if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size()) ValueTypeNodes.resize(VT.getSimpleVT()+1); @@ -1109,7 +1109,7 @@ SDValue SelectionDAG::getValueType(MVT VT) { return SDValue(N, 0); } -SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { +SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) { SDNode *&N = ExternalSymbols[Sym]; if (N) return SDValue(N, 0); N = NodeAllocator.Allocate<ExternalSymbolSDNode>(); @@ -1118,7 +1118,7 @@ SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) { return SDValue(N, 0); } -SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT, +SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT, unsigned char TargetFlags) { SDNode *&N = TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym, @@ -1157,7 +1157,7 @@ static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { } } -SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, +SDValue SelectionDAG::getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, const int *Mask) { assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); assert(VT.isVector() && N1.getValueType().isVector() && @@ -1247,7 +1247,7 @@ SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1, return SDValue(N, 0); } -SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, +SDValue SelectionDAG::getConvertRndSat(EVT VT, DebugLoc dl, SDValue Val, SDValue DTy, SDValue STy, SDValue Rnd, SDValue Sat, ISD::CvtCode Code) { @@ -1269,7 +1269,7 @@ SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl, return SDValue(N, 0); } -SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) { +SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0); ID.AddInteger(RegNo); @@ -1298,7 +1298,7 @@ SDValue SelectionDAG::getLabel(unsigned Opcode, DebugLoc dl, unsigned LabelID) { FoldingSetNodeID ID; SDValue Ops[] = { Root }; - AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1); + AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1); ID.AddInteger(LabelID); void *IP = 0; if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP)) @@ -1315,7 +1315,7 @@ SDValue SelectionDAG::getSrcValue(const Value *V) { "SrcValue is not a pointer?"); FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0); + AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0); ID.AddPointer(V); void *IP = 0; @@ -1337,7 +1337,7 @@ SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { #endif FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0); + AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0); MO.Profile(ID); void *IP = 0; @@ -1354,8 +1354,8 @@ SDValue SelectionDAG::getMemOperand(const MachineMemOperand &MO) { /// getShiftAmountOperand - Return the specified value casted to /// the target's desired shift amount type. SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { - MVT OpTy = Op.getValueType(); - MVT ShTy = TLI.getShiftAmountTy(); + EVT OpTy = Op.getValueType(); + EVT ShTy = TLI.getShiftAmountTy(); if (OpTy == ShTy || OpTy.isVector()) return Op; ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; @@ -1364,10 +1364,10 @@ SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) { /// CreateStackTemporary - Create a stack temporary, suitable for holding the /// specified value type. -SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { +SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) { MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo(); unsigned ByteSize = VT.getStoreSizeInBits()/8; - const Type *Ty = VT.getTypeForMVT(); + const Type *Ty = VT.getTypeForEVT(); unsigned StackAlign = std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign); @@ -1377,11 +1377,11 @@ SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) { /// CreateStackTemporary - Create a stack temporary suitable for holding /// either of the specified value types. -SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { +SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) { unsigned Bytes = std::max(VT1.getStoreSizeInBits(), VT2.getStoreSizeInBits())/8; - const Type *Ty1 = VT1.getTypeForMVT(); - const Type *Ty2 = VT2.getTypeForMVT(); + const Type *Ty1 = VT1.getTypeForEVT(); + const Type *Ty2 = VT2.getTypeForEVT(); const TargetData *TD = TLI.getTargetData(); unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1), TD->getPrefTypeAlignment(Ty2)); @@ -1391,7 +1391,7 @@ SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) { return getFrameIndex(FrameIdx, TLI.getPointerTy()); } -SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, +SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, DebugLoc dl) { // These setcc operations always fold. switch (Cond) { @@ -1438,7 +1438,7 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1, if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) { if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) { // No compile time operations on this type yet. - if (N1C->getValueType(0) == MVT::ppcf128) + if (N1C->getValueType(0) == EVT::ppcf128) return SDValue(); APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF()); @@ -1727,7 +1727,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, } return; case ISD::SIGN_EXTEND_INREG: { - MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); unsigned EBits = EVT.getSizeInBits(); // Sign extension. Compute the demanded bits in the result that are not @@ -1772,14 +1772,14 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, case ISD::LOAD: { if (ISD::isZEXTLoad(Op.getNode())) { LoadSDNode *LD = cast<LoadSDNode>(Op); - MVT VT = LD->getMemoryVT(); + EVT VT = LD->getMemoryVT(); unsigned MemBits = VT.getSizeInBits(); KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask; } return; } case ISD::ZERO_EXTEND: { - MVT InVT = Op.getOperand(0).getValueType(); + EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getSizeInBits(); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; APInt InMask = Mask; @@ -1793,7 +1793,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, return; } case ISD::SIGN_EXTEND: { - MVT InVT = Op.getOperand(0).getValueType(); + EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getSizeInBits(); APInt InSignBit = APInt::getSignBit(InBits); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask; @@ -1834,7 +1834,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, return; } case ISD::ANY_EXTEND: { - MVT InVT = Op.getOperand(0).getValueType(); + EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.trunc(InBits); @@ -1846,7 +1846,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, return; } case ISD::TRUNCATE: { - MVT InVT = Op.getOperand(0).getValueType(); + EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getSizeInBits(); APInt InMask = Mask; InMask.zext(InBits); @@ -1859,7 +1859,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, break; } case ISD::AssertZext: { - MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero, KnownOne, Depth+1); @@ -1978,7 +1978,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask, /// information. For example, immediately after an "SRA X, 2", we know that /// the top 3 bits are all equal to each other, so we return 3. unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{ - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); assert(VT.isInteger() && "Invalid VT!"); unsigned VTBits = VT.getSizeInBits(); unsigned Tmp, Tmp2; @@ -2213,7 +2213,7 @@ bool SelectionDAG::isVerifiedDebugInfoDesc(SDValue Op) const { /// element of the result of the vector shuffle. SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, unsigned i) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); if (N->getMaskElt(i) < 0) return getUNDEF(VT.getVectorElementType()); @@ -2224,7 +2224,7 @@ SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, if (V.getOpcode() == ISD::BIT_CONVERT) { V = V.getOperand(0); - MVT VVT = V.getValueType(); + EVT VVT = V.getValueType(); if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems) return SDValue(); } @@ -2241,7 +2241,7 @@ SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N, /// getNode - Gets or creates the specified node. /// -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0); void *IP = 0; @@ -2259,7 +2259,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) { } SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, - MVT VT, SDValue Operand) { + EVT VT, SDValue Operand) { // Constant fold unary operations with an integer constant operand. if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) { const APInt &Val = C->getAPIntValue(); @@ -2276,7 +2276,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, case ISD::SINT_TO_FP: { const uint64_t zero[] = {0, 0}; // No compile time operations on this type. - if (VT==MVT::ppcf128) + if (VT==EVT::ppcf128) break; APFloat apf = APFloat(APInt(BitWidth, 2, zero)); (void)apf.convertFromAPInt(Val, @@ -2285,9 +2285,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, return getConstantFP(apf, VT); } case ISD::BIT_CONVERT: - if (VT == MVT::f32 && C->getValueType(0) == MVT::i32) + if (VT == EVT::f32 && C->getValueType(0) == EVT::i32) return getConstantFP(Val.bitsToFloat(), VT); - else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64) + else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64) return getConstantFP(Val.bitsToDouble(), VT); break; case ISD::BSWAP: @@ -2304,7 +2304,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, // Constant fold unary operations with a floating point constant operand. if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) { APFloat V = C->getValueAPF(); // make copy - if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) { + if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) { switch (Opcode) { case ISD::FNEG: V.changeSign(); @@ -2317,7 +2317,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, bool ignored; // This can return overflow, underflow, or inexact; we don't care. // FIXME need to be more flexible about rounding mode. - (void)V.convert(*MVTToAPFloatSemantics(VT), + (void)V.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven, &ignored); return getConstantFP(V, VT); } @@ -2336,9 +2336,9 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, return getConstant(api, VT); } case ISD::BIT_CONVERT: - if (VT == MVT::i32 && C->getValueType(0) == MVT::f32) + if (VT == EVT::i32 && C->getValueType(0) == EVT::f32) return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT); - else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64) + else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64) return getConstant(V.bitcastToAPInt().getZExtValue(), VT); break; } @@ -2449,7 +2449,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDNode *N; SDVTList VTs = getVTList(VT); - if (VT != MVT::Flag) { // Don't CSE flag producing nodes + if (VT != EVT::Flag) { // Don't CSE flag producing nodes FoldingSetNodeID ID; SDValue Ops[1] = { Operand }; AddNodeIDNode(ID, Opcode, VTs, Ops, 1); @@ -2472,7 +2472,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, } SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, - MVT VT, + EVT VT, ConstantSDNode *Cst1, ConstantSDNode *Cst2) { const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue(); @@ -2507,15 +2507,15 @@ SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, return SDValue(); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2) { ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); switch (Opcode) { default: break; case ISD::TokenFactor: - assert(VT == MVT::Other && N1.getValueType() == MVT::Other && - N2.getValueType() == MVT::Other && "Invalid token factor!"); + assert(VT == EVT::Other && N1.getValueType() == EVT::Other && + N2.getValueType() == EVT::Other && "Invalid token factor!"); // Fold trivial token factors. if (N1.getOpcode() == ISD::EntryToken) return N2; if (N2.getOpcode() == ISD::EntryToken) return N1; @@ -2605,11 +2605,11 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, // Always fold shifts of i1 values so the code generator doesn't need to // handle them. Since we know the size of the shift has to be less than the // size of the value, the shift/rotate count is guaranteed to be zero. - if (VT == MVT::i1) + if (VT == EVT::i1) return N1; break; case ISD::FP_ROUND_INREG: { - MVT EVT = cast<VTSDNode>(N2)->getVT(); + EVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg round!"); assert(VT.isFloatingPoint() && EVT.isFloatingPoint() && "Cannot FP_ROUND_INREG integer types"); @@ -2626,7 +2626,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, break; case ISD::AssertSext: case ISD::AssertZext: { - MVT EVT = cast<VTSDNode>(N2)->getVT(); + EVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); @@ -2635,7 +2635,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, break; } case ISD::SIGN_EXTEND_INREG: { - MVT EVT = cast<VTSDNode>(N2)->getVT(); + EVT EVT = cast<VTSDNode>(N2)->getVT(); assert(VT == N1.getValueType() && "Not an inreg extend!"); assert(VT.isInteger() && EVT.isInteger() && "Cannot *_EXTEND_INREG FP types"); @@ -2673,7 +2673,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, // expanding large vector constants. if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) { SDValue Elt = N1.getOperand(N2C->getZExtValue()); - MVT VEltTy = N1.getValueType().getVectorElementType(); + EVT VEltTy = N1.getValueType().getVectorElementType(); if (Elt.getValueType() != VEltTy) { // If the vector element type is not legal, the BUILD_VECTOR operands // are promoted and implicitly truncated. Make that explicit here. @@ -2746,7 +2746,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, // Cannonicalize constant to RHS if commutative std::swap(N1CFP, N2CFP); std::swap(N1, N2); - } else if (N2CFP && VT != MVT::ppcf128) { + } else if (N2CFP && VT != EVT::ppcf128) { APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF(); APFloat::opStatus s; switch (Opcode) { @@ -2861,7 +2861,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, // Memoize this node if possible. SDNode *N; SDVTList VTs = getVTList(VT); - if (VT != MVT::Flag) { + if (VT != EVT::Flag) { SDValue Ops[] = { N1, N2 }; FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTs, Ops, 2); @@ -2883,7 +2883,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) { // Perform various simplifications. ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); @@ -2920,7 +2920,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, case ISD::BRCOND: if (N2C) { if (N2C->getZExtValue()) // Unconditional branch - return getNode(ISD::BR, DL, MVT::Other, N1, N3); + return getNode(ISD::BR, DL, EVT::Other, N1, N3); else return N1; // Never-taken branch } @@ -2938,7 +2938,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, // Memoize node if it doesn't produce a flag. SDNode *N; SDVTList VTs = getVTList(VT); - if (VT != MVT::Flag) { + if (VT != EVT::Flag) { SDValue Ops[] = { N1, N2, N3 }; FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTs, Ops, 3); @@ -2959,14 +2959,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return SDValue(N, 0); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) { SDValue Ops[] = { N1, N2, N3, N4 }; return getNode(Opcode, DL, VT, Ops, 4); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) { SDValue Ops[] = { N1, N2, N3, N4, N5 }; @@ -2992,13 +2992,13 @@ SDValue SelectionDAG::getStackArgumentTokenFactor(SDValue Chain) { ArgChains.push_back(SDValue(L, 1)); // Build a tokenfactor for all the chains. - return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other, + return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other, &ArgChains[0], ArgChains.size()); } /// getMemsetValue - Vectorized representation of the memset value /// operand. -static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, +static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG, DebugLoc dl) { unsigned NumBits = VT.isVector() ? VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits(); @@ -3032,7 +3032,7 @@ static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG, /// getMemsetStringVal - Similar to getMemsetValue. Except this is only /// used when a memcpy is turned into a memset when the source is a constant /// string ptr. -static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, +static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG, const TargetLowering &TLI, std::string &Str, unsigned Offset) { // Handle vector with all elements zero. @@ -3040,9 +3040,9 @@ static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, if (VT.isInteger()) return DAG.getConstant(0, VT); unsigned NumElts = VT.getVectorNumElements(); - MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64; + EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64; return DAG.getNode(ISD::BIT_CONVERT, dl, VT, - DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts))); + DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts))); } assert(!VT.isVector() && "Can't handle vector type here!"); @@ -3062,7 +3062,7 @@ static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG, /// static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SelectionDAG &DAG) { - MVT VT = Base.getValueType(); + EVT VT = Base.getValueType(); return DAG.getNode(ISD::ADD, Base.getDebugLoc(), VT, Base, DAG.getConstant(Offset, VT)); } @@ -3094,7 +3094,7 @@ static bool isMemSrcFromString(SDValue Src, std::string &Str) { /// to replace the memset / memcpy is below the threshold. It also returns the /// types of the sequence of memory ops to perform memset / memcpy. static -bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, +bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps, SDValue Dst, SDValue Src, unsigned Limit, uint64_t Size, unsigned &Align, std::string &Str, bool &isSrcStr, @@ -3103,23 +3103,23 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, isSrcStr = isMemSrcFromString(Src, Str); bool isSrcConst = isa<ConstantSDNode>(Src); bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses(); - MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); - if (VT != MVT::iAny) { + EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG); + if (VT != EVT::iAny) { unsigned NewAlign = (unsigned) - TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT()); + TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT()); // If source is a string constant, this will require an unaligned load. if (NewAlign > Align && (isSrcConst || AllowUnalign)) { if (Dst.getOpcode() != ISD::FrameIndex) { // Can't change destination alignment. It requires a unaligned store. if (AllowUnalign) - VT = MVT::iAny; + VT = EVT::iAny; } else { int FI = cast<FrameIndexSDNode>(Dst)->getIndex(); MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); if (MFI->isFixedObjectIndex(FI)) { // Can't change destination alignment. It requires a unaligned store. if (AllowUnalign) - VT = MVT::iAny; + VT = EVT::iAny; } else { // Give the stack frame object a larger alignment if needed. if (MFI->getObjectAlignment(FI) < NewAlign) @@ -3130,21 +3130,21 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, } } - if (VT == MVT::iAny) { + if (VT == EVT::iAny) { if (AllowUnalign) { - VT = MVT::i64; + VT = EVT::i64; } else { switch (Align & 7) { - case 0: VT = MVT::i64; break; - case 4: VT = MVT::i32; break; - case 2: VT = MVT::i16; break; - default: VT = MVT::i8; break; + case 0: VT = EVT::i64; break; + case 4: VT = EVT::i32; break; + case 2: VT = EVT::i16; break; + default: VT = EVT::i8; break; } } - MVT LVT = MVT::i64; + EVT LVT = EVT::i64; while (!TLI.isTypeLegal(LVT)) - LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1); + LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1); assert(LVT.isInteger()); if (VT.bitsGT(LVT)) @@ -3157,14 +3157,14 @@ bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps, while (VTSize > Size) { // For now, only use non-vector load / store's for the left-over pieces. if (VT.isVector()) { - VT = MVT::i64; + VT = EVT::i64; while (!TLI.isTypeLegal(VT)) - VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); + VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize = VT.getSizeInBits() / 8; } else { // This can result in a type that is not legal on the target, e.g. // 1 or 2 bytes on PPC. - VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1); + VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1); VTSize >>= 1; } } @@ -3188,7 +3188,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, // Expand memcpy to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector<MVT> MemOps; + std::vector<EVT> MemOps; uint64_t Limit = -1ULL; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemcpy(); @@ -3205,7 +3205,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, unsigned NumMemOps = MemOps.size(); uint64_t SrcOff = 0, DstOff = 0; for (unsigned i = 0; i < NumMemOps; i++) { - MVT VT = MemOps[i]; + EVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; @@ -3225,7 +3225,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, // thing to do is generate a LoadExt/StoreTrunc pair. These simplify // to Load/Store if NVT==VT. // FIXME does the case above also need this? - MVT NVT = TLI.getTypeToTransformTo(VT); + EVT NVT = TLI.getTypeToTransformTo(VT); assert(NVT.bitsGE(VT)); Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain, getMemBasePlusOffset(Src, SrcOff, DAG), @@ -3239,7 +3239,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &OutChains[0], OutChains.size()); } @@ -3253,7 +3253,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, // Expand memmove to a series of load and store ops if the size operand falls // below a certain threshold. - std::vector<MVT> MemOps; + std::vector<EVT> MemOps; uint64_t Limit = -1ULL; if (!AlwaysInline) Limit = TLI.getMaxStoresPerMemmove(); @@ -3271,7 +3271,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, SmallVector<SDValue, 8> OutChains; unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT VT = MemOps[i]; + EVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; @@ -3282,11 +3282,11 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, LoadChains.push_back(Value.getValue(1)); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LoadChains[0], LoadChains.size()); OutChains.clear(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT VT = MemOps[i]; + EVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value, Store; @@ -3297,7 +3297,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, DebugLoc dl, DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &OutChains[0], OutChains.size()); } @@ -3310,7 +3310,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, // Expand memset to a series of load/store ops if the size operand // falls below a certain threshold. - std::vector<MVT> MemOps; + std::vector<EVT> MemOps; std::string Str; bool CopyFromStr; if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(), @@ -3322,7 +3322,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, unsigned NumMemOps = MemOps.size(); for (unsigned i = 0; i < NumMemOps; i++) { - MVT VT = MemOps[i]; + EVT VT = MemOps[i]; unsigned VTSize = VT.getSizeInBits() / 8; SDValue Value = getMemsetValue(Src, VT, DAG, dl); SDValue Store = DAG.getStore(Chain, dl, Value, @@ -3332,7 +3332,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, DebugLoc dl, DstOff += VTSize; } - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &OutChains[0], OutChains.size()); } @@ -3477,10 +3477,10 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, Entry.Node = Dst; Entry.Ty = IntPtrTy; Args.push_back(Entry); // Extend or truncate the argument to be an i32 value for the call. - if (Src.getValueType().bitsGT(MVT::i32)) - Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src); + if (Src.getValueType().bitsGT(EVT::i32)) + Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src); else - Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); + Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src); Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true; Args.push_back(Entry); Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false; @@ -3496,7 +3496,7 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst, return CallResult.second; } -SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, const Value* PtrVal, @@ -3504,12 +3504,12 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op"); assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types"); - MVT VT = Cmp.getValueType(); + EVT VT = Cmp.getValueType(); if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); + Alignment = getEVTAlignment(MemVT); - SDVTList VTs = getVTList(VT, MVT::Other); + SDVTList VTs = getVTList(VT, EVT::Other); FoldingSetNodeID ID; ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Cmp, Swp}; @@ -3525,7 +3525,7 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, return SDValue(N, 0); } -SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, +SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, const Value* PtrVal, @@ -3543,12 +3543,12 @@ SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT, Opcode == ISD::ATOMIC_SWAP) && "Invalid Atomic Op"); - MVT VT = Val.getValueType(); + EVT VT = Val.getValueType(); if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(MemVT); + Alignment = getEVTAlignment(MemVT); - SDVTList VTs = getVTList(VT, MVT::Other); + SDVTList VTs = getVTList(VT, EVT::Other); FoldingSetNodeID ID; ID.AddInteger(MemVT.getRawBits()); SDValue Ops[] = {Chain, Ptr, Val}; @@ -3571,7 +3571,7 @@ SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, if (NumOps == 1) return Ops[0]; - SmallVector<MVT, 4> VTs; + SmallVector<EVT, 4> VTs; VTs.reserve(NumOps); for (unsigned i = 0; i < NumOps; ++i) VTs.push_back(Ops[i].getValueType()); @@ -3581,9 +3581,9 @@ SDValue SelectionDAG::getMergeValues(const SDValue *Ops, unsigned NumOps, SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, - const MVT *VTs, unsigned NumVTs, + const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, + EVT MemVT, const Value *srcValue, int SVOff, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) { return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps, @@ -3594,12 +3594,12 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDValue SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, const SDValue *Ops, unsigned NumOps, - MVT MemVT, const Value *srcValue, int SVOff, + EVT MemVT, const Value *srcValue, int SVOff, unsigned Align, bool Vol, bool ReadMem, bool WriteMem) { // Memoize the node unless it returns a flag. MemIntrinsicSDNode *N; - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { + if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); void *IP = 0; @@ -3621,12 +3621,12 @@ SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList, SDValue SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, - ISD::LoadExtType ExtType, MVT VT, SDValue Chain, + ISD::LoadExtType ExtType, EVT VT, SDValue Chain, SDValue Ptr, SDValue Offset, - const Value *SV, int SVOffset, MVT EVT, + const Value *SV, int SVOffset, EVT EVT, bool isVolatile, unsigned Alignment) { if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); + Alignment = getEVTAlignment(VT); if (VT == EVT) { ExtType = ISD::NON_EXTLOAD; @@ -3651,7 +3651,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, "Unindexed load with an offset!"); SDVTList VTs = Indexed ? - getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other); + getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other); SDValue Ops[] = { Chain, Ptr, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3); @@ -3668,7 +3668,7 @@ SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl, return SDValue(N, 0); } -SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, +SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { @@ -3677,10 +3677,10 @@ SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl, SV, SVOffset, VT, isVolatile, Alignment); } -SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT, +SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT, SDValue Chain, SDValue Ptr, const Value *SV, - int SVOffset, MVT EVT, + int SVOffset, EVT EVT, bool isVolatile, unsigned Alignment) { SDValue Undef = getUNDEF(Ptr.getValueType()); return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef, @@ -3702,12 +3702,12 @@ SelectionDAG::getIndexedLoad(SDValue OrigLoad, DebugLoc dl, SDValue Base, SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, int SVOffset, bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); + EVT VT = Val.getValueType(); if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); + Alignment = getEVTAlignment(VT); - SDVTList VTs = getVTList(MVT::Other); + SDVTList VTs = getVTList(EVT::Other); SDValue Undef = getUNDEF(Ptr.getValueType()); SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; @@ -3728,9 +3728,9 @@ SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, SDValue Ptr, const Value *SV, - int SVOffset, MVT SVT, + int SVOffset, EVT SVT, bool isVolatile, unsigned Alignment) { - MVT VT = Val.getValueType(); + EVT VT = Val.getValueType(); if (VT == SVT) return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment); @@ -3740,9 +3740,9 @@ SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val, "Can't do FP-INT conversion!"); if (Alignment == 0) // Ensure that codegen never sees alignment 0 - Alignment = getMVTAlignment(VT); + Alignment = getEVTAlignment(VT); - SDVTList VTs = getVTList(MVT::Other); + SDVTList VTs = getVTList(EVT::Other); SDValue Undef = getUNDEF(Ptr.getValueType()); SDValue Ops[] = { Chain, Val, Ptr, Undef }; FoldingSetNodeID ID; @@ -3767,7 +3767,7 @@ SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, StoreSDNode *ST = cast<StoreSDNode>(OrigStore); assert(ST->getOffset().getOpcode() == ISD::UNDEF && "Store is already a indexed store!"); - SDVTList VTs = getVTList(Base.getValueType(), MVT::Other); + SDVTList VTs = getVTList(Base.getValueType(), EVT::Other); SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset }; FoldingSetNodeID ID; AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4); @@ -3786,14 +3786,14 @@ SelectionDAG::getIndexedStore(SDValue OrigStore, DebugLoc dl, SDValue Base, return SDValue(N, 0); } -SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl, +SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl, SDValue Chain, SDValue Ptr, SDValue SV) { SDValue Ops[] = { Chain, Ptr, SV }; - return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3); + return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDUse *Ops, unsigned NumOps) { switch (NumOps) { case 0: return getNode(Opcode, DL, VT); @@ -3809,7 +3809,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, return getNode(Opcode, DL, VT, &NewOps[0], NumOps); } -SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, +SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT, const SDValue *Ops, unsigned NumOps) { switch (NumOps) { case 0: return getNode(Opcode, DL, VT); @@ -3843,7 +3843,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, SDNode *N; SDVTList VTs = getVTList(VT); - if (VT != MVT::Flag) { + if (VT != EVT::Flag) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps); void *IP = 0; @@ -3867,14 +3867,14 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT, } SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, - const std::vector<MVT> &ResultTys, + const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) { return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()), Ops, NumOps); } SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, - const MVT *VTs, unsigned NumVTs, + const EVT *VTs, unsigned NumVTs, const SDValue *Ops, unsigned NumOps) { if (NumVTs == 1) return getNode(Opcode, DL, VTs[0], Ops, NumOps); @@ -3895,7 +3895,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, case ISD::SRL_PARTS: case ISD::SHL_PARTS: if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG && - cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1) + cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1) return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0)); else if (N3.getOpcode() == ISD::AND) if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) { @@ -3911,7 +3911,7 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, // Memoize the node unless it returns a flag. SDNode *N; - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { + if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); void *IP = 0; @@ -3989,17 +3989,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, return getNode(Opcode, DL, VTList, Ops, 5); } -SDVTList SelectionDAG::getVTList(MVT VT) { +SDVTList SelectionDAG::getVTList(EVT VT) { return makeVTList(SDNode::getValueTypeList(VT), 1); } -SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { +SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) { for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), E = VTList.rend(); I != E; ++I) if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2) return *I; - MVT *Array = Allocator.Allocate<MVT>(2); + EVT *Array = Allocator.Allocate<EVT>(2); Array[0] = VT1; Array[1] = VT2; SDVTList Result = makeVTList(Array, 2); @@ -4007,14 +4007,14 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) { return Result; } -SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { +SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) { for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), E = VTList.rend(); I != E; ++I) if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && I->VTs[2] == VT3) return *I; - MVT *Array = Allocator.Allocate<MVT>(3); + EVT *Array = Allocator.Allocate<EVT>(3); Array[0] = VT1; Array[1] = VT2; Array[2] = VT3; @@ -4023,14 +4023,14 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) { return Result; } -SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { +SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) { for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(), E = VTList.rend(); I != E; ++I) if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 && I->VTs[2] == VT3 && I->VTs[3] == VT4) return *I; - MVT *Array = Allocator.Allocate<MVT>(3); + EVT *Array = Allocator.Allocate<EVT>(3); Array[0] = VT1; Array[1] = VT2; Array[2] = VT3; @@ -4040,7 +4040,7 @@ SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) { return Result; } -SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { +SDVTList SelectionDAG::getVTList(const EVT *VTs, unsigned NumVTs) { switch (NumVTs) { case 0: llvm_unreachable("Cannot have nodes without results!"); case 1: return getVTList(VTs[0]); @@ -4064,7 +4064,7 @@ SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) { return *I; } - MVT *Array = Allocator.Allocate<MVT>(NumVTs); + EVT *Array = Allocator.Allocate<EVT>(NumVTs); std::copy(VTs, VTs+NumVTs, Array); SDVTList Result = makeVTList(Array, NumVTs); VTList.push_back(Result); @@ -4206,20 +4206,20 @@ void SDNode::DropOperands() { /// machine opcode. /// SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT) { + EVT VT) { SDVTList VTs = getVTList(VT); return SelectNodeTo(N, MachineOpc, VTs, 0, 0); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT, SDValue Op1) { + EVT VT, SDValue Op1) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1 }; return SelectNodeTo(N, MachineOpc, VTs, Ops, 1); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT, SDValue Op1, + EVT VT, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1, Op2 }; @@ -4227,7 +4227,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT, SDValue Op1, + EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1, Op2, Op3 }; @@ -4235,41 +4235,41 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT, const SDValue *Ops, + EVT VT, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT); return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, const SDValue *Ops, + EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2); return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2) { + EVT VT1, EVT VT2) { SDVTList VTs = getVTList(VT1, VT2); return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3); return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, MVT VT3, MVT VT4, + EVT VT1, EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps); } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1 }; @@ -4277,7 +4277,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2 }; @@ -4285,7 +4285,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2); @@ -4294,7 +4294,7 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2, VT3); @@ -4309,20 +4309,20 @@ SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc, } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT) { + EVT VT) { SDVTList VTs = getVTList(VT); return MorphNodeTo(N, Opc, VTs, 0, 0); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT, SDValue Op1) { + EVT VT, SDValue Op1) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1 }; return MorphNodeTo(N, Opc, VTs, Ops, 1); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT, SDValue Op1, + EVT VT, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1, Op2 }; @@ -4330,7 +4330,7 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT, SDValue Op1, + EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT); SDValue Ops[] = { Op1, Op2, Op3 }; @@ -4338,34 +4338,34 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT, const SDValue *Ops, + EVT VT, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT); return MorphNodeTo(N, Opc, VTs, Ops, NumOps); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2, const SDValue *Ops, + EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2); return MorphNodeTo(N, Opc, VTs, Ops, NumOps); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2) { + EVT VT1, EVT VT2) { SDVTList VTs = getVTList(VT1, VT2); return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3); return MorphNodeTo(N, Opc, VTs, Ops, NumOps); } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1 }; @@ -4373,7 +4373,7 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2 }; @@ -4381,7 +4381,7 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, } SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2); @@ -4406,7 +4406,7 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, unsigned NumOps) { // If an identical node already exists, use it. void *IP = 0; - if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) { + if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opc, VTs, Ops, NumOps); if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP)) @@ -4478,54 +4478,54 @@ SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc, /// Note that getTargetNode returns the resultant node. If there is already a /// node of the specified opcode and operands, it returns that node instead of /// the current one. -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT) { return getNode(~Opcode, dl, VT).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1) { return getNode(~Opcode, dl, VT, Op1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2) { return getNode(~Opcode, dl, VT, Op1, Op2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) { return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT, const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, VT, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - MVT VT1, MVT VT2) { + EVT VT1, EVT VT2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Op; return getNode(~Opcode, dl, VTs, &Op, 0).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, - MVT VT2, SDValue Op1) { +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1) { SDVTList VTs = getVTList(VT1, VT2); return getNode(~Opcode, dl, VTs, &Op1, 1).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, - MVT VT2, SDValue Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2 }; return getNode(~Opcode, dl, VTs, Ops, 2).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, - MVT VT2, SDValue Op1, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2); SDValue Ops[] = { Op1, Op2, Op3 }; @@ -4533,14 +4533,14 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - MVT VT1, MVT VT2, + EVT VT1, EVT VT2, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2) { SDVTList VTs = getVTList(VT1, VT2, VT3); SDValue Ops[] = { Op1, Op2 }; @@ -4548,7 +4548,7 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) { SDVTList VTs = getVTList(VT1, VT2, VT3); @@ -4557,21 +4557,21 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - MVT VT1, MVT VT2, MVT VT3, + EVT VT1, EVT VT2, EVT VT3, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } -SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1, - MVT VT2, MVT VT3, MVT VT4, +SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1, + EVT VT2, EVT VT3, EVT VT4, const SDValue *Ops, unsigned NumOps) { SDVTList VTs = getVTList(VT1, VT2, VT3, VT4); return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode(); } SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, - const std::vector<MVT> &ResultTys, + const std::vector<EVT> &ResultTys, const SDValue *Ops, unsigned NumOps) { return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode(); } @@ -4580,7 +4580,7 @@ SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, /// else return NULL. SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList, const SDValue *Ops, unsigned NumOps) { - if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) { + if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) { FoldingSetNodeID ID; AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps); void *IP = 0; @@ -4928,13 +4928,13 @@ HandleSDNode::~HandleSDNode() { } GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA, - MVT VT, int64_t o, unsigned char TF) + EVT VT, int64_t o, unsigned char TF) : SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)), Offset(o), TargetFlags(TF) { TheGlobal = const_cast<GlobalValue*>(GA); } -MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, +MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) : SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { @@ -4946,7 +4946,7 @@ MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt, MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, const SDValue *Ops, - unsigned NumOps, MVT memvt, const Value *srcValue, + unsigned NumOps, EVT memvt, const Value *srcValue, int SVO, unsigned alignment, bool vol) : SDNode(Opc, dl, VTs, Ops, NumOps), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) { @@ -4994,13 +4994,13 @@ void SDNode::Profile(FoldingSetNodeID &ID) const { AddNodeIDNode(ID, this); } -static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs; -static MVT VTs[MVT::LAST_VALUETYPE]; +static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs; +static EVT VTs[EVT::LAST_VALUETYPE]; static ManagedStatic<sys::SmartMutex<true> > VTMutex; /// getValueTypeList - Return a pointer to the specified value type. /// -const MVT *SDNode::getValueTypeList(MVT VT) { +const EVT *SDNode::getValueTypeList(EVT VT) { sys::SmartScopedLock<true> Lock(*VTMutex); if (VT.isExtended()) { return &(*EVTs->insert(VT).first); @@ -5447,10 +5447,10 @@ void SDNode::print_types(raw_ostream &OS, const SelectionDAG *G) const { for (unsigned i = 0, e = getNumValues(); i != e; ++i) { if (i) OS << ","; - if (getValueType(i) == MVT::Other) + if (getValueType(i) == EVT::Other) OS << "ch"; else - OS << getValueType(i).getMVTString(); + OS << getValueType(i).getEVTString(); } OS << " = " << getOperationName(G); } @@ -5541,7 +5541,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { else OS << "<null:" << M->MO.getOffset() << ">"; } else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) { - OS << ":" << N->getVT().getMVTString(); + OS << ":" << N->getVT().getEVTString(); } else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) { const Value *SrcValue = LD->getSrcValue(); @@ -5561,7 +5561,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { case ISD::ZEXTLOAD: OS << " <zext "; break; } if (doExt) - OS << LD->getMemoryVT().getMVTString() << ">"; + OS << LD->getMemoryVT().getEVTString() << ">"; const char *AM = getIndexedModeName(LD->getAddressingMode()); if (*AM) @@ -5580,7 +5580,7 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { OS << ":" << SrcOffset << ">"; if (ST->isTruncatingStore()) - OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">"; + OS << " <trunc " << ST->getMemoryVT().getEVTString() << ">"; const char *AM = getIndexedModeName(ST->getAddressingMode()); if (*AM) @@ -5702,7 +5702,7 @@ bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits) { - MVT VT = getValueType(0); + EVT VT = getValueType(0); assert(VT.isVector() && "Expected a vector type"); unsigned sz = VT.getSizeInBits(); if (MinSplatBits > sz) @@ -5760,7 +5760,7 @@ bool BuildVectorSDNode::isConstantSplat(APInt &SplatValue, return true; } -bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) { +bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) { // Find the first non-undef value in the shuffle mask. unsigned i, e; for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i) diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 929740dd37..0180069623 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -106,14 +106,14 @@ static unsigned ComputeLinearIndex(const TargetLowering &TLI, const Type *Ty, } /// ComputeValueVTs - Given an LLVM IR type, compute a sequence of -/// MVTs that represent all the individual underlying +/// EVTs that represent all the individual underlying /// non-aggregate types that comprise it. /// /// If Offsets is non-null, it points to a vector to be filled in /// with the in-memory offsets of each of the individual values. /// static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, - SmallVectorImpl<MVT> &ValueVTs, + SmallVectorImpl<EVT> &ValueVTs, SmallVectorImpl<uint64_t> *Offsets = 0, uint64_t StartingOffset = 0) { // Given a struct type, recursively traverse the elements. @@ -139,7 +139,7 @@ static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty, // Interpret void as zero return values. if (Ty == Type::VoidTy) return; - // Base case: we can get an MVT for this LLVM IR type. + // Base case: we can get an EVT for this LLVM IR type. ValueVTs.push_back(TLI.getValueType(Ty)); if (Offsets) Offsets->push_back(StartingOffset); @@ -163,7 +163,7 @@ namespace llvm { /// ValueVTs - The value types of the values, which may not be legal, and /// may need be promoted or synthesized from one or more registers. /// - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; /// RegVTs - The value types of the registers. This is the same size as /// ValueVTs and it records, for each value, what the type of the assigned @@ -174,7 +174,7 @@ namespace llvm { /// getRegisterType member function, however when with physical registers /// it is necessary to have a separate record of the types. /// - SmallVector<MVT, 4> RegVTs; + SmallVector<EVT, 4> RegVTs; /// Regs - This list holds the registers assigned to the values. /// Each legal or promoted value requires one register, and each @@ -186,21 +186,21 @@ namespace llvm { RegsForValue(const TargetLowering &tli, const SmallVector<unsigned, 4> ®s, - MVT regvt, MVT valuevt) + EVT regvt, EVT valuevt) : TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} RegsForValue(const TargetLowering &tli, const SmallVector<unsigned, 4> ®s, - const SmallVector<MVT, 4> ®vts, - const SmallVector<MVT, 4> &valuevts) + const SmallVector<EVT, 4> ®vts, + const SmallVector<EVT, 4> &valuevts) : TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {} RegsForValue(const TargetLowering &tli, unsigned Reg, const Type *Ty) : TLI(&tli) { ComputeValueVTs(tli, Ty, ValueVTs); for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT ValueVT = ValueVTs[Value]; + EVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT RegisterVT = TLI->getRegisterType(ValueVT); + EVT RegisterVT = TLI->getRegisterType(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) Regs.push_back(Reg + i); RegVTs.push_back(RegisterVT); @@ -354,10 +354,10 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, unsigned PHIReg = ValueMap[PN]; assert(PHIReg && "PHI node does not have an assigned virtual register!"); - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, PN->getType(), ValueVTs); for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { - MVT VT = ValueVTs[vti]; + EVT VT = ValueVTs[vti]; unsigned NumRegisters = TLI.getNumRegisters(VT); const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); for (unsigned i = 0; i != NumRegisters; ++i) @@ -368,7 +368,7 @@ void FunctionLoweringInfo::set(Function &fn, MachineFunction &mf, } } -unsigned FunctionLoweringInfo::MakeReg(MVT VT) { +unsigned FunctionLoweringInfo::MakeReg(EVT VT) { return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -380,13 +380,13 @@ unsigned FunctionLoweringInfo::MakeReg(MVT VT) { /// will assign registers for each member or element. /// unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, V->getType(), ValueVTs); unsigned FirstReg = 0; for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT ValueVT = ValueVTs[Value]; - MVT RegisterVT = TLI.getRegisterType(ValueVT); + EVT ValueVT = ValueVTs[Value]; + EVT RegisterVT = TLI.getRegisterType(ValueVT); unsigned NumRegs = TLI.getNumRegisters(ValueVT); for (unsigned i = 0; i != NumRegs; ++i) { @@ -404,7 +404,7 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { /// (ISD::AssertSext). static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, const SDValue *Parts, - unsigned NumParts, MVT PartVT, MVT ValueVT, + unsigned NumParts, EVT PartVT, EVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -420,11 +420,11 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, unsigned RoundParts = NumParts & (NumParts - 1) ? 1 << Log2_32(NumParts) : NumParts; unsigned RoundBits = PartBits * RoundParts; - MVT RoundVT = RoundBits == ValueBits ? - ValueVT : MVT::getIntegerVT(RoundBits); + EVT RoundVT = RoundBits == ValueBits ? + ValueVT : EVT::getIntegerVT(RoundBits); SDValue Lo, Hi; - MVT HalfVT = MVT::getIntegerVT(RoundBits/2); + EVT HalfVT = EVT::getIntegerVT(RoundBits/2); if (RoundParts > 2) { Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT); @@ -441,7 +441,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; - MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); + EVT OddVT = EVT::getIntegerVT(OddParts * PartBits); Hi = getCopyFromParts(DAG, dl, Parts+RoundParts, OddParts, PartVT, OddVT); @@ -449,7 +449,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); - MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); + EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits); Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, DAG.getConstant(Lo.getValueType().getSizeInBits(), @@ -459,7 +459,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, } } else if (ValueVT.isVector()) { // Handle a multi-element vector. - MVT IntermediateVT, RegisterVT; + EVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, @@ -496,11 +496,11 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, ValueVT, &Ops[0], NumIntermediates); } else if (PartVT.isFloatingPoint()) { // FP split into multiple FP parts (for ppcf128) - assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) && + assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) && "Unexpected split"); SDValue Lo, Hi; - Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]); - Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]); if (TLI.isBigEndian()) std::swap(Lo, Hi); Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi); @@ -508,7 +508,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, // FP split into integer parts (soft fp) assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && !PartVT.isVector() && "Unexpected split"); - MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits()); + EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits()); Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT); } } @@ -565,11 +565,11 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, /// split into legal parts. If the parts contain more bits than Val, then, for /// integers, ExtendKind can be used to specify how to generate the extra bits. static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, - SDValue *Parts, unsigned NumParts, MVT PartVT, + SDValue *Parts, unsigned NumParts, EVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - MVT PtrVT = TLI.getPointerTy(); - MVT ValueVT = Val.getValueType(); + EVT PtrVT = TLI.getPointerTy(); + EVT ValueVT = Val.getValueType(); unsigned PartBits = PartVT.getSizeInBits(); unsigned OrigNumParts = NumParts; assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); @@ -590,7 +590,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, assert(NumParts == 1 && "Do not know what to promote to!"); Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); } else if (PartVT.isInteger() && ValueVT.isInteger()) { - ValueVT = MVT::getIntegerVT(NumParts * PartBits); + ValueVT = EVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { llvm_unreachable("Unknown mismatch!"); @@ -602,7 +602,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. if (PartVT.isInteger() && ValueVT.isInteger()) { - ValueVT = MVT::getIntegerVT(NumParts * PartBits); + ValueVT = EVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { llvm_unreachable("Unknown mismatch!"); @@ -636,19 +636,19 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; - ValueVT = MVT::getIntegerVT(NumParts * PartBits); + ValueVT = EVT::getIntegerVT(NumParts * PartBits); Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::getIntegerVT(ValueVT.getSizeInBits()), + EVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { for (unsigned i = 0; i < NumParts; i += StepSize) { unsigned ThisBits = StepSize * PartBits / 2; - MVT ThisVT = MVT::getIntegerVT (ThisBits); + EVT ThisVT = EVT::getIntegerVT (ThisBits); SDValue &Part0 = Parts[i]; SDValue &Part1 = Parts[i+StepSize/2]; @@ -694,7 +694,7 @@ static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, } // Handle a multi-element vector. - MVT IntermediateVT, RegisterVT; + EVT IntermediateVT, RegisterVT; unsigned NumIntermediates; unsigned NumRegs = TLI .getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates, @@ -774,7 +774,7 @@ SDValue SelectionDAGLowering::getRoot() { } // Otherwise, we have to make a token factor node. - SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, + SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other, &PendingLoads[0], PendingLoads.size()); PendingLoads.clear(); DAG.setRoot(Root); @@ -804,7 +804,7 @@ SDValue SelectionDAGLowering::getControlRoot() { PendingExports.push_back(Root); } - Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other, &PendingExports[0], PendingExports.size()); PendingExports.clear(); @@ -833,7 +833,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { if (N.getNode()) return N; if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) { - MVT VT = TLI.getValueType(V->getType(), true); + EVT VT = TLI.getValueType(V->getType(), true); if (ConstantInt *CI = dyn_cast<ConstantInt>(C)) return N = DAG.getConstant(*CI, VT); @@ -873,14 +873,14 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && "Unknown struct or array constant!"); - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, C->getType(), ValueVTs); unsigned NumElts = ValueVTs.size(); if (NumElts == 0) return SDValue(); // empty struct SmallVector<SDValue, 4> Constants(NumElts); for (unsigned i = 0; i != NumElts; ++i) { - MVT EltVT = ValueVTs[i]; + EVT EltVT = ValueVTs[i]; if (isa<UndefValue>(C)) Constants[i] = DAG.getUNDEF(EltVT); else if (EltVT.isFloatingPoint()) @@ -902,7 +902,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { Ops.push_back(getValue(CP->getOperand(i))); } else { assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); - MVT EltVT = TLI.getValueType(VecTy->getElementType()); + EVT EltVT = TLI.getValueType(VecTy->getElementType()); SDValue Op; if (EltVT.isFloatingPoint()) @@ -939,14 +939,14 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { SDValue Chain = getControlRoot(); SmallVector<ISD::OutputArg, 8> Outs; for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) { - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (NumValues == 0) continue; SDValue RetOp = getValue(I.getOperand(i)); for (unsigned j = 0, f = NumValues; j != f; ++j) { - MVT VT = ValueVTs[j]; + EVT VT = ValueVTs[j]; ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -961,13 +961,13 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { // conventions. The frontend should mark functions whose return values // require promoting with signext or zeroext attributes. if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { - MVT MinVT = TLI.getRegisterType(MVT::i32); + EVT MinVT = TLI.getRegisterType(EVT::i32); if (VT.bitsLT(MinVT)) VT = MinVT; } unsigned NumParts = TLI.getNumRegisters(VT); - MVT PartVT = TLI.getRegisterType(VT); + EVT PartVT = TLI.getRegisterType(VT); SmallVector<SDValue, 4> Parts(NumParts); getCopyToParts(DAG, getCurDebugLoc(), SDValue(RetOp.getNode(), RetOp.getResNo() + j), @@ -995,7 +995,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { Outs, getCurDebugLoc(), DAG); // Verify that the target's LowerReturn behaved as expected. - assert(Chain.getNode() && Chain.getValueType() == MVT::Other && + assert(Chain.getNode() && Chain.getValueType() == EVT::Other && "LowerReturn didn't return a valid chain!"); // Update the DAG with the new chain value resulting from return lowering. @@ -1250,7 +1250,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // If this is not a fall-through branch, emit the branch. if (Succ0MBB != NextBlock) DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), - MVT::Other, getControlRoot(), + EVT::Other, getControlRoot(), DAG.getBasicBlock(Succ0MBB))); return; } @@ -1334,7 +1334,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); } else - Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); + Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); } else { assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); @@ -1342,15 +1342,15 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); SDValue CmpOp = getValue(CB.CmpMHS); - MVT VT = CmpOp.getValueType(); + EVT VT = CmpOp.getValueType(); if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { - Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), + Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); } else { SDValue SUB = DAG.getNode(ISD::SUB, dl, VT, CmpOp, DAG.getConstant(Low, VT)); - Cond = DAG.getSetCC(dl, MVT::i1, SUB, + Cond = DAG.getSetCC(dl, EVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); } } @@ -1374,7 +1374,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); } SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, - MVT::Other, getControlRoot(), Cond, + EVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); // If the branch was constant folded, fix up the CFG. @@ -1389,7 +1389,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1398,12 +1398,12 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { void SelectionDAGLowering::visitJumpTable(JumpTable &JT) { // Emit the code for the jump table assert(JT.Reg != -1U && "Should lower JT Header first!"); - MVT PTy = TLI.getPointerTy(); + EVT PTy = TLI.getPointerTy(); SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), - MVT::Other, Index.getValue(1), + EVT::Other, Index.getValue(1), Table, Index)); } @@ -1415,7 +1415,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, // conditional branch to default mbb if the result is greater than the // difference between smallest and largest cases. SDValue SwitchOp = getValue(JTH.SValue); - MVT VT = SwitchOp.getValueType(); + EVT VT = SwitchOp.getValueType(); SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(JTH.First, VT)); @@ -1452,13 +1452,13 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, NextBlock = BBI; SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), - MVT::Other, CopyTo, CMP, + EVT::Other, CopyTo, CMP, DAG.getBasicBlock(JT.Default)); if (JT.MBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond, DAG.getBasicBlock(JT.MBB))); } @@ -1467,7 +1467,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { // Subtract the minimum value SDValue SwitchOp = getValue(B.SValue); - MVT VT = SwitchOp.getValueType(); + EVT VT = SwitchOp.getValueType(); SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(B.First, VT)); @@ -1502,13 +1502,13 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { CurMBB->addSuccessor(MBB); SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), - MVT::Other, CopyTo, RangeCmp, + EVT::Other, CopyTo, RangeCmp, DAG.getBasicBlock(B.Default)); if (MBB == NextBlock) DAG.setRoot(BrRange); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo, DAG.getBasicBlock(MBB))); } @@ -1537,7 +1537,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, CurMBB->addSuccessor(NextMBB); SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), - MVT::Other, getControlRoot(), + EVT::Other, getControlRoot(), AndCmp, DAG.getBasicBlock(B.TargetBB)); // Set NextBlock to be the MBB immediately after the current one, if any. @@ -1550,7 +1550,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, if (NextMBB == NextBlock) DAG.setRoot(BrAnd); else - DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); } @@ -1575,7 +1575,7 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) { // Drop into normal successor. DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), - MVT::Other, getControlRoot(), + EVT::Other, getControlRoot(), DAG.getBasicBlock(Return))); } @@ -1669,8 +1669,8 @@ bool SelectionDAGLowering::handleSmallSwitchRange(CaseRec& CR, static inline bool areJTsAllowed(const TargetLowering &TLI) { return !DisableJumpTables && - (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || - TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); + (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) || + TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other)); } static APInt ComputeRange(const APInt &First, const APInt &Last) { @@ -1911,7 +1911,7 @@ bool SelectionDAGLowering::handleBitTestsSwitchCase(CaseRec& CR, CaseRecVector& WorkList, Value* SV, MachineBasicBlock* Default){ - MVT PTy = TLI.getPointerTy(); + EVT PTy = TLI.getPointerTy(); unsigned IntPtrBits = PTy.getSizeInBits(); Case& FrontCase = *CR.Range.first; @@ -2096,7 +2096,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { CurMBB->addSuccessor(Default); if (Default != NextBlock) DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), - MVT::Other, getControlRoot(), + EVT::Other, getControlRoot(), DAG.getBasicBlock(Default))); return; } @@ -2188,8 +2188,8 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { if (!isa<VectorType>(I.getType()) && Op2.getValueType() != TLI.getShiftAmountTy()) { // If the operand is smaller than the shift count type, promote it. - MVT PTy = TLI.getPointerTy(); - MVT STy = TLI.getShiftAmountTy(); + EVT PTy = TLI.getPointerTy(); + EVT STy = TLI.getShiftAmountTy(); if (STy.bitsGT(Op2.getValueType())) Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), TLI.getShiftAmountTy(), Op2); @@ -2226,7 +2226,7 @@ void SelectionDAGLowering::visitICmp(User &I) { SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Opcode = getICmpCondCode(predicate); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); } @@ -2239,12 +2239,12 @@ void SelectionDAGLowering::visitFCmp(User &I) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); ISD::CondCode Condition = getFCmpCondCode(predicate); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); } void SelectionDAGLowering::visitSelect(User &I) { - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, I.getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); if (NumValues != 0) { @@ -2269,7 +2269,7 @@ void SelectionDAGLowering::visitSelect(User &I) { void SelectionDAGLowering::visitTrunc(User &I) { // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); } @@ -2277,7 +2277,7 @@ void SelectionDAGLowering::visitZExt(User &I) { // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } @@ -2285,14 +2285,14 @@ void SelectionDAGLowering::visitSExt(User &I) { // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). // SExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), DestVT, N, DAG.getIntPtrConstant(0))); } @@ -2300,35 +2300,35 @@ void SelectionDAGLowering::visitFPTrunc(User &I) { void SelectionDAGLowering::visitFPExt(User &I){ // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSIToFP(User &I){ // SIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); } @@ -2336,8 +2336,8 @@ void SelectionDAGLowering::visitPtrToInt(User &I) { // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDValue N = getValue(I.getOperand(0)); - MVT SrcVT = N.getValueType(); - MVT DestVT = TLI.getValueType(I.getType()); + EVT SrcVT = N.getValueType(); + EVT DestVT = TLI.getValueType(I.getType()); SDValue Result; if (DestVT.bitsLT(SrcVT)) Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N); @@ -2351,8 +2351,8 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { // What to do depends on the size of the integer and the size of the pointer. // We can either truncate, zero extend, or no-op, accordingly. SDValue N = getValue(I.getOperand(0)); - MVT SrcVT = N.getValueType(); - MVT DestVT = TLI.getValueType(I.getType()); + EVT SrcVT = N.getValueType(); + EVT DestVT = TLI.getValueType(I.getType()); if (DestVT.bitsLT(SrcVT)) setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); else @@ -2363,7 +2363,7 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { void SelectionDAGLowering::visitBitCast(User &I) { SDValue N = getValue(I.getOperand(0)); - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. @@ -2424,8 +2424,8 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); } - MVT VT = TLI.getValueType(I.getType()); - MVT SrcVT = Src1.getValueType(); + EVT VT = TLI.getValueType(I.getType()); + EVT SrcVT = Src1.getValueType(); unsigned SrcNumElts = SrcVT.getVectorNumElements(); if (SrcNumElts == MaskNumElts) { @@ -2559,8 +2559,8 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { // We can't use either concat vectors or extract subvectors so fall back to // replacing the shuffle with extract and build vector. // to insert and build vector. - MVT EltVT = VT.getVectorElementType(); - MVT PtrVT = TLI.getPointerTy(); + EVT EltVT = VT.getVectorElementType(); + EVT PtrVT = TLI.getPointerTy(); SmallVector<SDValue,8> Ops; for (unsigned i = 0; i != MaskNumElts; ++i) { if (Mask[i] < 0) { @@ -2591,9 +2591,9 @@ void SelectionDAGLowering::visitInsertValue(InsertValueInst &I) { unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, I.idx_begin(), I.idx_end()); - SmallVector<MVT, 4> AggValueVTs; + SmallVector<EVT, 4> AggValueVTs; ComputeValueVTs(TLI, AggTy, AggValueVTs); - SmallVector<MVT, 4> ValValueVTs; + SmallVector<EVT, 4> ValValueVTs; ComputeValueVTs(TLI, ValTy, ValValueVTs); unsigned NumAggValues = AggValueVTs.size(); @@ -2630,7 +2630,7 @@ void SelectionDAGLowering::visitExtractValue(ExtractValueInst &I) { unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy, I.idx_begin(), I.idx_end()); - SmallVector<MVT, 4> ValValueVTs; + SmallVector<EVT, 4> ValValueVTs; ComputeValueVTs(TLI, ValTy, ValValueVTs); unsigned NumValValues = ValValueVTs.size(); @@ -2675,12 +2675,12 @@ void SelectionDAGLowering::visitGetElementPtr(User &I) { uint64_t Offs = TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); SDValue OffsVal; - MVT PTy = TLI.getPointerTy(); + EVT PTy = TLI.getPointerTy(); unsigned PtrBits = PTy.getSizeInBits(); if (PtrBits < 64) { OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getPointerTy(), - DAG.getConstant(Offs, MVT::i64)); + DAG.getConstant(Offs, EVT::i64)); } else OffsVal = DAG.getIntPtrConstant(Offs); N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, @@ -2743,7 +2743,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { - MVT IntPtr = TLI.getPointerTy(); + EVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(AllocSize.getValueType())) AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, AllocSize); @@ -2770,7 +2770,7 @@ void SelectionDAGLowering::visitAlloca(AllocaInst &I) { DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; - SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); + SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other); SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), VTs, Ops, 3); setValue(&I, DSA); @@ -2789,7 +2789,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { bool isVolatile = I.isVolatile(); unsigned Alignment = I.getAlignment(); - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; SmallVector<uint64_t, 4> Offsets; ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); unsigned NumValues = ValueVTs.size(); @@ -2812,7 +2812,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { SmallVector<SDValue, 4> Values(NumValues); SmallVector<SDValue, 4> Chains(NumValues); - MVT PtrVT = Ptr.getValueType(); + EVT PtrVT = Ptr.getValueType(); for (unsigned i = 0; i != NumValues; ++i) { SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, DAG.getNode(ISD::ADD, getCurDebugLoc(), @@ -2826,7 +2826,7 @@ void SelectionDAGLowering::visitLoad(LoadInst &I) { if (!ConstantMemory) { SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), - MVT::Other, + EVT::Other, &Chains[0], NumValues); if (isVolatile) DAG.setRoot(Chain); @@ -2844,7 +2844,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) { Value *SrcV = I.getOperand(0); Value *PtrV = I.getOperand(1); - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; SmallVector<uint64_t, 4> Offsets; ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); unsigned NumValues = ValueVTs.size(); @@ -2859,7 +2859,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) { SDValue Root = getRoot(); SmallVector<SDValue, 4> Chains(NumValues); - MVT PtrVT = Ptr.getValueType(); + EVT PtrVT = Ptr.getValueType(); bool isVolatile = I.isVolatile(); unsigned Alignment = I.getAlignment(); for (unsigned i = 0; i != NumValues; ++i) @@ -2872,7 +2872,7 @@ void SelectionDAGLowering::visitStore(StoreInst &I) { isVolatile, Alignment); DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), - MVT::Other, &Chains[0], NumValues)); + EVT::Other, &Chains[0], NumValues)); } /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC @@ -2909,7 +2909,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, Ops.push_back(Op); } - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, I.getType(), ValueVTs); #ifndef NDEBUG for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { @@ -2918,7 +2918,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, } #endif // NDEBUG if (HasChain) - ValueVTs.push_back(MVT::Other); + ValueVTs.push_back(EVT::Other); SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); @@ -2951,7 +2951,7 @@ void SelectionDAGLowering::visitTargetIntrinsic(CallInst &I, } if (I.getType() != Type::VoidTy) { if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) { - MVT VT = TLI.getValueType(PTy); + EVT VT = TLI.getValueType(PTy); Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result); } setValue(&I, Result); @@ -3033,11 +3033,11 @@ void AddCatchInfo(CallInst &I, MachineModuleInfo *MMI, /// where Op is the hexidecimal representation of floating point value. static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { - SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, - DAG.getConstant(0x007fffff, MVT::i32)); - SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, - DAG.getConstant(0x3f800000, MVT::i32)); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2); + SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op, + DAG.getConstant(0x007fffff, EVT::i32)); + SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1, + DAG.getConstant(0x3f800000, EVT::i32)); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2); } /// GetExponent - Get the exponent: @@ -3048,19 +3048,19 @@ GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, DebugLoc dl) { - SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, - DAG.getConstant(0x7f800000, MVT::i32)); - SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, + SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op, + DAG.getConstant(0x7f800000, EVT::i32)); + SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0, DAG.getConstant(23, TLI.getPointerTy())); - SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, - DAG.getConstant(127, MVT::i32)); - return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); + SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1, + DAG.getConstant(127, EVT::i32)); + return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2); } /// getF32Constant - Get 32-bit floating point constant. static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt) { - return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); + return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32); } /// Inlined utility function to implement binary input atomic intrinsics for @@ -3087,7 +3087,7 @@ SelectionDAGLowering::implVisitAluOverflow(CallInst &I, ISD::NodeType Op) { SDValue Op1 = getValue(I.getOperand(1)); SDValue Op2 = getValue(I.getOperand(2)); - SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); + SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1); SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2); setValue(&I, Result); @@ -3101,7 +3101,7 @@ SelectionDAGLowering::visitExp(CallInst &I) { SDValue result; DebugLoc dl = getCurDebugLoc(); - if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && + if (getValue(I.getOperand(1)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); @@ -3110,16 +3110,16 @@ SelectionDAGLowering::visitExp(CallInst &I) { // // #define LOG2OFe 1.4426950f // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op, getF32Constant(DAG, 0x3fb8aa3b)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0); // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX, DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { @@ -3130,20 +3130,20 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.735607626f + 0.252464424f * x) * x; // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5); + SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5); // Add the exponent into the result in integer domain. - SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, + SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6); + result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3153,23 +3153,23 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // 0.000107046256 error, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7); + SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7); // Add the exponent into the result in integer domain. - SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, + SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8); + result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3182,33 +3182,33 @@ SelectionDAGLowering::visitExp(CallInst &I) { // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12, getF32Constant(DAG, 0x3f800000)); SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::i32, t13); + EVT::i32, t13); // Add the exponent into the result in integer domain. - SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, + SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32, TwoToFracPartOfX, IntegerPartOfX); - result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14); + result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14); } } else { // No special expansion. @@ -3227,14 +3227,14 @@ SelectionDAGLowering::visitLog(CallInst &I) { SDValue result; DebugLoc dl = getCurDebugLoc(); - if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && + if (getValue(I.getOperand(1)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op); // Scale the exponent by log(2) [0.69314718f]. SDValue Exp = GetExponent(DAG, Op1, TLI, dl); - SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, + SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp, getF32Constant(DAG, 0x3f317218)); // Get the significand and build it into a floating-point number with @@ -3249,16 +3249,16 @@ SelectionDAGLowering::visitLog(CallInst &I) { // (1.4034025f - 0.23903021f * x) * x; // // error 0.0034276066, which is better than 8 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbe74c456)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3fb3a2b1)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f949a29)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, LogOfMantissa); + EVT::f32, LogOfExponent, LogOfMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3269,22 +3269,22 @@ SelectionDAGLowering::visitLog(CallInst &I) { // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; // // error 0.000061011436, which is 14 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbd67b6d6)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3ee4f4b8)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3fbc278b)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x40348e95)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6, getF32Constant(DAG, 0x3fdef31a)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, LogOfMantissa); + EVT::f32, LogOfExponent, LogOfMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3297,28 +3297,28 @@ SelectionDAGLowering::visitLog(CallInst &I) { // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; // // error 0.0000023660568, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbc91e5ac)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3e4350aa)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f60d3e3)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x4011cdf0)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6, getF32Constant(DAG, 0x406cfd1c)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8, getF32Constant(DAG, 0x408797cb)); - SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); - SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X); + SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10, getF32Constant(DAG, 0x4006dcab)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, LogOfMantissa); + EVT::f32, LogOfExponent, LogOfMantissa); } } else { // No special expansion. @@ -3337,10 +3337,10 @@ SelectionDAGLowering::visitLog2(CallInst &I) { SDValue result; DebugLoc dl = getCurDebugLoc(); - if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && + if (getValue(I.getOperand(1)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op); // Get the exponent. SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); @@ -3357,16 +3357,16 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; // // error 0.0049451742, which is more than 7 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbeb08fe0)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x40019463)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3fd6633d)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log2ofMantissa); + EVT::f32, LogOfExponent, Log2ofMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3377,22 +3377,22 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; // // error 0.0000876136000, which is better than 13 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbda7262e)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3f25280b)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x4007b923)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x40823e2f)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6, getF32Constant(DAG, 0x4020d29c)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log2ofMantissa); + EVT::f32, LogOfExponent, Log2ofMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3406,28 +3406,28 @@ SelectionDAGLowering::visitLog2(CallInst &I) { // 0.25691327e-1f * x) * x) * x) * x) * x) * x; // // error 0.0000018516, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbcd2769e)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3e8ce0b9)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3fa22ae7)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x40525723)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6, getF32Constant(DAG, 0x40aaf200)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8, getF32Constant(DAG, 0x40c39dad)); - SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); - SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X); + SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10, getF32Constant(DAG, 0x4042902c)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log2ofMantissa); + EVT::f32, LogOfExponent, Log2ofMantissa); } } else { // No special expansion. @@ -3446,14 +3446,14 @@ SelectionDAGLowering::visitLog10(CallInst &I) { SDValue result; DebugLoc dl = getCurDebugLoc(); - if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && + if (getValue(I.getOperand(1)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); + SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op); // Scale the exponent by log10(2) [0.30102999f]. SDValue Exp = GetExponent(DAG, Op1, TLI, dl); - SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, + SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp, getF32Constant(DAG, 0x3e9a209a)); // Get the significand and build it into a floating-point number with @@ -3468,16 +3468,16 @@ SelectionDAGLowering::visitLog10(CallInst &I) { // (0.60948995f - 0.10380950f * x) * x; // // error 0.0014886165, which is 6 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0xbdd49a13)); - SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0, getF32Constant(DAG, 0x3f1c0789)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f011300)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log10ofMantissa); + EVT::f32, LogOfExponent, Log10ofMantissa); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3487,19 +3487,19 @@ SelectionDAGLowering::visitLog10(CallInst &I) { // (-0.31664806f + 0.47637168e-1f * x) * x) * x; // // error 0.00019228036, which is better than 12 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3d431f31)); - SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, getF32Constant(DAG, 0x3ea21fb2)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f6ae232)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f25f7c3)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log10ofMantissa); + EVT::f32, LogOfExponent, Log10ofMantissa); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3511,25 +3511,25 @@ SelectionDAGLowering::visitLog10(CallInst &I) { // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; // // error 0.0000037995730, which is better than 18 bits - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3c5d51ce)); - SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, + SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, getF32Constant(DAG, 0x3e00685a)); - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X); + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3efb6798)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f88d192)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3fc4316c)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8, getF32Constant(DAG, 0x3f57ce70)); result = DAG.getNode(ISD::FADD, dl, - MVT::f32, LogOfExponent, Log10ofMantissa); + EVT::f32, LogOfExponent, Log10ofMantissa); } } else { // No special expansion. @@ -3548,18 +3548,18 @@ SelectionDAGLowering::visitExp2(CallInst &I) { SDValue result; DebugLoc dl = getCurDebugLoc(); - if (getValue(I.getOperand(1)).getValueType() == MVT::f32 && + if (getValue(I.getOperand(1)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { SDValue Op = getValue(I.getOperand(1)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op); // FractionalPartOfX = x - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX, DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { @@ -3570,19 +3570,19 @@ SelectionDAGLowering::visitExp2(CallInst &I) { // (0.735607626f + 0.252464424f * x) * x; // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); + SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3592,22 +3592,22 @@ SelectionDAGLowering::visitExp2(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // error 0.000107046256, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); + SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3619,31 +3619,31 @@ SelectionDAGLowering::visitExp2(CallInst &I) { // (0.961591928e-2f + // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12, getF32Constant(DAG, 0x3f800000)); - SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); + SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } } else { // No special expansion. @@ -3664,8 +3664,8 @@ SelectionDAGLowering::visitPow(CallInst &I) { DebugLoc dl = getCurDebugLoc(); bool IsExp10 = false; - if (getValue(Val).getValueType() == MVT::f32 && - getValue(I.getOperand(2)).getValueType() == MVT::f32 && + if (getValue(Val).getValueType() == EVT::f32 && + getValue(I.getOperand(2)).getValueType() == EVT::f32 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { @@ -3683,16 +3683,16 @@ SelectionDAGLowering::visitPow(CallInst &I) { // // #define LOG2OF10 3.3219281f // IntegerPartOfX = (int32_t)(x * LOG2OF10); - SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, + SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op, getF32Constant(DAG, 0x40549a78)); - SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); + SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0); // FractionalPartOfX = x - (float)IntegerPartOfX; - SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); - SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); + SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX); + SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1); // IntegerPartOfX <<= 23; - IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, + IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX, DAG.getConstant(23, TLI.getPointerTy())); if (LimitFloatPrecision <= 6) { @@ -3703,19 +3703,19 @@ SelectionDAGLowering::visitPow(CallInst &I) { // (0.735607626f + 0.252464424f * x) * x; // // error 0.0144103317, which is 6 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3e814304)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3f3c50c8)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f7f5e7e)); - SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5); + SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { // For floating-point precision of 12: // @@ -3725,22 +3725,22 @@ SelectionDAGLowering::visitPow(CallInst &I) { // (0.224338339f + 0.792043434e-1f * x) * x) * x; // // error 0.000107046256, which is 13 to 14 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3da235e3)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3e65b8f3)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3f324b07)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3f7ff8fd)); - SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7); + SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 // For floating-point precision of 18: // @@ -3752,31 +3752,31 @@ SelectionDAGLowering::visitPow(CallInst &I) { // (0.961591928e-2f + // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; // error 2.47208000*10^(-7), which is better than 18 bits - SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, + SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X, getF32Constant(DAG, 0x3924b03e)); - SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, + SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2, getF32Constant(DAG, 0x3ab24b87)); - SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); - SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, + SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X); + SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4, getF32Constant(DAG, 0x3c1d8c17)); - SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); - SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, + SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X); + SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6, getF32Constant(DAG, 0x3d634a1d)); - SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); - SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, + SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X); + SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8, getF32Constant(DAG, 0x3e75fe14)); - SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); - SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, + SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X); + SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10, getF32Constant(DAG, 0x3f317234)); - SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); - SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, + SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X); + SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12, getF32Constant(DAG, 0x3f800000)); - SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13); + SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13); SDValue TwoToFractionalPartOfX = - DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); + DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX); result = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f32, TwoToFractionalPartOfX); + EVT::f32, TwoToFractionalPartOfX); } } else { // No special expansion. @@ -3973,14 +3973,14 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; Value *Variable = DI.getVariable(); - DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(), + DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(), getValue(DI.getAddress()), getValue(Variable))); return 0; } case Intrinsic::eh_exception: { // Insert the EXCEPTIONADDR instruction. assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!"); - SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); + SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other); SDValue Ops[1]; Ops[0] = DAG.getRoot(); SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); @@ -3992,8 +3992,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::eh_selector_i32: case Intrinsic::eh_selector_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? - MVT::i32 : MVT::i64); + EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ? + EVT::i32 : EVT::i64); if (MMI) { if (CurMBB->isLandingPad()) @@ -4008,7 +4008,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { } // Insert the EHSELECTION instruction. - SDVTList VTs = DAG.getVTList(VT, MVT::Other); + SDVTList VTs = DAG.getVTList(VT, EVT::Other); SDValue Ops[2]; Ops[0] = getValue(I.getOperand(1)); Ops[1] = getRoot(); @@ -4025,8 +4025,8 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::eh_typeid_for_i32: case Intrinsic::eh_typeid_for_i64: { MachineModuleInfo *MMI = DAG.getMachineModuleInfo(); - MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? - MVT::i32 : MVT::i64); + EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ? + EVT::i32 : EVT::i64); if (MMI) { // Find the type id for the given typeinfo. @@ -4047,7 +4047,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) { MMI->setCallsEHReturn(true); DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, - MVT::Other, + EVT::Other, getControlRoot(), getValue(I.getOperand(1)), getValue(I.getOperand(2)))); @@ -4064,7 +4064,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::eh_dwarf_cfa: { - MVT VT = getValue(I.getOperand(1)).getValueType(); + EVT VT = getValue(I.getOperand(1)).getValueType(); SDValue CfaArg; if (VT.bitsGT(TLI.getPointerTy())) CfaArg = DAG.getNode(ISD::TRUNCATE, dl, @@ -4109,7 +4109,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::convertus: Code = ISD::CVT_US; break; case Intrinsic::convertuu: Code = ISD::CVT_UU; break; } - MVT DestVT = TLI.getValueType(I.getType()); + EVT DestVT = TLI.getValueType(I.getType()); Value* Op1 = I.getOperand(1); setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), DAG.getValueType(DestVT), @@ -4161,13 +4161,13 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::pcmarker: { SDValue Tmp = getValue(I.getOperand(1)); - DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); + DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp)); return 0; } case Intrinsic::readcyclecounter: { SDValue Op = getRoot(); SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl, - DAG.getVTList(MVT::i64, MVT::Other), + DAG.getVTList(EVT::i64, EVT::Other), &Op, 1); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); @@ -4180,21 +4180,21 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::cttz: { SDValue Arg = getValue(I.getOperand(1)); - MVT Ty = Arg.getValueType(); + EVT Ty = Arg.getValueType(); SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctlz: { SDValue Arg = getValue(I.getOperand(1)); - MVT Ty = Arg.getValueType(); + EVT Ty = Arg.getValueType(); SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg); setValue(&I, result); return 0; } case Intrinsic::ctpop: { SDValue Arg = getValue(I.getOperand(1)); - MVT Ty = Arg.getValueType(); + EVT Ty = Arg.getValueType(); SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg); setValue(&I, result); return 0; @@ -4202,21 +4202,21 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { case Intrinsic::stacksave: { SDValue Op = getRoot(); SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl, - DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); + DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1); setValue(&I, Tmp); DAG.setRoot(Tmp.getValue(1)); return 0; } case Intrinsic::stackrestore: { SDValue Tmp = getValue(I.getOperand(1)); - DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp)); + DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp)); return 0; } case Intrinsic::stackprotector: { // Emit code into the DAG to store the stack guard onto the stack. MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MVT PtrTy = TLI.getPointerTy(); + EVT PtrTy = TLI.getPointerTy(); SDValue Src = getValue(I.getOperand(1)); // The guard's value. AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2)); @@ -4250,7 +4250,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Ops[5] = DAG.getSrcValue(F); SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl, - DAG.getVTList(TLI.getPointerTy(), MVT::Other), + DAG.getVTList(TLI.getPointerTy(), EVT::Other), Ops, 6); setValue(&I, Tmp); @@ -4274,12 +4274,12 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { return 0; case Intrinsic::flt_rounds: { - setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); + setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32)); return 0; } case Intrinsic::trap: { - DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); + DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot())); return 0; } @@ -4302,7 +4302,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { Ops[1] = getValue(I.getOperand(1)); Ops[2] = getValue(I.getOperand(2)); Ops[3] = getValue(I.getOperand(3)); - DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4)); + DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4)); return 0; } @@ -4312,7 +4312,7 @@ SelectionDAGLowering::visitIntrinsicCall(CallInst &I, unsigned Intrinsic) { for (int x = 1; x < 6; ++x) Ops[x] = getValue(I.getOperand(x)); - DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6)); + DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6)); return 0; } case Intrinsic::atomic_cmp_swap: { @@ -4599,9 +4599,9 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SmallVector<SDValue, 8> Parts; for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { // Copy the legal parts from the registers. - MVT ValueVT = ValueVTs[Value]; + EVT ValueVT = ValueVTs[Value]; unsigned NumRegs = TLI->getNumRegisters(ValueVT); - MVT RegisterVT = RegVTs[Value]; + EVT RegisterVT = RegVTs[Value]; Parts.resize(NumRegs); for (unsigned i = 0; i != NumRegs; ++i) { @@ -4630,25 +4630,25 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, // FIXME: We capture more information than the dag can represent. For // now, just use the tightest assertzext/assertsext possible. bool isSExt = true; - MVT FromVT(MVT::Other); + EVT FromVT(EVT::Other); if (NumSignBits == RegSize) - isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 + isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1 else if (NumZeroBits >= RegSize-1) - isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 + isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1 else if (NumSignBits > RegSize-8) - isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 + isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8 else if (NumZeroBits >= RegSize-8) - isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 + isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8 else if (NumSignBits > RegSize-16) - isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 + isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16 else if (NumZeroBits >= RegSize-16) - isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 + isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16 else if (NumSignBits > RegSize-32) - isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 + isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32 else if (NumZeroBits >= RegSize-32) - isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 + isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32 - if (FromVT != MVT::Other) { + if (FromVT != EVT::Other) { P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, RegisterVT, P, DAG.getValueType(FromVT)); @@ -4680,9 +4680,9 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, unsigned NumRegs = Regs.size(); SmallVector<SDValue, 8> Parts(NumRegs); for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { - MVT ValueVT = ValueVTs[Value]; + EVT ValueVT = ValueVTs[Value]; unsigned NumParts = TLI->getNumRegisters(ValueVT); - MVT RegisterVT = RegVTs[Value]; + EVT RegisterVT = RegVTs[Value]; getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), &Parts[Part], NumParts, RegisterVT); @@ -4715,7 +4715,7 @@ void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, // = op c3, ..., f2 Chain = Chains[NumRegs-1]; else - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs); } /// AddInlineAsmOperands - Add this value to the specified inlineasm node @@ -4725,7 +4725,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching,unsigned MatchingIdx, SelectionDAG &DAG, std::vector<SDValue> &Ops) const { - MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); + EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy(); assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!"); unsigned Flag = Code | (Regs.size() << 3); if (HasMatching) @@ -4733,7 +4733,7 @@ void RegsForValue::AddInlineAsmOperands(unsigned Code, Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy)); for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]); - MVT RegisterVT = RegVTs[Value]; + EVT RegisterVT = RegVTs[Value]; for (unsigned i = 0; i != NumRegs; ++i) { assert(Reg < Regs.size() && "Mismatch in # registers expected"); Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); @@ -4748,11 +4748,11 @@ static const TargetRegisterClass * isAllocatableRegister(unsigned Reg, MachineFunction &MF, const TargetLowering &TLI, const TargetRegisterInfo *TRI) { - MVT FoundVT = MVT::Other; + EVT FoundVT = EVT::Other; const TargetRegisterClass *FoundRC = 0; for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), E = TRI->regclass_end(); RCI != E; ++RCI) { - MVT ThisVT = MVT::Other; + EVT ThisVT = EVT::Other; const TargetRegisterClass *RC = *RCI; // If none of the the value types for this register class are valid, we @@ -4763,14 +4763,14 @@ isAllocatableRegister(unsigned Reg, MachineFunction &MF, // If we have already found this register in a different register class, // choose the one with the largest VT specified. For example, on // PowerPC, we favor f64 register classes over f32. - if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { + if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) { ThisVT = *I; break; } } } - if (ThisVT == MVT::Other) continue; + if (ThisVT == EVT::Other) continue; // NOTE: This isn't ideal. In particular, this might allocate the // frame pointer in functions that need it (due to them not being taken @@ -4825,12 +4825,12 @@ public: } } - /// getCallOperandValMVT - Return the MVT of the Value* that this operand + /// getCallOperandValEVT - Return the EVT of the Value* that this operand /// corresponds to. If there is no Value* for this operand, it returns - /// MVT::Other. - MVT getCallOperandValMVT(const TargetLowering &TLI, + /// EVT::Other. + EVT getCallOperandValEVT(const TargetLowering &TLI, const TargetData *TD) const { - if (CallOperandVal == 0) return MVT::Other; + if (CallOperandVal == 0) return EVT::Other; if (isa<BasicBlock>(CallOperandVal)) return TLI.getPointerTy(); @@ -4923,16 +4923,16 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, OpInfo.ConstraintVT); unsigned NumRegs = 1; - if (OpInfo.ConstraintVT != MVT::Other) { + if (OpInfo.ConstraintVT != EVT::Other) { // If this is a FP input in an integer register (or visa versa) insert a bit // cast of the input value. More generally, handle any case where the input // value disagrees with the register class we plan to stick this in. if (OpInfo.Type == InlineAsm::isInput && PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { - // Try to convert to the first MVT that the reg class contains. If the + // Try to convert to the first EVT that the reg class contains. If the // types are identical size, use a bitcast to convert (e.g. two differing // vector types). - MVT RegVT = *PhysReg.second->vt_begin(); + EVT RegVT = *PhysReg.second->vt_begin(); if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), RegVT, OpInfo.CallOperand); @@ -4942,7 +4942,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // bitcast to the corresponding integer type. This turns an f64 value // into i64, which can be passed with two i32 values on a 32-bit // machine. - RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); + RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits()); OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), RegVT, OpInfo.CallOperand); OpInfo.ConstraintVT = RegVT; @@ -4952,14 +4952,14 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT); } - MVT RegVT; - MVT ValueVT = OpInfo.ConstraintVT; + EVT RegVT; + EVT ValueVT = OpInfo.ConstraintVT; // If this is a constraint for a specific physical register, like {r17}, // assign it now. if (unsigned AssignedReg = PhysReg.first) { const TargetRegisterClass *RC = PhysReg.second; - if (OpInfo.ConstraintVT == MVT::Other) + if (OpInfo.ConstraintVT == EVT::Other) ValueVT = *RC->vt_begin(); // Get the actual register value type. This is important, because the user @@ -4993,7 +4993,7 @@ GetRegistersForValue(SDISelAsmOperandInfo &OpInfo, // for this reference. if (const TargetRegisterClass *RC = PhysReg.second) { RegVT = *RC->vt_begin(); - if (OpInfo.ConstraintVT == MVT::Other) + if (OpInfo.ConstraintVT == EVT::Other) ValueVT = RegVT; // Create the appropriate number of virtual registers. @@ -5107,7 +5107,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i])); SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); - MVT OpVT = MVT::Other; + EVT OpVT = EVT::Other; // Compute the value type for each operand. switch (OpInfo.Type) { @@ -5149,7 +5149,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); } - OpVT = OpInfo.getCallOperandValMVT(TLI, TD); + OpVT = OpInfo.getCallOperandValEVT(TLI, TD); } OpInfo.ConstraintVT = OpVT; @@ -5243,7 +5243,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { std::vector<SDValue> AsmNodeOperands; AsmNodeOperands.push_back(SDValue()); // reserve space for input chain AsmNodeOperands.push_back( - DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other)); + DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other)); // Loop over all of the inputs, copying the operand values into the @@ -5336,7 +5336,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { RegsForValue MatchedRegs; MatchedRegs.TLI = &TLI; MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); - MVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); + EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); MatchedRegs.RegVTs.push_back(RegVT); MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); @@ -5431,7 +5431,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { if (Flag.getNode()) AsmNodeOperands.push_back(Flag); Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), - DAG.getVTList(MVT::Other, MVT::Flag), + DAG.getVTList(EVT::Other, EVT::Flag), &AsmNodeOperands[0], AsmNodeOperands.size()); Flag = Chain.getValue(1); @@ -5443,7 +5443,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { // FIXME: Why don't we do this for inline asms with MRVs? if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { - MVT ResultType = TLI.getValueType(CS.getType()); + EVT ResultType = TLI.getValueType(CS.getType()); // If any of the results of the inline asm is a vector, it may have the // wrong width/num elts. This can happen for register classes that can @@ -5492,7 +5492,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) { getValue(StoresToEmit[i].second), StoresToEmit[i].second, 0)); if (!OutChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other, &OutChains[0], OutChains.size()); DAG.setRoot(Chain); } @@ -5509,13 +5509,13 @@ void SelectionDAGLowering::visitMalloc(MallocInst &I) { uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType()); if (ElementSize != 1) { // Src is always 32-bits, make sure the constant fits. - assert(Src.getValueType() == MVT::i32); + assert(Src.getValueType() == EVT::i32); ElementSize = (uint32_t)ElementSize; Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(), Src, DAG.getConstant(ElementSize, Src.getValueType())); } - MVT IntPtr = TLI.getPointerTy(); + EVT IntPtr = TLI.getPointerTy(); if (IntPtr.bitsLT(Src.getValueType())) Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src); @@ -5548,7 +5548,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { Entry.Node = getValue(I.getOperand(0)); Entry.Ty = TLI.getTargetData()->getIntPtrType(); Args.push_back(Entry); - MVT IntPtr = TLI.getPointerTy(); + EVT IntPtr = TLI.getPointerTy(); bool isTailCall = PerformTailCallOpt && isInTailCallPosition(&I, Attribute::None, TLI); std::pair<SDValue,SDValue> Result = @@ -5563,7 +5563,7 @@ void SelectionDAGLowering::visitFree(FreeInst &I) { void SelectionDAGLowering::visitVAStart(CallInst &I) { DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), - MVT::Other, getRoot(), + EVT::Other, getRoot(), getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); } @@ -5578,14 +5578,14 @@ void SelectionDAGLowering::visitVAArg(VAArgInst &I) { void SelectionDAGLowering::visitVAEnd(CallInst &I) { DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), - MVT::Other, getRoot(), + EVT::Other, getRoot(), getValue(I.getOperand(1)), DAG.getSrcValue(I.getOperand(1)))); } void SelectionDAGLowering::visitVACopy(CallInst &I) { DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), - MVT::Other, getRoot(), + EVT::Other, getRoot(), getValue(I.getOperand(1)), getValue(I.getOperand(2)), DAG.getSrcValue(I.getOperand(1)), @@ -5611,12 +5611,12 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, // Handle all of the outgoing arguments. SmallVector<ISD::OutputArg, 32> Outs; for (unsigned i = 0, e = Args.size(); i != e; ++i) { - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(*this, Args[i].Ty, ValueVTs); for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; ++Value) { - MVT VT = ValueVTs[Value]; - const Type *ArgTy = VT.getTypeForMVT(); + EVT VT = ValueVTs[Value]; + const Type *ArgTy = VT.getTypeForEVT(); SDValue Op = SDValue(Args[i].Node.getNode(), Args[i].Node.getResNo() + Value); ISD::ArgFlagsTy Flags; @@ -5648,7 +5648,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT PartVT = getRegisterType(VT); + EVT PartVT = getRegisterType(VT); unsigned NumParts = getNumRegisters(VT); SmallVector<SDValue, 4> Parts(NumParts); ISD::NodeType ExtendKind = ISD::ANY_EXTEND; @@ -5675,11 +5675,11 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, // Handle the incoming return values from the call. SmallVector<ISD::InputArg, 32> Ins; - SmallVector<MVT, 4> RetTys; + SmallVector<EVT, 4> RetTys; ComputeValueVTs(*this, RetTy, RetTys); for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT VT = RetTys[I]; - MVT RegisterVT = getRegisterType(VT); + EVT VT = RetTys[I]; + EVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) { ISD::InputArg MyFlags; @@ -5706,7 +5706,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, Outs, Ins, dl, DAG, InVals); // Verify that the target's LowerCall behaved as expected. - assert(Chain.getNode() && Chain.getValueType() == MVT::Other && + assert(Chain.getNode() && Chain.getValueType() == EVT::Other && "LowerCall didn't return a valid chain!"); assert((!isTailCall || InVals.empty()) && "LowerCall emitted a return value for a tail call!"); @@ -5738,8 +5738,8 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, SmallVector<SDValue, 4> ReturnValues; unsigned CurReg = 0; for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { - MVT VT = RetTys[I]; - MVT RegisterVT = getRegisterType(VT); + EVT VT = RetTys[I]; + EVT RegisterVT = getRegisterType(VT); unsigned NumRegs = getNumRegisters(VT); SDValue ReturnValue = @@ -5805,13 +5805,13 @@ LowerArguments(BasicBlock *LLVMBB) { unsigned Idx = 1; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++Idx) { - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, I->getType(), ValueVTs); bool isArgValueUsed = !I->use_empty(); for (unsigned Value = 0, NumValues = ValueVTs.size(); Value != NumValues; ++Value) { - MVT VT = ValueVTs[Value]; - const Type *ArgTy = VT.getTypeForMVT(); + EVT VT = ValueVTs[Value]; + const Type *ArgTy = VT.getTypeForEVT(); ISD::ArgFlagsTy Flags; unsigned OriginalAlignment = TD->getABITypeAlignment(ArgTy); @@ -5841,7 +5841,7 @@ LowerArguments(BasicBlock *LLVMBB) { Flags.setNest(); Flags.setOrigAlign(OriginalAlignment); - MVT RegisterVT = TLI.getRegisterType(VT); + EVT RegisterVT = TLI.getRegisterType(VT); unsigned NumRegs = TLI.getNumRegisters(VT); for (unsigned i = 0; i != NumRegs; ++i) { ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); @@ -5862,7 +5862,7 @@ LowerArguments(BasicBlock *LLVMBB) { dl, DAG, InVals); // Verify that the target's LowerFormalArguments behaved as expected. - assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && + assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other && "LowerFormalArguments didn't return a valid chain!"); assert(InVals.size() == Ins.size() && "LowerFormalArguments didn't emit the correct number of values!"); @@ -5882,12 +5882,12 @@ LowerArguments(BasicBlock *LLVMBB) { for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I, ++Idx) { SmallVector<SDValue, 4> ArgValues; - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, I->getType(), ValueVTs); unsigned NumValues = ValueVTs.size(); for (unsigned Value = 0; Value != NumValues; ++Value) { - MVT VT = ValueVTs[Value]; - MVT PartVT = TLI.getRegisterType(VT); + EVT VT = ValueVTs[Value]; + EVT PartVT = TLI.getRegisterType(VT); unsigned NumParts = TLI.getNumRegisters(VT); if (!I->use_empty()) { @@ -5975,10 +5975,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB) { // Remember that this register needs to added to the machine PHI node as // the input for this MBB. - SmallVector<MVT, 4> ValueVTs; + SmallVector<EVT, 4> ValueVTs; ComputeValueVTs(TLI, PN->getType(), ValueVTs); for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { - MVT VT = ValueVTs[vti]; + EVT VT = ValueVTs[vti]; unsigned NumRegisters = TLI.getNumRegisters(VT); for (unsigned i = 0, e = NumRegisters; i != e; ++i) SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); @@ -6029,10 +6029,10 @@ SelectionDAGISel::HandlePHINodesInSuccessorBlocksFast(BasicBlock *LLVMBB, // own moves. Second, this check is necessary becuase FastISel doesn't // use CreateRegForValue to create registers, so it always creates // exactly one register for each non-void instruction. - MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); - if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { - // Promote MVT::i1. - if (VT == MVT::i1) + EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true); + if (VT == EVT::Other || !TLI.isTypeLegal(VT)) { + // Promote EVT::i1. + if (VT == EVT::i1) VT = TLI.getTypeToTransformTo(VT); else { SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate); diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h index 379ced966f..9a079d62d5 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h @@ -117,7 +117,7 @@ public: SmallSet<Instruction*, 8> CatchInfoFound; #endif - unsigned MakeReg(MVT VT); + unsigned MakeReg(EVT VT); /// isExportedInst - Return true if the specified value is an instruction /// exported from its block. diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index b02fbea30d..97bb3b3ef9 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -283,7 +283,7 @@ SelectionDAGISel::~SelectionDAGISel() { delete FuncInfo; } -unsigned SelectionDAGISel::MakeReg(MVT VT) { +unsigned SelectionDAGISel::MakeReg(EVT VT) { return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); } @@ -421,7 +421,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() { // Otherwise, add all chain operands to the worklist. for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) - if (N->getOperand(i).getValueType() == MVT::Other) + if (N->getOperand(i).getValueType() == EVT::Other) Worklist.push_back(N->getOperand(i).getNode()); // If this is a CopyToReg with a vreg dest, process it. @@ -434,7 +434,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() { // Ignore non-scalar or non-integer values. SDValue Src = N->getOperand(2); - MVT SrcVT = Src.getValueType(); + EVT SrcVT = Src.getValueType(); if (!SrcVT.isInteger() || SrcVT.isVector()) continue; @@ -1098,7 +1098,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { Ops.push_back(InOps[1]); // input asm string. unsigned i = 2, e = InOps.size(); - if (InOps[e-1].getValueType() == MVT::Flag) + if (InOps[e-1].getValueType() == EVT::Flag) --e; // Don't process a flag operand if it is here. while (i != e) { @@ -1119,7 +1119,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { } // Add this to the output node. - MVT IntPtrTy = TLI.getPointerTy(); + EVT IntPtrTy = TLI.getPointerTy(); Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3), IntPtrTy)); Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); @@ -1132,7 +1132,7 @@ SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { Ops.push_back(InOps.back()); } -/// findFlagUse - Return use of MVT::Flag value produced by the specified +/// findFlagUse - Return use of EVT::Flag value produced by the specified /// SDNode. /// static SDNode *findFlagUse(SDNode *N) { @@ -1235,8 +1235,8 @@ bool SelectionDAGISel::IsLegalAndProfitableToFold(SDNode *N, SDNode *U, // Fold. But since Fold and FU are flagged together, this will create // a cycle in the scheduling graph. - MVT VT = Root->getValueType(Root->getNumValues()-1); - while (VT == MVT::Flag) { + EVT VT = Root->getValueType(Root->getNumValues()-1); + while (VT == EVT::Flag) { SDNode *FU = findFlagUse(Root); if (FU == NULL) break; diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp index 386d732348..ef45110361 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp @@ -44,7 +44,7 @@ namespace llvm { } static std::string getEdgeDestLabel(const void *Node, unsigned i) { - return ((const SDNode *) Node)->getValueType(i).getMVTString(); + return ((const SDNode *) Node)->getValueType(i).getEVTString(); } /// edgeTargetsEdgeSource - This method returns true if this outgoing edge @@ -84,10 +84,10 @@ namespace llvm { template<typename EdgeIter> static std::string getEdgeAttributes(const void *Node, EdgeIter EI) { SDValue Op = EI.getNode()->getOperand(EI.getOperand()); - MVT VT = Op.getValueType(); - if (VT == MVT::Flag) + EVT VT = Op.getValueType(); + if (VT == EVT::Flag) return "color=red,style=bold"; - else if (VT == MVT::Other) + else if (VT == EVT::Other) return "color=blue,style=dashed"; return ""; } diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 7d7afb2b4c..c7ddf0adb9 100644 --- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -249,9 +249,9 @@ static void InitLibcallNames(const char **Names) { /// getFPEXT - Return the FPEXT_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { - if (OpVT == MVT::f32) { - if (RetVT == MVT::f64) +RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) { + if (OpVT == EVT::f32) { + if (RetVT == EVT::f64) return FPEXT_F32_F64; } return UNKNOWN_LIBCALL; @@ -259,18 +259,18 @@ RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) { /// getFPROUND - Return the FPROUND_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { - if (RetVT == MVT::f32) { - if (OpVT == MVT::f64) +RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) { + if (RetVT == EVT::f32) { + if (OpVT == EVT::f64) return FPROUND_F64_F32; - if (OpVT == MVT::f80) + if (OpVT == EVT::f80) return FPROUND_F80_F32; - if (OpVT == MVT::ppcf128) + if (OpVT == EVT::ppcf128) return FPROUND_PPCF128_F32; - } else if (RetVT == MVT::f64) { - if (OpVT == MVT::f80) + } else if (RetVT == EVT::f64) { + if (OpVT == EVT::f80) return FPROUND_F80_F64; - if (OpVT == MVT::ppcf128) + if (OpVT == EVT::ppcf128) return FPROUND_PPCF128_F64; } return UNKNOWN_LIBCALL; @@ -278,38 +278,38 @@ RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) { /// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { - if (OpVT == MVT::f32) { - if (RetVT == MVT::i8) +RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) { + if (OpVT == EVT::f32) { + if (RetVT == EVT::i8) return FPTOSINT_F32_I8; - if (RetVT == MVT::i16) + if (RetVT == EVT::i16) return FPTOSINT_F32_I16; - if (RetVT == MVT::i32) + if (RetVT == EVT::i32) return FPTOSINT_F32_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOSINT_F32_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOSINT_F32_I128; - } else if (OpVT == MVT::f64) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::f64) { + if (RetVT == EVT::i32) return FPTOSINT_F64_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOSINT_F64_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOSINT_F64_I128; - } else if (OpVT == MVT::f80) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::f80) { + if (RetVT == EVT::i32) return FPTOSINT_F80_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOSINT_F80_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOSINT_F80_I128; - } else if (OpVT == MVT::ppcf128) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::ppcf128) { + if (RetVT == EVT::i32) return FPTOSINT_PPCF128_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOSINT_PPCF128_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOSINT_PPCF128_I128; } return UNKNOWN_LIBCALL; @@ -317,38 +317,38 @@ RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) { /// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { - if (OpVT == MVT::f32) { - if (RetVT == MVT::i8) +RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) { + if (OpVT == EVT::f32) { + if (RetVT == EVT::i8) return FPTOUINT_F32_I8; - if (RetVT == MVT::i16) + if (RetVT == EVT::i16) return FPTOUINT_F32_I16; - if (RetVT == MVT::i32) + if (RetVT == EVT::i32) return FPTOUINT_F32_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOUINT_F32_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOUINT_F32_I128; - } else if (OpVT == MVT::f64) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::f64) { + if (RetVT == EVT::i32) return FPTOUINT_F64_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOUINT_F64_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOUINT_F64_I128; - } else if (OpVT == MVT::f80) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::f80) { + if (RetVT == EVT::i32) return FPTOUINT_F80_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOUINT_F80_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOUINT_F80_I128; - } else if (OpVT == MVT::ppcf128) { - if (RetVT == MVT::i32) + } else if (OpVT == EVT::ppcf128) { + if (RetVT == EVT::i32) return FPTOUINT_PPCF128_I32; - if (RetVT == MVT::i64) + if (RetVT == EVT::i64) return FPTOUINT_PPCF128_I64; - if (RetVT == MVT::i128) + if (RetVT == EVT::i128) return FPTOUINT_PPCF128_I128; } return UNKNOWN_LIBCALL; @@ -356,33 +356,33 @@ RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) { /// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { - if (OpVT == MVT::i32) { - if (RetVT == MVT::f32) +RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) { + if (OpVT == EVT::i32) { + if (RetVT == EVT::f32) return SINTTOFP_I32_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return SINTTOFP_I32_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return SINTTOFP_I32_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return SINTTOFP_I32_PPCF128; - } else if (OpVT == MVT::i64) { - if (RetVT == MVT::f32) + } else if (OpVT == EVT::i64) { + if (RetVT == EVT::f32) return SINTTOFP_I64_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return SINTTOFP_I64_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return SINTTOFP_I64_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return SINTTOFP_I64_PPCF128; - } else if (OpVT == MVT::i128) { - if (RetVT == MVT::f32) + } else if (OpVT == EVT::i128) { + if (RetVT == EVT::f32) return SINTTOFP_I128_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return SINTTOFP_I128_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return SINTTOFP_I128_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return SINTTOFP_I128_PPCF128; } return UNKNOWN_LIBCALL; @@ -390,33 +390,33 @@ RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) { /// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or /// UNKNOWN_LIBCALL if there is none. -RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) { - if (OpVT == MVT::i32) { - if (RetVT == MVT::f32) +RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) { + if (OpVT == EVT::i32) { + if (RetVT == EVT::f32) return UINTTOFP_I32_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return UINTTOFP_I32_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return UINTTOFP_I32_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return UINTTOFP_I32_PPCF128; - } else if (OpVT == MVT::i64) { - if (RetVT == MVT::f32) + } else if (OpVT == EVT::i64) { + if (RetVT == EVT::f32) return UINTTOFP_I64_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return UINTTOFP_I64_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return UINTTOFP_I64_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return UINTTOFP_I64_PPCF128; - } else if (OpVT == MVT::i128) { - if (RetVT == MVT::f32) + } else if (OpVT == EVT::i128) { + if (RetVT == EVT::f32) return UINTTOFP_I128_F32; - else if (RetVT == MVT::f64) + else if (RetVT == EVT::f64) return UINTTOFP_I128_F64; - else if (RetVT == MVT::f80) + else if (RetVT == EVT::f80) return UINTTOFP_I128_F80; - else if (RetVT == MVT::ppcf128) + else if (RetVT == EVT::ppcf128) return UINTTOFP_I128_PPCF128; } return UNKNOWN_LIBCALL; @@ -456,48 +456,48 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) memset(CondCodeActions, 0, sizeof(CondCodeActions)); // Set default actions for various operations. - for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) { + for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) { // Default all indexed load / store to expand. for (unsigned IM = (unsigned)ISD::PRE_INC; IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) { - setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand); - setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand); + setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand); + setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand); } // These operations default to expand. - setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand); } // Most targets ignore the @llvm.prefetch intrinsic. - setOperationAction(ISD::PREFETCH, MVT::Other, Expand); + setOperationAction(ISD::PREFETCH, EVT::Other, Expand); // ConstantFP nodes default to expand. Targets can either change this to // Legal, in which case all fp constants are legal, or use addLegalFPImmediate // to optimize expansions for certain constants. - setOperationAction(ISD::ConstantFP, MVT::f32, Expand); - setOperationAction(ISD::ConstantFP, MVT::f64, Expand); - setOperationAction(ISD::ConstantFP, MVT::f80, Expand); + setOperationAction(ISD::ConstantFP, EVT::f32, Expand); + setOperationAction(ISD::ConstantFP, EVT::f64, Expand); + setOperationAction(ISD::ConstantFP, EVT::f80, Expand); // These library functions default to expand. - setOperationAction(ISD::FLOG , MVT::f64, Expand); - setOperationAction(ISD::FLOG2, MVT::f64, Expand); - setOperationAction(ISD::FLOG10,MVT::f64, Expand); - setOperationAction(ISD::FEXP , MVT::f64, Expand); - setOperationAction(ISD::FEXP2, MVT::f64, Expand); - setOperationAction(ISD::FLOG , MVT::f32, Expand); - setOperationAction(ISD::FLOG2, MVT::f32, Expand); - setOperationAction(ISD::FLOG10,MVT::f32, Expand); - setOperationAction(ISD::FEXP , MVT::f32, Expand); - setOperationAction(ISD::FEXP2, MVT::f32, Expand); + setOperationAction(ISD::FLOG , EVT::f64, Expand); + setOperationAction(ISD::FLOG2, EVT::f64, Expand); + setOperationAction(ISD::FLOG10,EVT::f64, Expand); + setOperationAction(ISD::FEXP , EVT::f64, Expand); + setOperationAction(ISD::FEXP2, EVT::f64, Expand); + setOperationAction(ISD::FLOG , EVT::f32, Expand); + setOperationAction(ISD::FLOG2, EVT::f32, Expand); + setOperationAction(ISD::FLOG10,EVT::f32, Expand); + setOperationAction(ISD::FEXP , EVT::f32, Expand); + setOperationAction(ISD::FEXP2, EVT::f32, Expand); // Default ISD::TRAP to expand (which turns it into abort). - setOperationAction(ISD::TRAP, MVT::Other, Expand); + setOperationAction(ISD::TRAP, EVT::Other, Expand); IsLittleEndian = TD->isLittleEndian(); UsesGlobalOffsetTable = false; ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT(); - memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); + memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*)); memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray)); maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8; allowUnalignedMemoryAccesses = false; @@ -524,7 +524,7 @@ TargetLowering::TargetLowering(TargetMachine &tm,TargetLoweringObjectFile *tlof) // Tell Legalize whether the assembler supports DEBUG_LOC. const TargetAsmInfo *TASM = TM.getTargetAsmInfo(); if (!TASM || !TASM->hasDotLocAndDotFile()) - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); } TargetLowering::~TargetLowering() { @@ -534,31 +534,31 @@ TargetLowering::~TargetLowering() { /// computeRegisterProperties - Once all of the register classes are added, /// this allows us to compute derived properties we expose. void TargetLowering::computeRegisterProperties() { - assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && + assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); // Everything defaults to needing one register. - for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) { + for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) { NumRegistersForVT[i] = 1; - RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i; + RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i; } // ...except isVoid, which doesn't need any registers. - NumRegistersForVT[MVT::isVoid] = 0; + NumRegistersForVT[EVT::isVoid] = 0; // Find the largest integer register class. - unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE; + unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE; for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg) - assert(LargestIntReg != MVT::i1 && "No integer registers defined!"); + assert(LargestIntReg != EVT::i1 && "No integer registers defined!"); // Every integer value type larger than this largest register takes twice as // many registers to represent as the previous ValueType. for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) { - MVT EVT = (MVT::SimpleValueType)ExpandedReg; + EVT EVT = (EVT::SimpleValueType)ExpandedReg; if (!EVT.isInteger()) break; NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1]; - RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg; - TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1); + RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg; + TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1); ValueTypeActions.setTypeAction(EVT, Expand); } @@ -566,56 +566,56 @@ void TargetLowering::computeRegisterProperties() { // register to see which ones need promotion. unsigned LegalIntReg = LargestIntReg; for (unsigned IntReg = LargestIntReg - 1; - IntReg >= (unsigned)MVT::i1; --IntReg) { - MVT IVT = (MVT::SimpleValueType)IntReg; + IntReg >= (unsigned)EVT::i1; --IntReg) { + EVT IVT = (EVT::SimpleValueType)IntReg; if (isTypeLegal(IVT)) { LegalIntReg = IntReg; } else { RegisterTypeForVT[IntReg] = TransformToType[IntReg] = - (MVT::SimpleValueType)LegalIntReg; + (EVT::SimpleValueType)LegalIntReg; ValueTypeActions.setTypeAction(IVT, Promote); } } // ppcf128 type is really two f64's. - if (!isTypeLegal(MVT::ppcf128)) { - NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64]; - RegisterTypeForVT[MVT::ppcf128] = MVT::f64; - TransformToType[MVT::ppcf128] = MVT::f64; - ValueTypeActions.setTypeAction(MVT::ppcf128, Expand); + if (!isTypeLegal(EVT::ppcf128)) { + NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64]; + RegisterTypeForVT[EVT::ppcf128] = EVT::f64; + TransformToType[EVT::ppcf128] = EVT::f64; + ValueTypeActions.setTypeAction(EVT::ppcf128, Expand); } // Decide how to handle f64. If the target does not have native f64 support, // expand it to i64 and we will be generating soft float library calls. - if (!isTypeLegal(MVT::f64)) { - NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64]; - RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64]; - TransformToType[MVT::f64] = MVT::i64; - ValueTypeActions.setTypeAction(MVT::f64, Expand); + if (!isTypeLegal(EVT::f64)) { + NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64]; + RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64]; + TransformToType[EVT::f64] = EVT::i64; + ValueTypeActions.setTypeAction(EVT::f64, Expand); } // Decide how to handle f32. If the target does not have native support for // f32, promote it to f64 if it is legal. Otherwise, expand it to i32. - if (!isTypeLegal(MVT::f32)) { - if (isTypeLegal(MVT::f64)) { - NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64]; - RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64]; - TransformToType[MVT::f32] = MVT::f64; - ValueTypeActions.setTypeAction(MVT::f32, Promote); + if (!isTypeLegal(EVT::f32)) { + if (isTypeLegal(EVT::f64)) { + NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64]; + RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64]; + TransformToType[EVT::f32] = EVT::f64; + ValueTypeActions.setTypeAction(EVT::f32, Promote); } else { - NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32]; - RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32]; - TransformToType[MVT::f32] = MVT::i32; - ValueTypeActions.setTypeAction(MVT::f32, Expand); + NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32]; + RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32]; + TransformToType[EVT::f32] = EVT::i32; + ValueTypeActions.setTypeAction(EVT::f32, Expand); } } // Loop over all of the vector value types to see which need transformations. - for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE; - i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { - MVT VT = (MVT::SimpleValueType)i; + for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) { + EVT VT = (EVT::SimpleValueType)i; if (!isTypeLegal(VT)) { - MVT IntermediateVT, RegisterVT; + EVT IntermediateVT, RegisterVT; unsigned NumIntermediates; NumRegistersForVT[i] = getVectorTypeBreakdown(VT, @@ -625,10 +625,10 @@ void TargetLowering::computeRegisterProperties() { // Determine if there is a legal wider type. bool IsLegalWiderType = false; - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); unsigned NElts = VT.getVectorNumElements(); - for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { - MVT SVT = (MVT::SimpleValueType)nVT; + for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) { + EVT SVT = (EVT::SimpleValueType)nVT; if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts) { TransformToType[i] = SVT; @@ -638,10 +638,10 @@ void TargetLowering::computeRegisterProperties() { } } if (!IsLegalWiderType) { - MVT NVT = VT.getPow2VectorType(); + EVT NVT = VT.getPow2VectorType(); if (NVT == VT) { // Type is already a power of 2. The default action is to split. - TransformToType[i] = MVT::Other; + TransformToType[i] = EVT::Other; ValueTypeActions.setTypeAction(VT, Expand); } else { TransformToType[i] = NVT; @@ -657,27 +657,27 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { } -MVT::SimpleValueType TargetLowering::getSetCCResultType(MVT VT) const { +EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const { return getValueType(TD->getIntPtrType()).getSimpleVT(); } /// getVectorTypeBreakdown - Vector types are broken down into some number of -/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32 -/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack. -/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86. +/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32 +/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack. +/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86. /// /// This method returns the number of registers needed, and the VT for each /// register. It also returns the VT and quantity of the intermediate values /// before they are promoted/expanded. /// -unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, - MVT &IntermediateVT, +unsigned TargetLowering::getVectorTypeBreakdown(EVT VT, + EVT &IntermediateVT, unsigned &NumIntermediates, - MVT &RegisterVT) const { + EVT &RegisterVT) const { // Figure out the right, legal destination reg to copy into. unsigned NumElts = VT.getVectorNumElements(); - MVT EltTy = VT.getVectorElementType(); + EVT EltTy = VT.getVectorElementType(); unsigned NumVectorRegs = 1; @@ -690,19 +690,19 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, // Divide the input until we get to a supported size. This will always // end with a scalar if the target doesn't support vectors. - while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { + while (NumElts > 1 && !isTypeLegal(EVT::getVectorVT(EltTy, NumElts))) { NumElts >>= 1; NumVectorRegs <<= 1; } NumIntermediates = NumVectorRegs; - MVT NewVT = MVT::getVectorVT(EltTy, NumElts); + EVT NewVT = EVT::getVectorVT(EltTy, NumElts); if (!isTypeLegal(NewVT)) NewVT = EltTy; IntermediateVT = NewVT; - MVT DestVT = getRegisterType(NewVT); + EVT DestVT = getRegisterType(NewVT); RegisterVT = DestVT; if (DestVT.bitsLT(NewVT)) { // Value is expanded, e.g. i64 -> i16. @@ -718,16 +718,16 @@ unsigned TargetLowering::getVectorTypeBreakdown(MVT VT, /// getWidenVectorType: given a vector type, returns the type to widen to /// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. -/// If there is no vector type that we want to widen to, returns MVT::Other +/// If there is no vector type that we want to widen to, returns EVT::Other /// When and where to widen is target dependent based on the cost of /// scalarizing vs using the wider vector type. -MVT TargetLowering::getWidenVectorType(MVT VT) const { +EVT TargetLowering::getWidenVectorType(EVT VT) const { assert(VT.isVector()); if (isTypeLegal(VT)) return VT; // Default is not to widen until moved to LegalizeTypes - return MVT::Other; + return EVT::Other; } /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate @@ -788,7 +788,7 @@ bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, // if we can expand it to have all bits set, do it if (C->getAPIntValue().intersects(~Demanded)) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), DAG.getConstant(Demanded & C->getAPIntValue(), @@ -829,7 +829,7 @@ TargetLowering::TargetLoweringOpt::ShrinkDemandedOp(SDValue Op, if (!isPowerOf2_32(SmallVTBits)) SmallVTBits = NextPowerOf2(SmallVTBits); for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) { - MVT SmallVT = MVT::getIntegerVT(SmallVTBits); + EVT SmallVT = EVT::getIntegerVT(SmallVTBits); if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && TLI.isZExtFree(SmallVT, Op.getValueType())) { // We found a type with free casts. @@ -1015,7 +1015,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known if ((KnownOne & KnownOne2) == KnownOne) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), ANDC)); @@ -1030,7 +1030,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, // if we can expand it to have all bits set, do it if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), TLO.DAG.getConstant(Expanded, VT)); return TLO.CombineTo(Op, New); @@ -1106,7 +1106,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, SDValue NewSA = TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType()); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, InOp.getOperand(0), NewSA)); } @@ -1123,7 +1123,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, break; case ISD::SRL: if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned ShAmt = SA->getZExtValue(); unsigned VTSize = VT.getSizeInBits(); SDValue InOp = Op.getOperand(0); @@ -1175,7 +1175,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, Op.getOperand(0), Op.getOperand(1))); if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned ShAmt = SA->getZExtValue(); // If the shift count is an invalid immediate, don't do anything. @@ -1212,7 +1212,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, } break; case ISD::SIGN_EXTEND_INREG: { - MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT(); // Sign extension. Compute the demanded bits in the result that are not // present in the input. @@ -1279,7 +1279,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, break; } case ISD::SIGN_EXTEND: { - MVT InVT = Op.getOperand(0).getValueType(); + EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getSizeInBits(); APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); @@ -1378,7 +1378,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, break; } case ISD::AssertZext: { - MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); + EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask, @@ -1392,9 +1392,9 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op, #if 0 // If this is an FP->Int bitcast and if the sign bit is the only thing that // is demanded, turn this into a FGETSIGN. - if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) && - MVT::isFloatingPoint(Op.getOperand(0).getValueType()) && - !MVT::isVector(Op.getOperand(0).getValueType())) { + if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) && + EVT::isFloatingPoint(Op.getOperand(0).getValueType()) && + !EVT::isVector(Op.getOperand(0).getValueType())) { // Only do this xform if FGETSIGN is valid or if before legalize. if (!TLO.AfterLegalize || isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { @@ -1499,7 +1499,7 @@ static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { // to handle some common cases. // Fall back to ComputeMaskedBits to catch other known cases. - MVT OpVT = Val.getValueType(); + EVT OpVT = Val.getValueType(); unsigned BitWidth = OpVT.getSizeInBits(); APInt Mask = APInt::getAllOnesValue(BitWidth); APInt KnownZero, KnownOne; @@ -1511,7 +1511,7 @@ static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { /// SimplifySetCC - Try to simplify a setcc built with the specified operands /// and cc. If it is unable to simplify it, return a null SDValue. SDValue -TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, +TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, bool foldBooleans, DAGCombinerInfo &DCI, DebugLoc dl) const { SelectionDAG &DAG = DCI.DAG; @@ -1597,9 +1597,9 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, } } if (bestWidth) { - MVT newVT = MVT::getIntegerVT(bestWidth); + EVT newVT = EVT::getIntegerVT(bestWidth); if (newVT.isRound()) { - MVT PtrType = Lod->getOperand(1).getValueType(); + EVT PtrType = Lod->getOperand(1).getValueType(); SDValue Ptr = Lod->getBasePtr(); if (bestOffset != 0) Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(), @@ -1653,7 +1653,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, case ISD::SETUGE: case ISD::SETULT: case ISD::SETULE: { - MVT newVT = N0.getOperand(0).getValueType(); + EVT newVT = N0.getOperand(0).getValueType(); if (DCI.isBeforeLegalizeOps() || (isOperationLegal(ISD::SETCC, newVT) && getCondCodeAction(Cond, newVT)==Legal)) @@ -1667,9 +1667,9 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, } } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); + EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits(); - MVT ExtDstTy = N0.getValueType(); + EVT ExtDstTy = N0.getValueType(); unsigned ExtDstTyBits = ExtDstTy.getSizeInBits(); // If the extended part has any inconsistent bits, it cannot ever @@ -1681,7 +1681,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, return DAG.getConstant(Cond == ISD::SETNE, VT); SDValue ZextOp; - MVT Op0Ty = N0.getOperand(0).getValueType(); + EVT Op0Ty = N0.getOperand(0).getValueType(); if (Op0Ty == ExtSrcTy) { ZextOp = N0.getOperand(0); } else { @@ -1822,7 +1822,7 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, VT == N0.getValueType() && N0.getOpcode() == ISD::AND) if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { - MVT ShiftTy = DCI.isBeforeLegalize() ? + EVT ShiftTy = DCI.isBeforeLegalize() ? getPointerTy() : getShiftAmountTy(); if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. @@ -2010,46 +2010,46 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1, // Fold away ALL boolean setcc's. SDValue Temp; - if (N0.getValueType() == MVT::i1 && foldBooleans) { + if (N0.getValueType() == EVT::i1 && foldBooleans) { switch (Cond) { default: llvm_unreachable("Unknown integer setcc!"); case ISD::SETEQ: // X == Y -> ~(X^Y) - Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); - N0 = DAG.getNOT(dl, Temp, MVT::i1); + Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1); + N0 = DAG.getNOT(dl, Temp, EVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETNE: // X != Y --> (X^Y) - N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); + N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1); break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y - Temp = DAG.getNOT(dl, N0, MVT::i1); - N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp); + Temp = DAG.getNOT(dl, N0, EVT::i1); + N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X - Temp = DAG.getNOT(dl, N1, MVT::i1); - N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp); + Temp = DAG.getNOT(dl, N1, EVT::i1); + N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y - Temp = DAG.getNOT(dl, N0, MVT::i1); - N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp); + Temp = DAG.getNOT(dl, N0, EVT::i1); + N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X - Temp = DAG.getNOT(dl, N1, MVT::i1); - N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp); + Temp = DAG.getNOT(dl, N1, EVT::i1); + N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp); break; } - if (VT != MVT::i1) { + if (VT != EVT::i1) { if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(N0.getNode()); // FIXME: If running after legalize, we probably can't do this. @@ -2102,7 +2102,7 @@ bool TargetLowering::isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base, const MachineFrameInfo *MFI) const { if (LD->getChain() != Base->getChain()) return false; - MVT VT = LD->getValueType(0); + EVT VT = LD->getValueType(0); if (VT.getSizeInBits() / 8 != Bytes) return false; @@ -2183,7 +2183,7 @@ TargetLowering::getConstraintType(const std::string &Constraint) const { /// LowerXConstraint - try to replace an X constraint, which matches anything, /// with another that has more specific requirements based on the type of the /// corresponding operand. -const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{ +const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ if (ConstraintVT.isInteger()) return "r"; if (ConstraintVT.isFloatingPoint()) @@ -2245,7 +2245,7 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, // now; without this it would get ZExt'd later in // ScheduleDAGSDNodes::EmitNode, which is very generic. Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(), - MVT::i64)); + EVT::i64)); return; } } @@ -2256,14 +2256,14 @@ void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::vector<unsigned> TargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { return std::vector<unsigned>(); } std::pair<unsigned, const TargetRegisterClass*> TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint[0] != '{') return std::pair<unsigned, const TargetRegisterClass*>(0, 0); assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); @@ -2479,7 +2479,7 @@ bool TargetLowering::isLegalAddressingMode(const AddrMode &AM, /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, std::vector<SDNode*>* Created) const { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl= N->getDebugLoc(); // Check to see if we can do this. @@ -2536,7 +2536,7 @@ SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG, /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG, std::vector<SDNode*>* Created) const { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); // Check to see if we can do this. diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp index 823ae2f10e..07575290c1 100644 --- a/lib/Target/ARM/ARMISelDAGToDAG.cpp +++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp @@ -63,7 +63,7 @@ public: /// getI32Imm - Return a target constant with the specified value, of type i32. inline SDValue getI32Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } SDNode *Select(SDValue Op); @@ -156,13 +156,13 @@ bool ARMDAGToDAGISel::SelectShifterOperandReg(SDValue Op, BaseReg = N.getOperand(0); unsigned ShImmVal = 0; if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { - ShReg = CurDAG->getRegister(0, MVT::i32); + ShReg = CurDAG->getRegister(0, EVT::i32); ShImmVal = RHS->getZExtValue() & 31; } else { ShReg = N.getOperand(1); } Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal), - MVT::i32); + EVT::i32); return true; } @@ -185,7 +185,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, Base = Offset = N.getOperand(0); Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ARM_AM::lsl), - MVT::i32); + EVT::i32); return true; } } @@ -200,10 +200,10 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, } else if (N.getOpcode() == ARMISD::Wrapper) { Base = N.getOperand(0); } - Offset = CurDAG->getRegister(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(ARM_AM::add, 0, ARM_AM::no_shift), - MVT::i32); + EVT::i32); return true; } @@ -218,7 +218,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(Base)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - Offset = CurDAG->getRegister(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); ARM_AM::AddrOpc AddSub = ARM_AM::add; if (RHSC < 0) { @@ -227,7 +227,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, } Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, RHSC, ARM_AM::no_shift), - MVT::i32); + EVT::i32); return true; } } @@ -270,7 +270,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N, } Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), - MVT::i32); + EVT::i32); return true; } @@ -285,10 +285,10 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N, if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { int Val = (int)C->getZExtValue(); if (Val >= 0 && Val < 0x1000) { // 12 bits. - Offset = CurDAG->getRegister(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift), - MVT::i32); + EVT::i32); return true; } } @@ -308,7 +308,7 @@ bool ARMDAGToDAGISel::SelectAddrMode2Offset(SDValue Op, SDValue N, } Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt, ShOpcVal), - MVT::i32); + EVT::i32); return true; } @@ -320,7 +320,7 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N, // X - C is canonicalize to X + -C, no need to handle it here. Base = N.getOperand(0); Offset = N.getOperand(1); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),MVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::sub, 0),EVT::i32); return true; } @@ -330,8 +330,8 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(N)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - Offset = CurDAG->getRegister(0, MVT::i32); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0),EVT::i32); return true; } @@ -345,21 +345,21 @@ bool ARMDAGToDAGISel::SelectAddrMode3(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(Base)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - Offset = CurDAG->getRegister(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); ARM_AM::AddrOpc AddSub = ARM_AM::add; if (RHSC < 0) { AddSub = ARM_AM::sub; RHSC = - RHSC; } - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),MVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, RHSC),EVT::i32); return true; } } Base = N.getOperand(0); Offset = N.getOperand(1); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), MVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(ARM_AM::add, 0), EVT::i32); return true; } @@ -374,21 +374,21 @@ bool ARMDAGToDAGISel::SelectAddrMode3Offset(SDValue Op, SDValue N, if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N)) { int Val = (int)C->getZExtValue(); if (Val >= 0 && Val < 256) { - Offset = CurDAG->getRegister(0, MVT::i32); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, Val), EVT::i32); return true; } } Offset = N; - Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), MVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM3Opc(AddSub, 0), EVT::i32); return true; } bool ARMDAGToDAGISel::SelectAddrMode4(SDValue Op, SDValue N, SDValue &Addr, SDValue &Mode) { Addr = N; - Mode = CurDAG->getTargetConstant(0, MVT::i32); + Mode = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -403,7 +403,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N, Base = N.getOperand(0); } Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), - MVT::i32); + EVT::i32); return true; } @@ -426,7 +426,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N, RHSC = - RHSC; } Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(AddSub, RHSC), - MVT::i32); + EVT::i32); return true; } } @@ -434,7 +434,7 @@ bool ARMDAGToDAGISel::SelectAddrMode5(SDValue Op, SDValue N, Base = N; Offset = CurDAG->getTargetConstant(ARM_AM::getAM5Opc(ARM_AM::add, 0), - MVT::i32); + EVT::i32); return true; } @@ -443,8 +443,8 @@ bool ARMDAGToDAGISel::SelectAddrMode6(SDValue Op, SDValue N, SDValue &Opc) { Addr = N; // The optional writeback is handled in ARMLoadStoreOpt. - Update = CurDAG->getRegister(0, MVT::i32); - Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), MVT::i32); + Update = CurDAG->getRegister(0, EVT::i32); + Opc = CurDAG->getTargetConstant(ARM_AM::getAM6Opc(false), EVT::i32); return true; } @@ -454,7 +454,7 @@ bool ARMDAGToDAGISel::SelectAddrModePC(SDValue Op, SDValue N, Offset = N.getOperand(0); SDValue N1 = N.getOperand(1); Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(), - MVT::i32); + EVT::i32); return true; } return false; @@ -493,8 +493,8 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, if (N.getOpcode() != ISD::ADD) { Base = (N.getOpcode() == ARMISD::Wrapper) ? N.getOperand(0) : N; - Offset = CurDAG->getRegister(0, MVT::i32); - OffImm = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); + OffImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -504,8 +504,8 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, if ((LHSR && LHSR->getReg() == ARM::SP) || (RHSR && RHSR->getReg() == ARM::SP)) { Base = N; - Offset = CurDAG->getRegister(0, MVT::i32); - OffImm = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); + OffImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -516,8 +516,8 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, RHSC /= Scale; if (RHSC >= 0 && RHSC < 32) { Base = N.getOperand(0); - Offset = CurDAG->getRegister(0, MVT::i32); - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + Offset = CurDAG->getRegister(0, EVT::i32); + OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32); return true; } } @@ -525,7 +525,7 @@ ARMDAGToDAGISel::SelectThumbAddrModeRI5(SDValue Op, SDValue N, Base = N.getOperand(0); Offset = N.getOperand(1); - OffImm = CurDAG->getTargetConstant(0, MVT::i32); + OffImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -552,7 +552,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N, if (N.getOpcode() == ISD::FrameIndex) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); - OffImm = CurDAG->getTargetConstant(0, MVT::i32); + OffImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -573,7 +573,7 @@ bool ARMDAGToDAGISel::SelectThumbAddrModeSP(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(Base)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32); return true; } } @@ -612,7 +612,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N, if (N.getOpcode() == ISD::FrameIndex) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); - OffImm = CurDAG->getTargetConstant(0, MVT::i32); + OffImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } return false; @@ -629,7 +629,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm12(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(Base)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32); return true; } } @@ -652,7 +652,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8(SDValue Op, SDValue N, int FI = cast<FrameIndexSDNode>(Base)->getIndex(); Base = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); } - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32); return true; } } @@ -671,8 +671,8 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8Offset(SDValue Op, SDValue N, int RHSC = (int)RHS->getZExtValue(); if (RHSC >= 0 && RHSC < 0x100) { // 8 bits. OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) - ? CurDAG->getTargetConstant(RHSC, MVT::i32) - : CurDAG->getTargetConstant(-RHSC, MVT::i32); + ? CurDAG->getTargetConstant(RHSC, EVT::i32) + : CurDAG->getTargetConstant(-RHSC, EVT::i32); return true; } } @@ -688,7 +688,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N, if (((RHSC & 0x3) == 0) && ((RHSC >= 0 && RHSC < 0x400) || (RHSC < 0 && RHSC > -0x400))) { // 8 bits. Base = N.getOperand(0); - OffImm = CurDAG->getTargetConstant(RHSC, MVT::i32); + OffImm = CurDAG->getTargetConstant(RHSC, EVT::i32); return true; } } @@ -697,7 +697,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeImm8s4(SDValue Op, SDValue N, int RHSC = (int)RHS->getZExtValue(); if (((RHSC & 0x3) == 0) && (RHSC >= 0 && RHSC < 0x400)) { // 8 bits. Base = N.getOperand(0); - OffImm = CurDAG->getTargetConstant(-RHSC, MVT::i32); + OffImm = CurDAG->getTargetConstant(-RHSC, EVT::i32); return true; } } @@ -719,8 +719,8 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N, if (Base.getOpcode() == ISD::TargetConstantPool) return false; // We want to select t2LDRpci instead. } - OffReg = CurDAG->getRegister(0, MVT::i32); - ShImm = CurDAG->getTargetConstant(0, MVT::i32); + OffReg = CurDAG->getRegister(0, EVT::i32); + ShImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -736,8 +736,8 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N, // Thumb2 does not support (R - R) or (R - (R << [1,2,3])). if (N.getOpcode() == ISD::SUB) { Base = N; - OffReg = CurDAG->getRegister(0, MVT::i32); - ShImm = CurDAG->getTargetConstant(0, MVT::i32); + OffReg = CurDAG->getRegister(0, EVT::i32); + ShImm = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -771,7 +771,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N, } } - ShImm = CurDAG->getTargetConstant(ShAmt, MVT::i32); + ShImm = CurDAG->getTargetConstant(ShAmt, EVT::i32); return true; } @@ -780,7 +780,7 @@ bool ARMDAGToDAGISel::SelectT2AddrModeSoReg(SDValue Op, SDValue N, /// getAL - Returns a ARMCC::AL immediate node. static inline SDValue getAL(SelectionDAG *CurDAG) { - return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, MVT::i32); + return CurDAG->getTargetConstant((uint64_t)ARMCC::AL, EVT::i32); } SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) { @@ -789,22 +789,22 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) { if (AM == ISD::UNINDEXED) return NULL; - MVT LoadedVT = LD->getMemoryVT(); + EVT LoadedVT = LD->getMemoryVT(); SDValue Offset, AMOpc; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); unsigned Opcode = 0; bool Match = false; - if (LoadedVT == MVT::i32 && + if (LoadedVT == EVT::i32 && SelectAddrMode2Offset(Op, LD->getOffset(), Offset, AMOpc)) { Opcode = isPre ? ARM::LDR_PRE : ARM::LDR_POST; Match = true; - } else if (LoadedVT == MVT::i16 && + } else if (LoadedVT == EVT::i16 && SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) { Match = true; Opcode = (LD->getExtensionType() == ISD::SEXTLOAD) ? (isPre ? ARM::LDRSH_PRE : ARM::LDRSH_POST) : (isPre ? ARM::LDRH_PRE : ARM::LDRH_POST); - } else if (LoadedVT == MVT::i8 || LoadedVT == MVT::i1) { + } else if (LoadedVT == EVT::i8 || LoadedVT == EVT::i1) { if (LD->getExtensionType() == ISD::SEXTLOAD) { if (SelectAddrMode3Offset(Op, LD->getOffset(), Offset, AMOpc)) { Match = true; @@ -822,9 +822,9 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDValue Op) { SDValue Chain = LD->getChain(); SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, - MVT::Other, Ops, 6); + CurDAG->getRegister(0, EVT::i32), Chain }; + return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32, + EVT::Other, Ops, 6); } return NULL; @@ -836,7 +836,7 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { if (AM == ISD::UNINDEXED) return NULL; - MVT LoadedVT = LD->getMemoryVT(); + EVT LoadedVT = LD->getMemoryVT(); bool isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD; SDValue Offset; bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); @@ -844,17 +844,17 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { bool Match = false; if (SelectT2AddrModeImm8Offset(Op, LD->getOffset(), Offset)) { switch (LoadedVT.getSimpleVT()) { - case MVT::i32: + case EVT::i32: Opcode = isPre ? ARM::t2LDR_PRE : ARM::t2LDR_POST; break; - case MVT::i16: + case EVT::i16: if (isSExtLd) Opcode = isPre ? ARM::t2LDRSH_PRE : ARM::t2LDRSH_POST; else Opcode = isPre ? ARM::t2LDRH_PRE : ARM::t2LDRH_POST; break; - case MVT::i8: - case MVT::i1: + case EVT::i8: + case EVT::i1: if (isSExtLd) Opcode = isPre ? ARM::t2LDRSB_PRE : ARM::t2LDRSB_POST; else @@ -870,9 +870,9 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { SDValue Chain = LD->getChain(); SDValue Base = LD->getBasePtr(); SDValue Ops[]= { Base, Offset, getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32), Chain }; - return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), MVT::i32, MVT::i32, - MVT::Other, Ops, 5); + CurDAG->getRegister(0, EVT::i32), Chain }; + return CurDAG->getTargetNode(Opcode, Op.getDebugLoc(), EVT::i32, EVT::i32, + EVT::Other, Ops, 5); } return NULL; @@ -881,11 +881,11 @@ SDNode *ARMDAGToDAGISel::SelectT2IndexedLoad(SDValue Op) { SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) { SDNode *N = Op.getNode(); DebugLoc dl = N->getDebugLoc(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); SDValue Align = Op.getOperand(2); - SDValue SP = CurDAG->getRegister(ARM::SP, MVT::i32); + SDValue SP = CurDAG->getRegister(ARM::SP, EVT::i32); int32_t AlignVal = cast<ConstantSDNode>(Align)->getSExtValue(); if (AlignVal < 0) // We need to align the stack. Use Thumb1 tAND which is the only thumb @@ -900,8 +900,8 @@ SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) { // tSUBspi - immediate is between 0 ... 508 inclusive. if (C <= 508 && ((C & 3) == 0)) // FIXME: tSUBspi encode scale 4 implicitly. - return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, MVT::Other, SP, - CurDAG->getTargetConstant(C/4, MVT::i32), + return CurDAG->SelectNodeTo(N, ARM::tSUBspi_, VT, EVT::Other, SP, + CurDAG->getTargetConstant(C/4, EVT::i32), Chain); if (Subtarget->isThumb1Only()) { @@ -909,22 +909,22 @@ SDNode *ARMDAGToDAGISel::SelectDYN_ALLOC(SDValue Op) { // should have negated the size operand already. FIXME: We can't insert // new target independent node at this stage so we are forced to negate // it earlier. Is there a better solution? - return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, MVT::Other, SP, Size, + return CurDAG->SelectNodeTo(N, ARM::tADDspr_, VT, EVT::Other, SP, Size, Chain); } else if (Subtarget->isThumb2()) { if (isC && Predicate_t2_so_imm(Size.getNode())) { // t2SUBrSPi - SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain }; - return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, MVT::Other, Ops, 3); + SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain }; + return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi_, VT, EVT::Other, Ops, 3); } else if (isC && Predicate_imm0_4095(Size.getNode())) { // t2SUBrSPi12 - SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, MVT::i32), Chain }; - return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, MVT::Other, Ops, 3); + SDValue Ops[] = { SP, CurDAG->getTargetConstant(C, EVT::i32), Chain }; + return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPi12_, VT, EVT::Other, Ops, 3); } else { // t2SUBrSPs SDValue Ops[] = { SP, Size, getI32Imm(ARM_AM::getSORegOpc(ARM_AM::lsl,0)), Chain }; - return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, MVT::Other, Ops, 4); + return CurDAG->SelectNodeTo(N, ARM::t2SUBrSPs_, VT, EVT::Other, Ops, 4); } } @@ -964,21 +964,21 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDNode *ResNode; if (Subtarget->isThumb1Only()) { - SDValue Pred = CurDAG->getTargetConstant(0xEULL, MVT::i32); - SDValue PredReg = CurDAG->getRegister(0, MVT::i32); + SDValue Pred = CurDAG->getTargetConstant(0xEULL, EVT::i32); + SDValue PredReg = CurDAG->getRegister(0, EVT::i32); SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; - ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, MVT::i32, MVT::Other, + ResNode = CurDAG->getTargetNode(ARM::tLDRcp, dl, EVT::i32, EVT::Other, Ops, 4); } else { SDValue Ops[] = { CPIdx, - CurDAG->getRegister(0, MVT::i32), - CurDAG->getTargetConstant(0, MVT::i32), + CurDAG->getRegister(0, EVT::i32), + CurDAG->getTargetConstant(0, EVT::i32), getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32), + CurDAG->getRegister(0, EVT::i32), CurDAG->getEntryNode() }; - ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, MVT::i32, MVT::Other, + ResNode=CurDAG->getTargetNode(ARM::LDRcp, dl, EVT::i32, EVT::Other, Ops, 6); } ReplaceUses(Op, SDValue(ResNode, 0)); @@ -990,19 +990,19 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { } case ISD::ConstantFP: { ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(N); - MVT VT = CFP->getValueType(0); + EVT VT = CFP->getValueType(0); ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); SDValue CPIdx = CurDAG->getTargetConstantPool(LLVMC, TLI.getPointerTy()); SDNode *ResNode; SDValue Ops[] = { CPIdx, - CurDAG->getTargetConstant(0, MVT::i32), + CurDAG->getTargetConstant(0, EVT::i32), getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32), + CurDAG->getRegister(0, EVT::i32), CurDAG->getEntryNode() }; - unsigned Opc = (VT == MVT::f32) ? ARM::FLDS : ARM::FLDD; - ResNode=CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Ops, 5); + unsigned Opc = (VT == EVT::f32) ? ARM::FLDS : ARM::FLDD; + ResNode=CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Ops, 5); ReplaceUses(Op, SDValue(ResNode, 0)); return NULL; } @@ -1011,15 +1011,15 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { int FI = cast<FrameIndexSDNode>(N)->getIndex(); SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); if (Subtarget->isThumb1Only()) { - return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, TFI, - CurDAG->getTargetConstant(0, MVT::i32)); + return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, EVT::i32, TFI, + CurDAG->getTargetConstant(0, EVT::i32)); } else { unsigned Opc = ((Subtarget->isThumb() && Subtarget->hasThumb2()) ? ARM::t2ADDri : ARM::ADDri); - SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32), - getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), - CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5); + SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, EVT::i32), + getAL(CurDAG), CurDAG->getRegister(0, EVT::i32), + CurDAG->getRegister(0, EVT::i32) }; + return CurDAG->SelectNodeTo(N, Opc, EVT::i32, Ops, 5); } } case ARMISD::DYN_ALLOC: @@ -1036,14 +1036,14 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { break; SDValue V = Op.getOperand(0); ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); - SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); - SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); + SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32); + SDValue Reg0 = CurDAG->getRegister(0, EVT::i32); if (Subtarget->isThumb()) { SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; - return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6); + return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, EVT::i32, Ops, 6); } else { SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; - return CurDAG->SelectNodeTo(N, ARM::ADDrs, MVT::i32, Ops, 7); + return CurDAG->SelectNodeTo(N, ARM::ADDrs, EVT::i32, Ops, 7); } } if (isPowerOf2_32(RHSV+1)) { // 2^n-1? @@ -1052,35 +1052,35 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { break; SDValue V = Op.getOperand(0); ShImm = ARM_AM::getSORegOpc(ARM_AM::lsl, ShImm); - SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, MVT::i32); - SDValue Reg0 = CurDAG->getRegister(0, MVT::i32); + SDValue ShImmOp = CurDAG->getTargetConstant(ShImm, EVT::i32); + SDValue Reg0 = CurDAG->getRegister(0, EVT::i32); if (Subtarget->isThumb()) { SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0 }; - return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 5); + return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, EVT::i32, Ops, 5); } else { SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 }; - return CurDAG->SelectNodeTo(N, ARM::RSBrs, MVT::i32, Ops, 7); + return CurDAG->SelectNodeTo(N, ARM::RSBrs, EVT::i32, Ops, 7); } } } break; case ARMISD::FMRRD: - return CurDAG->getTargetNode(ARM::FMRRD, dl, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(ARM::FMRRD, dl, EVT::i32, EVT::i32, Op.getOperand(0), getAL(CurDAG), - CurDAG->getRegister(0, MVT::i32)); + CurDAG->getRegister(0, EVT::i32)); case ISD::UMUL_LOHI: { if (Subtarget->isThumb1Only()) break; if (Subtarget->isThumb()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), - getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), - CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32, Ops,4); + getAL(CurDAG), CurDAG->getRegister(0, EVT::i32), + CurDAG->getRegister(0, EVT::i32) }; + return CurDAG->getTargetNode(ARM::t2UMULL, dl, EVT::i32, EVT::i32, Ops,4); } else { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), - getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), - CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::UMULL, dl, MVT::i32, MVT::i32, Ops, 5); + getAL(CurDAG), CurDAG->getRegister(0, EVT::i32), + CurDAG->getRegister(0, EVT::i32) }; + return CurDAG->getTargetNode(ARM::UMULL, dl, EVT::i32, EVT::i32, Ops, 5); } } case ISD::SMUL_LOHI: { @@ -1088,13 +1088,13 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { break; if (Subtarget->isThumb()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), - getAL(CurDAG), CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32, Ops,4); + getAL(CurDAG), CurDAG->getRegister(0, EVT::i32) }; + return CurDAG->getTargetNode(ARM::t2SMULL, dl, EVT::i32, EVT::i32, Ops,4); } else { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), - getAL(CurDAG), CurDAG->getRegister(0, MVT::i32), - CurDAG->getRegister(0, MVT::i32) }; - return CurDAG->getTargetNode(ARM::SMULL, dl, MVT::i32, MVT::i32, Ops, 5); + getAL(CurDAG), CurDAG->getRegister(0, EVT::i32), + CurDAG->getRegister(0, EVT::i32) }; + return CurDAG->getTargetNode(ARM::SMULL, dl, EVT::i32, EVT::i32, Ops, 5); } } case ISD::LOAD: { @@ -1134,10 +1134,10 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag }; - SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, MVT::Other, - MVT::Flag, Ops, 5); + SDNode *ResNode = CurDAG->getTargetNode(Opc, dl, EVT::Other, + EVT::Flag, Ops, 5); Chain = SDValue(ResNode, 0); if (Op.getNode()->getNumValues() == 2) { InFlag = SDValue(ResNode, 1); @@ -1147,7 +1147,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { return NULL; } case ARMISD::CMOV: { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); @@ -1156,7 +1156,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { assert(N2.getOpcode() == ISD::Constant); assert(N3.getOpcode() == ISD::Register); - if (!Subtarget->isThumb1Only() && VT == MVT::i32) { + if (!Subtarget->isThumb1Only() && VT == EVT::i32) { // Pattern: (ARMcmov:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) // Emits: (MOVCCs:i32 GPR:i32:$false, so_reg:i32:$true, (imm:i32):$cc) // Pattern complexity = 18 cost = 1 size = 0 @@ -1178,21 +1178,21 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { break; } SDValue SOShImm = - CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), MVT::i32); + CurDAG->getTargetConstant(ARM_AM::getSORegOffset(SOVal), EVT::i32); SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, CPTmp0, SOShImm, Tmp2, N3, InFlag }; - return CurDAG->SelectNodeTo(Op.getNode(), Opc, MVT::i32,Ops, 6); + return CurDAG->SelectNodeTo(Op.getNode(), Opc, EVT::i32,Ops, 6); } } else { if (SelectShifterOperandReg(Op, N1, CPTmp0, CPTmp1, CPTmp2)) { SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag }; return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCs, MVT::i32, Ops, 7); + ARM::MOVCCs, EVT::i32, Ops, 7); } } @@ -1207,25 +1207,25 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { if (Predicate_t2_so_imm(N3.getNode())) { SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; return CurDAG->SelectNodeTo(Op.getNode(), - ARM::t2MOVCCi, MVT::i32, Ops, 5); + ARM::t2MOVCCi, EVT::i32, Ops, 5); } } else { if (Predicate_so_imm(N3.getNode())) { SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N1)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag }; return CurDAG->SelectNodeTo(Op.getNode(), - ARM::MOVCCi, MVT::i32, Ops, 5); + ARM::MOVCCi, EVT::i32, Ops, 5); } } } @@ -1242,28 +1242,28 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { // Also FCPYScc and FCPYDcc. SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); break; - case MVT::i32: + case EVT::i32: Opc = Subtarget->isThumb() ? (Subtarget->hasThumb2() ? ARM::t2MOVCCr : ARM::tMOVCCr) : ARM::MOVCCr; break; - case MVT::f32: + case EVT::f32: Opc = ARM::FCPYScc; break; - case MVT::f64: + case EVT::f64: Opc = ARM::FCPYDcc; break; } return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5); } case ARMISD::CNEG: { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue N0 = Op.getOperand(0); SDValue N1 = Op.getOperand(1); SDValue N2 = Op.getOperand(2); @@ -1274,16 +1274,16 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned) cast<ConstantSDNode>(N2)->getZExtValue()), - MVT::i32); + EVT::i32); SDValue Ops[] = { N0, N1, Tmp2, N3, InFlag }; unsigned Opc = 0; switch (VT.getSimpleVT()) { default: assert(false && "Illegal conditional move type!"); break; - case MVT::f32: + case EVT::f32: Opc = ARM::FNEGScc; break; - case MVT::f64: + case EVT::f64: Opc = ARM::FNEGDcc; break; } @@ -1328,11 +1328,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); SDValue Ops[] = { Tmp1, Tmp2, Chain }; return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, - MVT::Other, Ops, 3); + EVT::Other, Ops, 3); } case ISD::VECTOR_SHUFFLE: { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); // Match 128-bit splat to VDUPLANEQ. (This could be done with a Pat in // ARMInstrNEON.td but it is awkward because the shuffle mask needs to be @@ -1345,22 +1345,22 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { Op.getOperand(1).getOpcode() == ISD::UNDEF) { unsigned LaneVal = SVOp->getSplatIndex(); - MVT HalfVT; + EVT HalfVT; unsigned Opc = 0; switch (VT.getVectorElementType().getSimpleVT()) { default: llvm_unreachable("unhandled VDUP splat type"); - case MVT::i8: Opc = ARM::VDUPLN8q; HalfVT = MVT::v8i8; break; - case MVT::i16: Opc = ARM::VDUPLN16q; HalfVT = MVT::v4i16; break; - case MVT::i32: Opc = ARM::VDUPLN32q; HalfVT = MVT::v2i32; break; - case MVT::f32: Opc = ARM::VDUPLNfq; HalfVT = MVT::v2f32; break; + case EVT::i8: Opc = ARM::VDUPLN8q; HalfVT = EVT::v8i8; break; + case EVT::i16: Opc = ARM::VDUPLN16q; HalfVT = EVT::v4i16; break; + case EVT::i32: Opc = ARM::VDUPLN32q; HalfVT = EVT::v2i32; break; + case EVT::f32: Opc = ARM::VDUPLNfq; HalfVT = EVT::v2f32; break; } // The source operand needs to be changed to a subreg of the original // 128-bit operand, and the lane number needs to be adjusted accordingly. unsigned NumElts = VT.getVectorNumElements() / 2; unsigned SRVal = (LaneVal < NumElts ? arm_dsubreg_0 : arm_dsubreg_1); - SDValue SR = CurDAG->getTargetConstant(SRVal, MVT::i32); - SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, MVT::i32); + SDValue SR = CurDAG->getTargetConstant(SRVal, EVT::i32); + SDValue NewLane = CurDAG->getTargetConstant(LaneVal % NumElts, EVT::i32); SDNode *SubReg = CurDAG->getTargetNode(TargetInstrInfo::EXTRACT_SUBREG, dl, HalfVT, N->getOperand(0), SR); return CurDAG->SelectNodeTo(N, Opc, VT, SDValue(SubReg, 0), NewLane); @@ -1374,16 +1374,16 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc)) return NULL; unsigned Opc = 0; - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); switch (VT.getSimpleVT()) { default: llvm_unreachable("unhandled VLD2D type"); - case MVT::v8i8: Opc = ARM::VLD2d8; break; - case MVT::v4i16: Opc = ARM::VLD2d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VLD2d32; break; + case EVT::v8i8: Opc = ARM::VLD2d8; break; + case EVT::v4i16: Opc = ARM::VLD2d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VLD2d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3); + return CurDAG->getTargetNode(Opc, dl, VT, VT, EVT::Other, Ops, 3); } case ARMISD::VLD3D: { @@ -1391,16 +1391,16 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc)) return NULL; unsigned Opc = 0; - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); switch (VT.getSimpleVT()) { default: llvm_unreachable("unhandled VLD3D type"); - case MVT::v8i8: Opc = ARM::VLD3d8; break; - case MVT::v4i16: Opc = ARM::VLD3d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VLD3d32; break; + case EVT::v8i8: Opc = ARM::VLD3d8; break; + case EVT::v4i16: Opc = ARM::VLD3d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VLD3d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; - return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3); + return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, EVT::Other, Ops, 3); } case ARMISD::VLD4D: { @@ -1408,17 +1408,17 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { if (!SelectAddrMode6(Op, N->getOperand(1), MemAddr, MemUpdate, MemOpc)) return NULL; unsigned Opc = 0; - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); switch (VT.getSimpleVT()) { default: llvm_unreachable("unhandled VLD4D type"); - case MVT::v8i8: Opc = ARM::VLD4d8; break; - case MVT::v4i16: Opc = ARM::VLD4d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VLD4d32; break; + case EVT::v8i8: Opc = ARM::VLD4d8; break; + case EVT::v4i16: Opc = ARM::VLD4d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VLD4d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc }; - std::vector<MVT> ResTys(4, VT); - ResTys.push_back(MVT::Other); + std::vector<EVT> ResTys(4, VT); + ResTys.push_back(EVT::Other); return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3); } @@ -1429,14 +1429,14 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { unsigned Opc = 0; switch (N->getOperand(2).getValueType().getSimpleVT()) { default: llvm_unreachable("unhandled VST2D type"); - case MVT::v8i8: Opc = ARM::VST2d8; break; - case MVT::v4i16: Opc = ARM::VST2d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VST2d32; break; + case EVT::v8i8: Opc = ARM::VST2d8; break; + case EVT::v4i16: Opc = ARM::VST2d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VST2d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(2), N->getOperand(3) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5); + return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 5); } case ARMISD::VST3D: { @@ -1446,15 +1446,15 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { unsigned Opc = 0; switch (N->getOperand(2).getValueType().getSimpleVT()) { default: llvm_unreachable("unhandled VST3D type"); - case MVT::v8i8: Opc = ARM::VST3d8; break; - case MVT::v4i16: Opc = ARM::VST3d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VST3d32; break; + case EVT::v8i8: Opc = ARM::VST3d8; break; + case EVT::v4i16: Opc = ARM::VST3d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VST3d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(2), N->getOperand(3), N->getOperand(4) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6); + return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 6); } case ARMISD::VST4D: { @@ -1464,20 +1464,20 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { unsigned Opc = 0; switch (N->getOperand(2).getValueType().getSimpleVT()) { default: llvm_unreachable("unhandled VST4D type"); - case MVT::v8i8: Opc = ARM::VST4d8; break; - case MVT::v4i16: Opc = ARM::VST4d16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VST4d32; break; + case EVT::v8i8: Opc = ARM::VST4d8; break; + case EVT::v4i16: Opc = ARM::VST4d16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VST4d32; break; } const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, N->getOperand(2), N->getOperand(3), N->getOperand(4), N->getOperand(5) }; - return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7); + return CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7); } case ISD::INTRINSIC_WO_CHAIN: { unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); unsigned Opc = 0; // Match intrinsics that return multiple values. @@ -1488,14 +1488,14 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case Intrinsic::arm_neon_vtrnf: switch (VT.getSimpleVT()) { default: return NULL; - case MVT::v8i8: Opc = ARM::VTRNd8; break; - case MVT::v4i16: Opc = ARM::VTRNd16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VTRNd32; break; - case MVT::v16i8: Opc = ARM::VTRNq8; break; - case MVT::v8i16: Opc = ARM::VTRNq16; break; - case MVT::v4f32: - case MVT::v4i32: Opc = ARM::VTRNq32; break; + case EVT::v8i8: Opc = ARM::VTRNd8; break; + case EVT::v4i16: Opc = ARM::VTRNd16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VTRNd32; break; + case EVT::v16i8: Opc = ARM::VTRNq8; break; + case EVT::v8i16: Opc = ARM::VTRNq16; break; + case EVT::v4f32: + case EVT::v4i32: Opc = ARM::VTRNq32; break; } return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1), N->getOperand(2)); @@ -1504,14 +1504,14 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case Intrinsic::arm_neon_vuzpf: switch (VT.getSimpleVT()) { default: return NULL; - case MVT::v8i8: Opc = ARM::VUZPd8; break; - case MVT::v4i16: Opc = ARM::VUZPd16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VUZPd32; break; - case MVT::v16i8: Opc = ARM::VUZPq8; break; - case MVT::v8i16: Opc = ARM::VUZPq16; break; - case MVT::v4f32: - case MVT::v4i32: Opc = ARM::VUZPq32; break; + case EVT::v8i8: Opc = ARM::VUZPd8; break; + case EVT::v4i16: Opc = ARM::VUZPd16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VUZPd32; break; + case EVT::v16i8: Opc = ARM::VUZPq8; break; + case EVT::v8i16: Opc = ARM::VUZPq16; break; + case EVT::v4f32: + case EVT::v4i32: Opc = ARM::VUZPq32; break; } return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1), N->getOperand(2)); @@ -1520,14 +1520,14 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) { case Intrinsic::arm_neon_vzipf: switch (VT.getSimpleVT()) { default: return NULL; - case MVT::v8i8: Opc = ARM::VZIPd8; break; - case MVT::v4i16: Opc = ARM::VZIPd16; break; - case MVT::v2f32: - case MVT::v2i32: Opc = ARM::VZIPd32; break; - case MVT::v16i8: Opc = ARM::VZIPq8; break; - case MVT::v8i16: Opc = ARM::VZIPq16; break; - case MVT::v4f32: - case MVT::v4i32: Opc = ARM::VZIPq32; break; + case EVT::v8i8: Opc = ARM::VZIPd8; break; + case EVT::v4i16: Opc = ARM::VZIPd16; break; + case EVT::v2f32: + case EVT::v2i32: Opc = ARM::VZIPd32; break; + case EVT::v16i8: Opc = ARM::VZIPq8; break; + case EVT::v8i16: Opc = ARM::VZIPq16; break; + case EVT::v4f32: + case EVT::v4i32: Opc = ARM::VZIPq32; break; } return CurDAG->getTargetNode(Opc, dl, VT, VT, N->getOperand(1), N->getOperand(2)); diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 8678e03bc1..aedddaa20b 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -41,25 +41,25 @@ #include "llvm/Support/MathExtras.h" using namespace llvm; -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, - MVT PromotedBitwiseVT) { +void ARMTargetLowering::addTypeForNEON(EVT VT, EVT PromotedLdStVT, + EVT PromotedBitwiseVT) { if (VT != PromotedLdStVT) { setOperationAction(ISD::LOAD, VT.getSimpleVT(), Promote); AddPromotedToType (ISD::LOAD, VT.getSimpleVT(), @@ -70,10 +70,10 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, PromotedLdStVT.getSimpleVT()); } - MVT ElemTy = VT.getVectorElementType(); - if (ElemTy != MVT::i64 && ElemTy != MVT::f64) + EVT ElemTy = VT.getVectorElementType(); + if (ElemTy != EVT::i64 && ElemTy != EVT::f64) setOperationAction(ISD::VSETCC, VT.getSimpleVT(), Custom); - if (ElemTy == MVT::i8 || ElemTy == MVT::i16) + if (ElemTy == EVT::i8 || ElemTy == EVT::i16) setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); setOperationAction(ISD::BUILD_VECTOR, VT.getSimpleVT(), Custom); setOperationAction(ISD::VECTOR_SHUFFLE, VT.getSimpleVT(), Custom); @@ -99,14 +99,14 @@ void ARMTargetLowering::addTypeForNEON(MVT VT, MVT PromotedLdStVT, } } -void ARMTargetLowering::addDRTypeForNEON(MVT VT) { +void ARMTargetLowering::addDRTypeForNEON(EVT VT) { addRegisterClass(VT, ARM::DPRRegisterClass); - addTypeForNEON(VT, MVT::f64, MVT::v2i32); + addTypeForNEON(VT, EVT::f64, EVT::v2i32); } -void ARMTargetLowering::addQRTypeForNEON(MVT VT) { +void ARMTargetLowering::addQRTypeForNEON(EVT VT) { addRegisterClass(VT, ARM::QPRRegisterClass); - addTypeForNEON(VT, MVT::v2f64, MVT::v4i32); + addTypeForNEON(VT, EVT::v2f64, EVT::v4i32); } static TargetLoweringObjectFile *createTLOF(TargetMachine &TM) { @@ -202,29 +202,29 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) setLibcallName(RTLIB::SRA_I128, 0); if (Subtarget->isThumb1Only()) - addRegisterClass(MVT::i32, ARM::tGPRRegisterClass); + addRegisterClass(EVT::i32, ARM::tGPRRegisterClass); else - addRegisterClass(MVT::i32, ARM::GPRRegisterClass); + addRegisterClass(EVT::i32, ARM::GPRRegisterClass); if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { - addRegisterClass(MVT::f32, ARM::SPRRegisterClass); - addRegisterClass(MVT::f64, ARM::DPRRegisterClass); + addRegisterClass(EVT::f32, ARM::SPRRegisterClass); + addRegisterClass(EVT::f64, ARM::DPRRegisterClass); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); } if (Subtarget->hasNEON()) { - addDRTypeForNEON(MVT::v2f32); - addDRTypeForNEON(MVT::v8i8); - addDRTypeForNEON(MVT::v4i16); - addDRTypeForNEON(MVT::v2i32); - addDRTypeForNEON(MVT::v1i64); - - addQRTypeForNEON(MVT::v4f32); - addQRTypeForNEON(MVT::v2f64); - addQRTypeForNEON(MVT::v16i8); - addQRTypeForNEON(MVT::v8i16); - addQRTypeForNEON(MVT::v4i32); - addQRTypeForNEON(MVT::v2i64); + addDRTypeForNEON(EVT::v2f32); + addDRTypeForNEON(EVT::v8i8); + addDRTypeForNEON(EVT::v4i16); + addDRTypeForNEON(EVT::v2i32); + addDRTypeForNEON(EVT::v1i64); + + addQRTypeForNEON(EVT::v4f32); + addQRTypeForNEON(EVT::v2f64); + addQRTypeForNEON(EVT::v16i8); + addQRTypeForNEON(EVT::v8i16); + addQRTypeForNEON(EVT::v4i32); + addQRTypeForNEON(EVT::v2i64); setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); setTargetDAGCombine(ISD::SHL); @@ -238,137 +238,137 @@ ARMTargetLowering::ARMTargetLowering(TargetMachine &TM) computeRegisterProperties(); // ARM does not have f32 extending load. - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); // ARM does not have i1 sign extending load. - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); // ARM supports all 4 flavors of integer indexed load / store. if (!Subtarget->isThumb1Only()) { for (unsigned im = (unsigned)ISD::PRE_INC; im != (unsigned)ISD::LAST_INDEXED_MODE; ++im) { - setIndexedLoadAction(im, MVT::i1, Legal); - setIndexedLoadAction(im, MVT::i8, Legal); - setIndexedLoadAction(im, MVT::i16, Legal); - setIndexedLoadAction(im, MVT::i32, Legal); - setIndexedStoreAction(im, MVT::i1, Legal); - setIndexedStoreAction(im, MVT::i8, Legal); - setIndexedStoreAction(im, MVT::i16, Legal); - setIndexedStoreAction(im, MVT::i32, Legal); + setIndexedLoadAction(im, EVT::i1, Legal); + setIndexedLoadAction(im, EVT::i8, Legal); + setIndexedLoadAction(im, EVT::i16, Legal); + setIndexedLoadAction(im, EVT::i32, Legal); + setIndexedStoreAction(im, EVT::i1, Legal); + setIndexedStoreAction(im, EVT::i8, Legal); + setIndexedStoreAction(im, EVT::i16, Legal); + setIndexedStoreAction(im, EVT::i32, Legal); } } // i64 operation support. if (Subtarget->isThumb1Only()) { - setOperationAction(ISD::MUL, MVT::i64, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); - setOperationAction(ISD::MULHS, MVT::i32, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::MUL, EVT::i64, Expand); + setOperationAction(ISD::MULHU, EVT::i32, Expand); + setOperationAction(ISD::MULHS, EVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); } else { - setOperationAction(ISD::MUL, MVT::i64, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); + setOperationAction(ISD::MUL, EVT::i64, Expand); + setOperationAction(ISD::MULHU, EVT::i32, Expand); if (!Subtarget->hasV6Ops()) - setOperationAction(ISD::MULHS, MVT::i32, Expand); + setOperationAction(ISD::MULHS, EVT::i32, Expand); } - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL, MVT::i64, Custom); - setOperationAction(ISD::SRA, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL, EVT::i64, Custom); + setOperationAction(ISD::SRA, EVT::i64, Custom); // ARM does not have ROTL. - setOperationAction(ISD::ROTL, MVT::i32, Expand); - setOperationAction(ISD::CTTZ, MVT::i32, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Expand); + setOperationAction(ISD::ROTL, EVT::i32, Expand); + setOperationAction(ISD::CTTZ, EVT::i32, Expand); + setOperationAction(ISD::CTPOP, EVT::i32, Expand); if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) - setOperationAction(ISD::CTLZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, EVT::i32, Expand); // Only ARMv6 has BSWAP. if (!Subtarget->hasV6Ops()) - setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, EVT::i32, Expand); // These are expanded into libcalls. - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + setOperationAction(ISD::SDIV, EVT::i32, Expand); + setOperationAction(ISD::UDIV, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + setOperationAction(ISD::SDIVREM, EVT::i32, Expand); + setOperationAction(ISD::UDIVREM, EVT::i32, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::GLOBAL_OFFSET_TABLE, MVT::i32, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); + setOperationAction(ISD::ConstantPool, EVT::i32, Custom); + setOperationAction(ISD::GLOBAL_OFFSET_TABLE, EVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom); // Use the default implementation. - setOperationAction(ISD::VASTART, MVT::Other, Custom); - setOperationAction(ISD::VAARG, MVT::Other, Expand); - setOperationAction(ISD::VACOPY, MVT::Other, Expand); - setOperationAction(ISD::VAEND, MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::VASTART, EVT::Other, Custom); + setOperationAction(ISD::VAARG, EVT::Other, Expand); + setOperationAction(ISD::VACOPY, EVT::Other, Expand); + setOperationAction(ISD::VAEND, EVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); if (Subtarget->isThumb()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom); else - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand); + setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand); if (!Subtarget->hasV6Ops() && !Subtarget->isThumb2()) { - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand); } - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) // Turn f64->i64 into FMRRD, i64 -> f64 to FMDRR iff target supports vfp2. - setOperationAction(ISD::BIT_CONVERT, MVT::i64, Custom); + setOperationAction(ISD::BIT_CONVERT, EVT::i64, Custom); // We want to custom lower some of our intrinsics. - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); - setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); - - setOperationAction(ISD::SETCC, MVT::i32, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Expand); - setOperationAction(ISD::SETCC, MVT::f64, Expand); - setOperationAction(ISD::SELECT, MVT::i32, Expand); - setOperationAction(ISD::SELECT, MVT::f32, Expand); - setOperationAction(ISD::SELECT, MVT::f64, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); - - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::i32, Custom); - setOperationAction(ISD::BR_CC, MVT::f32, Custom); - setOperationAction(ISD::BR_CC, MVT::f64, Custom); - setOperationAction(ISD::BR_JT, MVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_W_CHAIN, EVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_VOID, EVT::Other, Custom); + + setOperationAction(ISD::SETCC, EVT::i32, Expand); + setOperationAction(ISD::SETCC, EVT::f32, Expand); + setOperationAction(ISD::SETCC, EVT::f64, Expand); + setOperationAction(ISD::SELECT, EVT::i32, Expand); + setOperationAction(ISD::SELECT, EVT::f32, Expand); + setOperationAction(ISD::SELECT, EVT::f64, Expand); + setOperationAction(ISD::SELECT_CC, EVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f64, Custom); + + setOperationAction(ISD::BRCOND, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::i32, Custom); + setOperationAction(ISD::BR_CC, EVT::f32, Custom); + setOperationAction(ISD::BR_CC, EVT::f64, Custom); + setOperationAction(ISD::BR_JT, EVT::Other, Custom); // We don't support sin/cos/fmod/copysign/pow - setOperationAction(ISD::FSIN, MVT::f64, Expand); - setOperationAction(ISD::FSIN, MVT::f32, Expand); - setOperationAction(ISD::FCOS, MVT::f32, Expand); - setOperationAction(ISD::FCOS, MVT::f64, Expand); - setOperationAction(ISD::FREM, MVT::f64, Expand); - setOperationAction(ISD::FREM, MVT::f32, Expand); + setOperationAction(ISD::FSIN, EVT::f64, Expand); + setOperationAction(ISD::FSIN, EVT::f32, Expand); + setOperationAction(ISD::FCOS, EVT::f32, Expand); + setOperationAction(ISD::FCOS, EVT::f64, Expand); + setOperationAction(ISD::FREM, EVT::f64, Expand); + setOperationAction(ISD::FREM, EVT::f32, Expand); if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom); } - setOperationAction(ISD::FPOW, MVT::f64, Expand); - setOperationAction(ISD::FPOW, MVT::f32, Expand); + setOperationAction(ISD::FPOW, EVT::f64, Expand); + setOperationAction(ISD::FPOW, EVT::f32, Expand); // int <-> fp are custom expanded into bit_convert + ARMISD ops. if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) { - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom); } // We have target-specific dag combine patterns for the following nodes: @@ -549,7 +549,7 @@ static bool FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, #include "ARMGenCallingConv.inc" // APCS f64 is in register pairs, possibly split to stack -static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool f64AssignAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 }; @@ -579,20 +579,20 @@ static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, return true; } -static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) return false; - if (LocVT == MVT::v2f64 && + if (LocVT == EVT::v2f64 && !f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) return false; return true; // we handled it } // AAPCS f64 is in aligned register pairs -static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool f64AssignAAPCS(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State, bool CanFail) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; @@ -622,19 +622,19 @@ static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT, return true; } -static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true)) return false; - if (LocVT == MVT::v2f64 && + if (LocVT == EVT::v2f64 && !f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false)) return false; return true; // we handled it } -static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool f64RetAssign(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, CCState &State) { static const unsigned HiRegList[] = { ARM::R0, ARM::R2 }; static const unsigned LoRegList[] = { ARM::R1, ARM::R3 }; @@ -654,18 +654,18 @@ static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT, return true; } -static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) return false; - if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) + if (LocVT == EVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State)) return false; return true; // we handled it } -static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -725,33 +725,33 @@ ARMTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, SDValue Val; if (VA.needsCustom()) { // Handle f64 or half of a v2f64. - SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, + SDValue Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag); Chain = Lo.getValue(1); InFlag = Lo.getValue(2); VA = RVLocs[++i]; // skip ahead to next loc - SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, + SDValue Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag); Chain = Hi.getValue(1); InFlag = Hi.getValue(2); - Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); + Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi); - if (VA.getLocVT() == MVT::v2f64) { - SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); - Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, - DAG.getConstant(0, MVT::i32)); + if (VA.getLocVT() == EVT::v2f64) { + SDValue Vec = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64); + Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val, + DAG.getConstant(0, EVT::i32)); VA = RVLocs[++i]; // skip ahead to next loc - Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); + Lo = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag); Chain = Lo.getValue(1); InFlag = Lo.getValue(2); VA = RVLocs[++i]; // skip ahead to next loc - Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), MVT::i32, InFlag); + Hi = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), EVT::i32, InFlag); Chain = Hi.getValue(1); InFlag = Hi.getValue(2); - Val = DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); - Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Vec, Val, - DAG.getConstant(1, MVT::i32)); + Val = DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi); + Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Vec, Val, + DAG.getConstant(1, EVT::i32)); } } else { Val = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getLocVT(), @@ -784,7 +784,7 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, DebugLoc dl) { - SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), /*AlwaysInline=*/false, NULL, 0, NULL, 0); } @@ -815,7 +815,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, ISD::ArgFlagsTy Flags) { SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, - DAG.getVTList(MVT::i32, MVT::i32), Arg); + DAG.getVTList(EVT::i32, EVT::i32), Arg); RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd)); if (NextVA.isRegLoc()) @@ -858,7 +858,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // These operations are automatically eliminated by the prolog/epilog pass Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); - SDValue StackPtr = DAG.getRegister(ARM::SP, MVT::i32); + SDValue StackPtr = DAG.getRegister(ARM::SP, EVT::i32); RegsToPassVector RegsToPass; SmallVector<SDValue, 8> MemOpChains; @@ -892,11 +892,11 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // f64 and v2f64 might be passed in i32 pairs and must be split into pieces if (VA.needsCustom()) { - if (VA.getLocVT() == MVT::v2f64) { - SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, - DAG.getConstant(0, MVT::i32)); - SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, - DAG.getConstant(1, MVT::i32)); + if (VA.getLocVT() == EVT::v2f64) { + SDValue Op0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg, + DAG.getConstant(0, EVT::i32)); + SDValue Op1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg, + DAG.getConstant(1, EVT::i32)); PassF64ArgInRegs(dl, DAG, Chain, Op0, RegsToPass, VA, ArgLocs[++i], StackPtr, MemOpChains, Flags); @@ -930,7 +930,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain @@ -962,10 +962,10 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMPCLabelIndex, ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, NULL, 0); - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, dl, getPointerTy(), Callee, PICLabel); } else @@ -981,10 +981,10 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, ARMConstantPoolValue *CPV = new ARMConstantPoolValue(Sym, ARMPCLabelIndex, ARMCP::CPStub, 4); SDValue CPAddr = DAG.getTargetConstantPool(CPV, getPointerTy(), 4); - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), CPAddr, NULL, 0); - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); Callee = DAG.getNode(ARMISD::PIC_ADD, dl, getPointerTy(), Callee, PICLabel); } else @@ -1005,7 +1005,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } if (CallOpc == ARMISD::CALL_NOLINK && !Subtarget->isThumb1Only()) { // implicit def LR - LR mustn't be allocated as GRP:$dst of CALL_NOLINK - Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(MVT::i32),InFlag); + Chain = DAG.getCopyToReg(Chain, dl, ARM::LR, DAG.getUNDEF(EVT::i32),InFlag); InFlag = Chain.getValue(1); } @@ -1022,7 +1022,7 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -1082,12 +1082,12 @@ ARMTargetLowering::LowerReturn(SDValue Chain, } if (VA.needsCustom()) { - if (VA.getLocVT() == MVT::v2f64) { + if (VA.getLocVT() == EVT::v2f64) { // Extract the first half and return it in two registers. - SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, - DAG.getConstant(0, MVT::i32)); + SDValue Half = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg, + DAG.getConstant(0, EVT::i32)); SDValue HalfGPRs = DAG.getNode(ARMISD::FMRRD, dl, - DAG.getVTList(MVT::i32, MVT::i32), Half); + DAG.getVTList(EVT::i32, EVT::i32), Half); Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), HalfGPRs, Flag); Flag = Chain.getValue(1); @@ -1098,13 +1098,13 @@ ARMTargetLowering::LowerReturn(SDValue Chain, VA = RVLocs[++i]; // skip ahead to next loc // Extract the 2nd half and fall through to handle it as an f64 value. - Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Arg, - DAG.getConstant(1, MVT::i32)); + Arg = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Arg, + DAG.getConstant(1, EVT::i32)); } // Legalize ret f64 -> ret 2 x i32. We always have fmrrd if f64 is // available. SDValue fmrrd = DAG.getNode(ARMISD::FMRRD, dl, - DAG.getVTList(MVT::i32, MVT::i32), &Arg, 1); + DAG.getVTList(EVT::i32, EVT::i32), &Arg, 1); Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), fmrrd, Flag); Flag = Chain.getValue(1); VA = RVLocs[++i]; // skip ahead to next loc @@ -1120,9 +1120,9 @@ ARMTargetLowering::LowerReturn(SDValue Chain, SDValue result; if (Flag.getNode()) - result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain, Flag); else // Return Void - result = DAG.getNode(ARMISD::RET_FLAG, dl, MVT::Other, Chain); + result = DAG.getNode(ARMISD::RET_FLAG, dl, EVT::Other, Chain); return result; } @@ -1134,7 +1134,7 @@ ARMTargetLowering::LowerReturn(SDValue Chain, // be used to form addressing mode. These wrapped nodes will be selected // into MOVi. static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); // FIXME there is no actual debug info here DebugLoc dl = Op.getDebugLoc(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); @@ -1145,7 +1145,7 @@ static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) { else Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment()); - return DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Res); + return DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Res); } // Lower ISD::GlobalTLSAddress using the "general dynamic" model @@ -1153,17 +1153,17 @@ SDValue ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA, SelectionDAG &DAG) { DebugLoc dl = GA->getDebugLoc(); - MVT PtrVT = getPointerTy(); + EVT PtrVT = getPointerTy(); unsigned char PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, PCAdj, "tlsgd", true); SDValue Argument = DAG.getTargetConstantPool(CPV, PtrVT, 4); - Argument = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Argument); + Argument = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Argument); Argument = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Argument, NULL, 0); SDValue Chain = Argument.getValue(1); - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); Argument = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Argument, PICLabel); // call __tls_get_addr. @@ -1189,7 +1189,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, DebugLoc dl = GA->getDebugLoc(); SDValue Offset; SDValue Chain = DAG.getEntryNode(); - MVT PtrVT = getPointerTy(); + EVT PtrVT = getPointerTy(); // Get the Thread Pointer SDValue ThreadPointer = DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); @@ -1200,11 +1200,11 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, new ARMConstantPoolValue(GA->getGlobal(), ARMPCLabelIndex, ARMCP::CPValue, PCAdj, "gottpoff", true); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); - Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); + Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); Chain = Offset.getValue(1); - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); Offset = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Offset, PICLabel); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); @@ -1213,7 +1213,7 @@ ARMTargetLowering::LowerToTLSExecModels(GlobalAddressSDNode *GA, ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, "tpoff"); Offset = DAG.getTargetConstantPool(CPV, PtrVT, 4); - Offset = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, Offset); + Offset = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, Offset); Offset = DAG.getLoad(PtrVT, dl, Chain, Offset, NULL, 0); } @@ -1238,7 +1238,7 @@ ARMTargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = getPointerTy(); + EVT PtrVT = getPointerTy(); DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); @@ -1247,7 +1247,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, ARMCP::CPValue, UseGOTOFF ? "GOTOFF":"GOT"); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); @@ -1258,7 +1258,7 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, return Result; } else { SDValue CPAddr = DAG.getTargetConstantPool(GV, PtrVT, 4); - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); } } @@ -1276,7 +1276,7 @@ static bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) { SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = getPointerTy(); + EVT PtrVT = getPointerTy(); DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); Reloc::Model RelocM = getTargetMachine().getRelocationModel(); @@ -1293,13 +1293,13 @@ SDValue ARMTargetLowering::LowerGlobalAddressDarwin(SDValue Op, Kind, PCAdj); CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); } - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); SDValue Chain = Result.getValue(1); if (RelocM == Reloc::PIC_) { - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); Result = DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } if (IsIndirect) @@ -1312,23 +1312,23 @@ SDValue ARMTargetLowering::LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG){ assert(Subtarget->isTargetELF() && "GLOBAL OFFSET TABLE not implemented for non-ELF targets"); - MVT PtrVT = getPointerTy(); + EVT PtrVT = getPointerTy(); DebugLoc dl = Op.getDebugLoc(); unsigned PCAdj = Subtarget->isThumb() ? 4 : 8; ARMConstantPoolValue *CPV = new ARMConstantPoolValue("_GLOBAL_OFFSET_TABLE_", ARMPCLabelIndex, ARMCP::CPValue, PCAdj); SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, 4); - CPAddr = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, CPAddr); + CPAddr = DAG.getNode(ARMISD::Wrapper, dl, EVT::i32, CPAddr); SDValue Result = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), CPAddr, NULL, 0); - SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, MVT::i32); + SDValue PICLabel = DAG.getConstant(ARMPCLabelIndex++, EVT::i32); return DAG.getNode(ARMISD::PIC_ADD, dl, PtrVT, Result, PICLabel); } static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG, unsigned Opcode) { SDNode *Node = Op.getNode(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); DebugLoc dl = Op.getDebugLoc(); if (!VT.is64BitVector()) @@ -1342,7 +1342,7 @@ static SDValue LowerNeonVLDIntrinsic(SDValue Op, SelectionDAG &DAG, static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG, unsigned Opcode, unsigned NumVecs) { SDNode *Node = Op.getNode(); - MVT VT = Node->getOperand(3).getValueType(); + EVT VT = Node->getOperand(3).getValueType(); DebugLoc dl = Op.getDebugLoc(); if (!VT.is64BitVector()) @@ -1353,7 +1353,7 @@ static SDValue LowerNeonVSTIntrinsic(SDValue Op, SelectionDAG &DAG, Ops.push_back(Node->getOperand(2)); for (unsigned N = 0; N < NumVecs; ++N) Ops.push_back(Node->getOperand(N + 3)); - return DAG.getNode(Opcode, dl, MVT::Other, Ops.data(), Ops.size()); + return DAG.getNode(Opcode, dl, EVT::Other, Ops.data(), Ops.size()); } SDValue @@ -1389,11 +1389,11 @@ ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { switch (IntNo) { default: return SDValue(); // Don't custom lower most intrinsics. case Intrinsic::arm_thread_pointer: { - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); return DAG.getNode(ARMISD::THREAD_POINTER, dl, PtrVT); } case Intrinsic::eh_sjlj_setjmp: - return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, MVT::i32, Op.getOperand(1)); + return DAG.getNode(ARMISD::EH_SJLJ_SETJMP, dl, EVT::i32, Op.getOperand(1)); } } @@ -1402,7 +1402,7 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. DebugLoc dl = Op.getDebugLoc(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); @@ -1412,7 +1412,7 @@ SDValue ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDValue Chain = Op.getOperand(0); SDValue Size = Op.getOperand(1); SDValue Align = Op.getOperand(2); @@ -1445,7 +1445,7 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { Size = DAG.getNode(ISD::SUB, dl, VT, DAG.getConstant(0, VT), Size); } - SDVTList VTList = DAG.getVTList(VT, MVT::Other); + SDVTList VTList = DAG.getVTList(VT, EVT::Other); SDValue Ops1[] = { Chain, Size, Align }; SDValue Res = DAG.getNode(ARMISD::DYN_ALLOC, dl, VTList, Ops1, 3); Chain = Res.getValue(1); @@ -1470,7 +1470,7 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, // Transform the arguments stored in physical registers into virtual ones. unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); - SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); + SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32); SDValue ArgValue2; if (NextVA.isMemLoc()) { @@ -1480,13 +1480,13 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA, // Create load node to retrieve arguments from the stack. SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); - ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0); + ArgValue2 = DAG.getLoad(EVT::i32, dl, Root, FIN, NULL, 0); } else { Reg = MF.addLiveIn(NextVA.getLocReg(), RC); - ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32); + ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, EVT::i32); } - return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, ArgValue, ArgValue2); + return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, ArgValue, ArgValue2); } SDValue @@ -1517,24 +1517,24 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, // Arguments stored in registers. if (VA.isRegLoc()) { - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); SDValue ArgValue; if (VA.needsCustom()) { // f64 and vector types are split up into multiple registers or // combinations of registers and stack slots. - RegVT = MVT::i32; + RegVT = EVT::i32; - if (VA.getLocVT() == MVT::v2f64) { + if (VA.getLocVT() == EVT::v2f64) { SDValue ArgValue1 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); VA = ArgLocs[++i]; // skip ahead to next loc SDValue ArgValue2 = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); - ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64); - ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, + ArgValue = DAG.getNode(ISD::UNDEF, dl, EVT::v2f64); + ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, ArgValue, ArgValue1, DAG.getIntPtrConstant(0)); - ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, + ArgValue = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, ArgValue, ArgValue2, DAG.getIntPtrConstant(1)); } else ArgValue = GetF64FormalArgument(VA, ArgLocs[++i], Chain, DAG, dl); @@ -1542,13 +1542,13 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, } else { TargetRegisterClass *RC; - if (RegVT == MVT::f32) + if (RegVT == EVT::f32) RC = ARM::SPRRegisterClass; - else if (RegVT == MVT::f64) + else if (RegVT == EVT::f64) RC = ARM::DPRRegisterClass; - else if (RegVT == MVT::v2f64) + else if (RegVT == EVT::v2f64) RC = ARM::QPRRegisterClass; - else if (RegVT == MVT::i32) + else if (RegVT == EVT::i32) RC = (AFI->isThumb1OnlyFunction() ? ARM::tGPRRegisterClass : ARM::GPRRegisterClass); else @@ -1586,7 +1586,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, // sanity check assert(VA.isMemLoc()); - assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered"); + assert(VA.getValVT() != EVT::i64 && "i64 should already be lowered"); unsigned ArgSize = VA.getLocVT().getSizeInBits()/8; int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset()); @@ -1629,14 +1629,14 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain, RC = ARM::GPRRegisterClass; unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getConstant(4, getPointerTy())); } if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOps[0], MemOps.size()); } else // This will point to the next argument passed via stack. @@ -1682,28 +1682,28 @@ static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, case ISD::SETGE: if (isLegalCmpImmediate(C-1, isThumb1Only)) { CC = (CC == ISD::SETLT) ? ISD::SETLE : ISD::SETGT; - RHS = DAG.getConstant(C-1, MVT::i32); + RHS = DAG.getConstant(C-1, EVT::i32); } break; case ISD::SETULT: case ISD::SETUGE: if (C > 0 && isLegalCmpImmediate(C-1, isThumb1Only)) { CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; - RHS = DAG.getConstant(C-1, MVT::i32); + RHS = DAG.getConstant(C-1, EVT::i32); } break; case ISD::SETLE: case ISD::SETGT: if (isLegalCmpImmediate(C+1, isThumb1Only)) { CC = (CC == ISD::SETLE) ? ISD::SETLT : ISD::SETGE; - RHS = DAG.getConstant(C+1, MVT::i32); + RHS = DAG.getConstant(C+1, EVT::i32); } break; case ISD::SETULE: case ISD::SETUGT: if (C < 0xffffffff && isLegalCmpImmediate(C+1, isThumb1Only)) { CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; - RHS = DAG.getConstant(C+1, MVT::i32); + RHS = DAG.getConstant(C+1, EVT::i32); } break; } @@ -1722,8 +1722,8 @@ static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC, CompareType = ARMISD::CMPZ; break; } - ARMCC = DAG.getConstant(CondCode, MVT::i32); - return DAG.getNode(CompareType, dl, MVT::Flag, LHS, RHS); + ARMCC = DAG.getConstant(CondCode, EVT::i32); + return DAG.getNode(CompareType, dl, EVT::Flag, LHS, RHS); } /// Returns a appropriate VFP CMP (fcmp{s|d}+fmstat) for the given operands. @@ -1731,15 +1731,15 @@ static SDValue getVFPCmp(SDValue LHS, SDValue RHS, SelectionDAG &DAG, DebugLoc dl) { SDValue Cmp; if (!isFloatingPointZero(RHS)) - Cmp = DAG.getNode(ARMISD::CMPFP, dl, MVT::Flag, LHS, RHS); + Cmp = DAG.getNode(ARMISD::CMPFP, dl, EVT::Flag, LHS, RHS); else - Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, MVT::Flag, LHS); - return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Flag, Cmp); + Cmp = DAG.getNode(ARMISD::CMPFPw0, dl, EVT::Flag, LHS); + return DAG.getNode(ARMISD::FMSTAT, dl, EVT::Flag, Cmp); } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const ARMSubtarget *ST) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue LHS = Op.getOperand(0); SDValue RHS = Op.getOperand(1); ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); @@ -1747,9 +1747,9 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, SDValue FalseVal = Op.getOperand(3); DebugLoc dl = Op.getDebugLoc(); - if (LHS.getValueType() == MVT::i32) { + if (LHS.getValueType() == EVT::i32) { SDValue ARMCC; - SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32); SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl); return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR,Cmp); } @@ -1758,13 +1758,13 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, if (FPCCToARMCC(CC, CondCode, CondCode2)) std::swap(TrueVal, FalseVal); - SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); - SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32); SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); SDValue Result = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMCC, CCR, Cmp); if (CondCode2 != ARMCC::AL) { - SDValue ARMCC2 = DAG.getConstant(CondCode2, MVT::i32); + SDValue ARMCC2 = DAG.getConstant(CondCode2, EVT::i32); // FIXME: Needs another CMP because flag can have but one use. SDValue Cmp2 = getVFPCmp(LHS, RHS, DAG, dl); Result = DAG.getNode(ARMISD::CMOV, dl, VT, @@ -1782,28 +1782,28 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG, SDValue Dest = Op.getOperand(4); DebugLoc dl = Op.getDebugLoc(); - if (LHS.getValueType() == MVT::i32) { + if (LHS.getValueType() == EVT::i32) { SDValue ARMCC; - SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32); SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMCC, DAG, ST->isThumb1Only(), dl); - return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, + return DAG.getNode(ARMISD::BRCOND, dl, EVT::Other, Chain, Dest, ARMCC, CCR,Cmp); } - assert(LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64); + assert(LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64); ARMCC::CondCodes CondCode, CondCode2; if (FPCCToARMCC(CC, CondCode, CondCode2)) // Swap the LHS/RHS of the comparison if needed. std::swap(LHS, RHS); SDValue Cmp = getVFPCmp(LHS, RHS, DAG, dl); - SDValue ARMCC = DAG.getConstant(CondCode, MVT::i32); - SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); - SDVTList VTList = DAG.getVTList(MVT::Other, MVT::Flag); + SDValue ARMCC = DAG.getConstant(CondCode, EVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32); + SDVTList VTList = DAG.getVTList(EVT::Other, EVT::Flag); SDValue Ops[] = { Chain, Dest, ARMCC, CCR, Cmp }; SDValue Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); if (CondCode2 != ARMCC::AL) { - ARMCC = DAG.getConstant(CondCode2, MVT::i32); + ARMCC = DAG.getConstant(CondCode2, EVT::i32); SDValue Ops[] = { Res, Dest, ARMCC, CCR, Res.getValue(1) }; Res = DAG.getNode(ARMISD::BRCOND, dl, VTList, Ops, 5); } @@ -1816,12 +1816,12 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { SDValue Index = Op.getOperand(2); DebugLoc dl = Op.getDebugLoc(); - MVT PTy = getPointerTy(); + EVT PTy = getPointerTy(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Table); ARMFunctionInfo *AFI = DAG.getMachineFunction().getInfo<ARMFunctionInfo>(); SDValue UId = DAG.getConstant(AFI->createJumpTableUId(), PTy); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PTy); - Table = DAG.getNode(ARMISD::WrapperJT, dl, MVT::i32, JTI, UId); + Table = DAG.getNode(ARMISD::WrapperJT, dl, EVT::i32, JTI, UId); Index = DAG.getNode(ISD::MUL, dl, PTy, Index, DAG.getConstant(4, PTy)); SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); if (Subtarget->isThumb2()) { @@ -1829,18 +1829,18 @@ SDValue ARMTargetLowering::LowerBR_JT(SDValue Op, SelectionDAG &DAG) { // which does another jump to the destination. This also makes it easier // to translate it to TBB / TBH later. // FIXME: This might not work if the function is extremely large. - return DAG.getNode(ARMISD::BR2_JT, dl, MVT::Other, Chain, + return DAG.getNode(ARMISD::BR2_JT, dl, EVT::Other, Chain, Addr, Op.getOperand(2), JTI, UId); } if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { - Addr = DAG.getLoad((MVT)MVT::i32, dl, Chain, Addr, NULL, 0); + Addr = DAG.getLoad((EVT)EVT::i32, dl, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, Table); - return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); + return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId); } else { Addr = DAG.getLoad(PTy, dl, Chain, Addr, NULL, 0); Chain = Addr.getValue(1); - return DAG.getNode(ARMISD::BR_JT, dl, MVT::Other, Chain, Addr, JTI, UId); + return DAG.getNode(ARMISD::BR_JT, dl, EVT::Other, Chain, Addr, JTI, UId); } } @@ -1848,17 +1848,17 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::FP_TO_SINT ? ARMISD::FTOSI : ARMISD::FTOUI; - Op = DAG.getNode(Opc, dl, MVT::f32, Op.getOperand(0)); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); + Op = DAG.getNode(Opc, dl, EVT::f32, Op.getOperand(0)); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op); } static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); unsigned Opc = Op.getOpcode() == ISD::SINT_TO_FP ? ARMISD::SITOF : ARMISD::UITOF; - Op = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); + Op = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0)); return DAG.getNode(Opc, dl, VT, Op); } @@ -1867,19 +1867,19 @@ static SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { SDValue Tmp0 = Op.getOperand(0); SDValue Tmp1 = Op.getOperand(1); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); - MVT SrcVT = Tmp1.getValueType(); + EVT VT = Op.getValueType(); + EVT SrcVT = Tmp1.getValueType(); SDValue AbsVal = DAG.getNode(ISD::FABS, dl, VT, Tmp0); SDValue Cmp = getVFPCmp(Tmp1, DAG.getConstantFP(0.0, SrcVT), DAG, dl); - SDValue ARMCC = DAG.getConstant(ARMCC::LT, MVT::i32); - SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); + SDValue ARMCC = DAG.getConstant(ARMCC::LT, EVT::i32); + SDValue CCR = DAG.getRegister(ARM::CPSR, EVT::i32); return DAG.getNode(ARMISD::CNEG, dl, VT, AbsVal, AbsVal, ARMCC, CCR, Cmp); } SDValue ARMTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned FrameReg = (Subtarget->isThumb() || Subtarget->isTargetDarwin()) @@ -1914,7 +1914,7 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, unsigned BytesLeft = SizeVal & 3; unsigned NumMemOps = SizeVal >> 2; unsigned EmittedNumMemOps = 0; - MVT VT = MVT::i32; + EVT VT = EVT::i32; unsigned VTSize = 4; unsigned i = 0; const unsigned MAX_LOADS_IN_LDM = 6; @@ -1929,23 +1929,23 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { Loads[i] = DAG.getLoad(VT, dl, Chain, - DAG.getNode(ISD::ADD, dl, MVT::i32, Src, - DAG.getConstant(SrcOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, EVT::i32, Src, + DAG.getConstant(SrcOff, EVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); SrcOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i); for (i = 0; i < MAX_LOADS_IN_LDM && EmittedNumMemOps + i < NumMemOps; ++i) { TFOps[i] = DAG.getStore(Chain, dl, Loads[i], - DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, - DAG.getConstant(DstOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, EVT::i32, Dst, + DAG.getConstant(DstOff, EVT::i32)), DstSV, DstSVOff + DstOff); DstOff += VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i); EmittedNumMemOps += i; } @@ -1958,69 +1958,69 @@ ARMTargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, i = 0; while (BytesLeft) { if (BytesLeft >= 2) { - VT = MVT::i16; + VT = EVT::i16; VTSize = 2; } else { - VT = MVT::i8; + VT = EVT::i8; VTSize = 1; } Loads[i] = DAG.getLoad(VT, dl, Chain, - DAG.getNode(ISD::ADD, dl, MVT::i32, Src, - DAG.getConstant(SrcOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, EVT::i32, Src, + DAG.getConstant(SrcOff, EVT::i32)), SrcSV, SrcSVOff + SrcOff); TFOps[i] = Loads[i].getValue(1); ++i; SrcOff += VTSize; BytesLeft -= VTSize; } - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i); i = 0; BytesLeft = BytesLeftSave; while (BytesLeft) { if (BytesLeft >= 2) { - VT = MVT::i16; + VT = EVT::i16; VTSize = 2; } else { - VT = MVT::i8; + VT = EVT::i8; VTSize = 1; } TFOps[i] = DAG.getStore(Chain, dl, Loads[i], - DAG.getNode(ISD::ADD, dl, MVT::i32, Dst, - DAG.getConstant(DstOff, MVT::i32)), + DAG.getNode(ISD::ADD, dl, EVT::i32, Dst, + DAG.getConstant(DstOff, EVT::i32)), DstSV, DstSVOff + DstOff); ++i; DstOff += VTSize; BytesLeft -= VTSize; } - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &TFOps[0], i); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &TFOps[0], i); } static SDValue ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) { SDValue Op = N->getOperand(0); DebugLoc dl = N->getDebugLoc(); - if (N->getValueType(0) == MVT::f64) { + if (N->getValueType(0) == EVT::f64) { // Turn i64->f64 into FMDRR. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, - DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Op, - DAG.getConstant(1, MVT::i32)); - return DAG.getNode(ARMISD::FMDRR, dl, MVT::f64, Lo, Hi); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op, + DAG.getConstant(0, EVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op, + DAG.getConstant(1, EVT::i32)); + return DAG.getNode(ARMISD::FMDRR, dl, EVT::f64, Lo, Hi); } // Turn f64->i64 into FMRRD. SDValue Cvt = DAG.getNode(ARMISD::FMRRD, dl, - DAG.getVTList(MVT::i32, MVT::i32), &Op, 1); + DAG.getVTList(EVT::i32, EVT::i32), &Op, 1); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); + return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Cvt, Cvt.getValue(1)); } /// getZeroVector - Returns a vector of specified type with all zero elements. /// -static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { +static SDValue getZeroVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); // Zero vectors are used to represent vector negation and in those cases @@ -2030,35 +2030,35 @@ static SDValue getZeroVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { // the future, always build zero vectors as <4 x i32> or <2 x i32> bitcasted // to their dest type. This ensures they get CSE'd. SDValue Vec; - SDValue Cst = DAG.getTargetConstant(0, MVT::i32); + SDValue Cst = DAG.getTargetConstant(0, EVT::i32); if (VT.getSizeInBits() == 64) - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst); else - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } /// getOnesVector - Returns a vector of specified type with all bits set. /// -static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { +static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. SDValue Vec; - SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); + SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32); if (VT.getSizeInBits() == 64) - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst); else - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); DebugLoc dl = N->getDebugLoc(); // Lower vector shifts on NEON to use VSHL. @@ -2068,7 +2068,7 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, // Left shifts translate directly to the vshiftu intrinsic. if (N->getOpcode() == ISD::SHL) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::arm_neon_vshiftu, MVT::i32), + DAG.getConstant(Intrinsic::arm_neon_vshiftu, EVT::i32), N->getOperand(0), N->getOperand(1)); assert((N->getOpcode() == ISD::SRA || @@ -2077,7 +2077,7 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, // NEON uses the same intrinsics for both left and right shifts. For // right shifts, the shift amounts are negative, so negate the vector of // shift amounts. - MVT ShiftVT = N->getOperand(1).getValueType(); + EVT ShiftVT = N->getOperand(1).getValueType(); SDValue NegatedCount = DAG.getNode(ISD::SUB, dl, ShiftVT, getZeroVector(ShiftVT, DAG, dl), N->getOperand(1)); @@ -2085,11 +2085,11 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, Intrinsic::arm_neon_vshifts : Intrinsic::arm_neon_vshiftu); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(vshiftInt, MVT::i32), + DAG.getConstant(vshiftInt, EVT::i32), N->getOperand(0), NegatedCount); } - assert(VT == MVT::i64 && + assert(VT == EVT::i64 && (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) && "Unknown shift to lower!"); @@ -2102,21 +2102,21 @@ static SDValue LowerShift(SDNode *N, SelectionDAG &DAG, if (ST->isThumb1Only()) return SDValue(); // Okay, we have a 64-bit SRA or SRL of 1. Lower this to an RRX expr. - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), - DAG.getConstant(0, MVT::i32)); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(0), - DAG.getConstant(1, MVT::i32)); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0), + DAG.getConstant(0, EVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(0), + DAG.getConstant(1, EVT::i32)); // First, build a SRA_FLAG/SRL_FLAG op, which shifts the top part by one and // captures the result into a carry flag. unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG; - Hi = DAG.getNode(Opc, dl, DAG.getVTList(MVT::i32, MVT::Flag), &Hi, 1); + Hi = DAG.getNode(Opc, dl, DAG.getVTList(EVT::i32, EVT::Flag), &Hi, 1); // The low part is an ARMISD::RRX operand, which shifts the carry in. - Lo = DAG.getNode(ARMISD::RRX, dl, MVT::i32, Lo, Hi.getValue(1)); + Lo = DAG.getNode(ARMISD::RRX, dl, EVT::i32, Lo, Hi.getValue(1)); // Merge the pieces into a single i64 value. - return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi); } static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { @@ -2128,7 +2128,7 @@ static SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); SDValue CC = Op.getOperand(2); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); DebugLoc dl = Op.getDebugLoc(); @@ -2227,13 +2227,13 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, case 8: // Any 1-byte value is OK. assert((SplatBits & ~0xff) == 0 && "one byte splat value is too big"); - return DAG.getTargetConstant(SplatBits, MVT::i8); + return DAG.getTargetConstant(SplatBits, EVT::i8); case 16: // NEON's 16-bit VMOV supports splat values where only one byte is nonzero. if ((SplatBits & ~0xff) == 0 || (SplatBits & ~0xff00) == 0) - return DAG.getTargetConstant(SplatBits, MVT::i16); + return DAG.getTargetConstant(SplatBits, EVT::i16); break; case 32: @@ -2245,15 +2245,15 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, (SplatBits & ~0xff00) == 0 || (SplatBits & ~0xff0000) == 0 || (SplatBits & ~0xff000000) == 0) - return DAG.getTargetConstant(SplatBits, MVT::i32); + return DAG.getTargetConstant(SplatBits, EVT::i32); if ((SplatBits & ~0xffff) == 0 && ((SplatBits | SplatUndef) & 0xff) == 0xff) - return DAG.getTargetConstant(SplatBits | 0xff, MVT::i32); + return DAG.getTargetConstant(SplatBits | 0xff, EVT::i32); if ((SplatBits & ~0xffffff) == 0 && ((SplatBits | SplatUndef) & 0xffff) == 0xffff) - return DAG.getTargetConstant(SplatBits | 0xffff, MVT::i32); + return DAG.getTargetConstant(SplatBits | 0xffff, EVT::i32); // Note: there are a few 32-bit splat values (specifically: 00ffff00, // ff000000, ff0000ff, and ffff00ff) that are valid for VMOV.I64 but not @@ -2273,7 +2273,7 @@ static SDValue isVMOVSplat(uint64_t SplatBits, uint64_t SplatUndef, return SDValue(); BitMask <<= 8; } - return DAG.getTargetConstant(Val, MVT::i64); + return DAG.getTargetConstant(Val, EVT::i64); } default: @@ -2311,7 +2311,7 @@ bool ARM::isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) { assert((BlockSize==16 || BlockSize==32 || BlockSize==64) && "Only possible block sizes for VREV are: 16, 32, 64"); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); unsigned NumElts = VT.getVectorNumElements(); unsigned EltSz = VT.getVectorElementType().getSizeInBits(); unsigned BlockElts = N->getMaskElt(0) + 1; @@ -2328,7 +2328,7 @@ bool ARM::isVREVMask(ShuffleVectorSDNode *N, unsigned BlockSize) { return true; } -static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { +static SDValue BuildSplat(SDValue Val, EVT VT, SelectionDAG &DAG, DebugLoc dl) { // Canonicalize all-zeros and all-ones vectors. ConstantSDNode *ConstVal = dyn_cast<ConstantSDNode>(Val.getNode()); if (ConstVal->isNullValue()) @@ -2336,22 +2336,22 @@ static SDValue BuildSplat(SDValue Val, MVT VT, SelectionDAG &DAG, DebugLoc dl) { if (ConstVal->isAllOnesValue()) return getOnesVector(VT, DAG, dl); - MVT CanonicalVT; + EVT CanonicalVT; if (VT.is64BitVector()) { switch (Val.getValueType().getSizeInBits()) { - case 8: CanonicalVT = MVT::v8i8; break; - case 16: CanonicalVT = MVT::v4i16; break; - case 32: CanonicalVT = MVT::v2i32; break; - case 64: CanonicalVT = MVT::v1i64; break; + case 8: CanonicalVT = EVT::v8i8; break; + case 16: CanonicalVT = EVT::v4i16; break; + case 32: CanonicalVT = EVT::v2i32; break; + case 64: CanonicalVT = EVT::v1i64; break; default: llvm_unreachable("unexpected splat element type"); break; } } else { assert(VT.is128BitVector() && "unknown splat vector size"); switch (Val.getValueType().getSizeInBits()) { - case 8: CanonicalVT = MVT::v16i8; break; - case 16: CanonicalVT = MVT::v8i16; break; - case 32: CanonicalVT = MVT::v4i32; break; - case 64: CanonicalVT = MVT::v2i64; break; + case 8: CanonicalVT = EVT::v16i8; break; + case 16: CanonicalVT = EVT::v8i16; break; + case 32: CanonicalVT = EVT::v4i32; break; + case 64: CanonicalVT = EVT::v2i64; break; default: llvm_unreachable("unexpected splat element type"); break; } } @@ -2370,7 +2370,7 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode()); assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR"); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); APInt SplatBits, SplatUndef; unsigned SplatBitSize; @@ -2411,14 +2411,14 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); - assert((VT == MVT::i8 || VT == MVT::i16) && + assert((VT == EVT::i8 || VT == EVT::i16) && "unexpected type for custom-lowering vector extract"); SDValue Vec = Op.getOperand(0); SDValue Lane = Op.getOperand(1); - Op = DAG.getNode(ARMISD::VGETLANEu, dl, MVT::i32, Vec, Lane); - Op = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Op, DAG.getValueType(VT)); + Op = DAG.getNode(ARMISD::VGETLANEu, dl, EVT::i32, Vec, Lane); + Op = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Op, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, dl, VT, Op); } @@ -2428,16 +2428,16 @@ static SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { assert(Op.getValueType().is128BitVector() && Op.getNumOperands() == 2 && "unexpected CONCAT_VECTORS"); DebugLoc dl = Op.getDebugLoc(); - SDValue Val = DAG.getUNDEF(MVT::v2f64); + SDValue Val = DAG.getUNDEF(EVT::v2f64); SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); if (Op0.getOpcode() != ISD::UNDEF) - Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op0), + Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op0), DAG.getIntPtrConstant(0)); if (Op1.getOpcode() != ISD::UNDEF) - Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2f64, Val, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op1), + Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v2f64, Val, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op1), DAG.getIntPtrConstant(1)); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Val); } @@ -2652,7 +2652,7 @@ SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, TargetLowering::DAGCombinerInfo &DCI) { SelectionDAG &DAG = DCI.DAG; const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); unsigned Opc = N->getOpcode(); bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); @@ -2680,7 +2680,7 @@ SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, cast<ConstantSDNode>(RHS)->isNullValue()) { std::swap(LHS, RHS); SDValue Op0 = Slct.getOperand(0); - MVT OpVT = isSlctCC ? Op0.getValueType() : + EVT OpVT = isSlctCC ? Op0.getValueType() : Op0.getOperand(0).getValueType(); bool isInt = OpVT.isInteger(); CC = ISD::getSetCCInverse(CC, isInt); @@ -2775,7 +2775,7 @@ static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) { /// operand of a vector shift left operation. That value must be in the range: /// 0 <= Value < ElementBits for a left shift; or /// 0 <= Value <= ElementBits for a long left shift. -static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) { +static bool isVShiftLImm(SDValue Op, EVT VT, bool isLong, int64_t &Cnt) { assert(VT.isVector() && "vector shift count is not a vector type"); unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); if (! getVShiftImm(Op, ElementBits, Cnt)) @@ -2789,7 +2789,7 @@ static bool isVShiftLImm(SDValue Op, MVT VT, bool isLong, int64_t &Cnt) { /// absolute value must be in the range: /// 1 <= |Value| <= ElementBits for a right shift; or /// 1 <= |Value| <= ElementBits/2 for a narrow right shift. -static bool isVShiftRImm(SDValue Op, MVT VT, bool isNarrow, bool isIntrinsic, +static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, bool isIntrinsic, int64_t &Cnt) { assert(VT.isVector() && "vector shift count is not a vector type"); unsigned ElementBits = VT.getVectorElementType().getSizeInBits(); @@ -2830,7 +2830,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { case Intrinsic::arm_neon_vqrshiftns: case Intrinsic::arm_neon_vqrshiftnu: case Intrinsic::arm_neon_vqrshiftnsu: { - MVT VT = N->getOperand(1).getValueType(); + EVT VT = N->getOperand(1).getValueType(); int64_t Cnt; unsigned VShiftOpc = 0; @@ -2930,11 +2930,11 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { } return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), - N->getOperand(1), DAG.getConstant(Cnt, MVT::i32)); + N->getOperand(1), DAG.getConstant(Cnt, EVT::i32)); } case Intrinsic::arm_neon_vshiftins: { - MVT VT = N->getOperand(1).getValueType(); + EVT VT = N->getOperand(1).getValueType(); int64_t Cnt; unsigned VShiftOpc = 0; @@ -2948,7 +2948,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { return DAG.getNode(VShiftOpc, N->getDebugLoc(), N->getValueType(0), N->getOperand(1), N->getOperand(2), - DAG.getConstant(Cnt, MVT::i32)); + DAG.getConstant(Cnt, EVT::i32)); } case Intrinsic::arm_neon_vqrshifts: @@ -2967,7 +2967,7 @@ static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) { /// their values after they get legalized to loads from a constant pool. static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // Nothing to be done for scalar shifts. if (! VT.isVector()) @@ -2982,7 +2982,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, case ISD::SHL: if (isVShiftLImm(N->getOperand(1), VT, false, Cnt)) return DAG.getNode(ARMISD::VSHL, N->getDebugLoc(), VT, N->getOperand(0), - DAG.getConstant(Cnt, MVT::i32)); + DAG.getConstant(Cnt, EVT::i32)); break; case ISD::SRA: @@ -2991,7 +2991,7 @@ static SDValue PerformShiftCombine(SDNode *N, SelectionDAG &DAG, unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ? ARMISD::VSHRs : ARMISD::VSHRu); return DAG.getNode(VShiftOpc, N->getDebugLoc(), VT, N->getOperand(0), - DAG.getConstant(Cnt, MVT::i32)); + DAG.getConstant(Cnt, EVT::i32)); } } return SDValue(); @@ -3010,12 +3010,12 @@ static SDValue PerformExtendCombine(SDNode *N, SelectionDAG &DAG, if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) { SDValue Vec = N0.getOperand(0); SDValue Lane = N0.getOperand(1); - MVT VT = N->getValueType(0); - MVT EltVT = N0.getValueType(); + EVT VT = N->getValueType(0); + EVT EltVT = N0.getValueType(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); - if (VT == MVT::i32 && - (EltVT == MVT::i8 || EltVT == MVT::i16) && + if (VT == EVT::i32 && + (EltVT == EVT::i8 || EltVT == EVT::i16) && TLI.isTypeLegal(Vec.getValueType())) { unsigned Opc = 0; @@ -3060,7 +3060,7 @@ SDValue ARMTargetLowering::PerformDAGCombine(SDNode *N, /// isLegalAddressImmediate - Return true if the integer value can be used /// as the offset of the target addressing mode for load / store of the /// given type. -static bool isLegalAddressImmediate(int64_t V, MVT VT, +static bool isLegalAddressImmediate(int64_t V, EVT VT, const ARMSubtarget *Subtarget) { if (V == 0) return true; @@ -3075,15 +3075,15 @@ static bool isLegalAddressImmediate(int64_t V, MVT VT, unsigned Scale = 1; switch (VT.getSimpleVT()) { default: return false; - case MVT::i1: - case MVT::i8: + case EVT::i1: + case EVT::i8: // Scale == 1; break; - case MVT::i16: + case EVT::i16: // Scale == 2; Scale = 2; break; - case MVT::i32: + case EVT::i32: // Scale == 4; Scale = 4; break; @@ -3099,16 +3099,16 @@ static bool isLegalAddressImmediate(int64_t V, MVT VT, V = - V; switch (VT.getSimpleVT()) { default: return false; - case MVT::i1: - case MVT::i8: - case MVT::i32: + case EVT::i1: + case EVT::i8: + case EVT::i32: // +- imm12 return V == (V & ((1LL << 12) - 1)); - case MVT::i16: + case EVT::i16: // +- imm8 return V == (V & ((1LL << 8) - 1)); - case MVT::f32: - case MVT::f64: + case EVT::f32: + case EVT::f64: if (!Subtarget->hasVFP2()) return false; if ((V & 3) != 0) @@ -3122,7 +3122,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT VT, /// by AM is legal for this target, for a load/store of the specified type. bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, const Type *Ty) const { - MVT VT = getValueType(Ty, true); + EVT VT = getValueType(Ty, true); if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) return false; @@ -3148,10 +3148,10 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, int Scale = AM.Scale; switch (VT.getSimpleVT()) { default: return false; - case MVT::i1: - case MVT::i8: - case MVT::i32: - case MVT::i64: + case EVT::i1: + case EVT::i8: + case EVT::i32: + case EVT::i64: // This assumes i64 is legalized to a pair of i32. If not (i.e. // ldrd / strd are used, then its address mode is same as i16. // r + r @@ -3160,13 +3160,13 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, return true; // r + r << imm return isPowerOf2_32(Scale & ~1); - case MVT::i16: + case EVT::i16: // r + r if (((unsigned)AM.HasBaseReg + Scale) <= 2) return true; return false; - case MVT::isVoid: + case EVT::isVoid: // Note, we allow "void" uses (basically, uses that aren't loads or // stores), because arm allows folding a scale into many arithmetic // operations. This should be made more precise and revisited later. @@ -3180,14 +3180,14 @@ bool ARMTargetLowering::isLegalAddressingMode(const AddrMode &AM, return true; } -static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT, +static bool getARMIndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) { if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB) return false; - if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) { + if (VT == EVT::i16 || ((VT == EVT::i8 || VT == EVT::i1) && isSEXTLoad)) { // AddressingMode 3 Base = Ptr->getOperand(0); if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { @@ -3202,7 +3202,7 @@ static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT, isInc = (Ptr->getOpcode() == ISD::ADD); Offset = Ptr->getOperand(1); return true; - } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) { + } else if (VT == EVT::i32 || VT == EVT::i8 || VT == EVT::i1) { // AddressingMode 2 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) { int RHSC = (int)RHS->getZExtValue(); @@ -3238,7 +3238,7 @@ static bool getARMIndexedAddressParts(SDNode *Ptr, MVT VT, return false; } -static bool getT2IndexedAddressParts(SDNode *Ptr, MVT VT, +static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT, bool isSEXTLoad, SDValue &Base, SDValue &Offset, bool &isInc, SelectionDAG &DAG) { @@ -3274,7 +3274,7 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, if (Subtarget->isThumb1Only()) return false; - MVT VT; + EVT VT; SDValue Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { @@ -3313,7 +3313,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op, if (Subtarget->isThumb1Only()) return false; - MVT VT; + EVT VT; SDValue Ptr; bool isSEXTLoad = false; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { @@ -3383,7 +3383,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const { std::pair<unsigned, const TargetRegisterClass*> ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { @@ -3395,9 +3395,9 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, case 'r': return std::make_pair(0U, ARM::GPRRegisterClass); case 'w': - if (VT == MVT::f32) + if (VT == EVT::f32) return std::make_pair(0U, ARM::SPRRegisterClass); - if (VT == MVT::f64) + if (VT == EVT::f64) return std::make_pair(0U, ARM::DPRRegisterClass); break; } @@ -3407,7 +3407,7 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, std::vector<unsigned> ARMTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() != 1) return std::vector<unsigned>(); @@ -3423,7 +3423,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, ARM::R8, ARM::R9, ARM::R10, ARM::R11, ARM::R12, ARM::LR, 0); case 'w': - if (VT == MVT::f32) + if (VT == EVT::f32) return make_vector<unsigned>(ARM::S0, ARM::S1, ARM::S2, ARM::S3, ARM::S4, ARM::S5, ARM::S6, ARM::S7, ARM::S8, ARM::S9, ARM::S10, ARM::S11, @@ -3432,7 +3432,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, ARM::S20,ARM::S21,ARM::S22,ARM::S23, ARM::S24,ARM::S25,ARM::S26,ARM::S27, ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); - if (VT == MVT::f64) + if (VT == EVT::f64) return make_vector<unsigned>(ARM::D0, ARM::D1, ARM::D2, ARM::D3, ARM::D4, ARM::D5, ARM::D6, ARM::D7, ARM::D8, ARM::D9, ARM::D10,ARM::D11, diff --git a/lib/Target/ARM/ARMISelLowering.h b/lib/Target/ARM/ARMISelLowering.h index 4649c18de8..648d388037 100644 --- a/lib/Target/ARM/ARMISelLowering.h +++ b/lib/Target/ARM/ARMISelLowering.h @@ -194,10 +194,10 @@ namespace llvm { ConstraintType getConstraintType(const std::string &Constraint) const; std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. If hasMemory is @@ -225,9 +225,9 @@ namespace llvm { /// unsigned ARMPCLabelIndex; - void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT); - void addDRTypeForNEON(MVT VT); - void addQRTypeForNEON(MVT VT); + void addTypeForNEON(EVT VT, EVT PromotedLdStVT, EVT PromotedBitwiseVT); + void addDRTypeForNEON(EVT VT); + void addQRTypeForNEON(EVT VT); typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector; void PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG, diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 9789a3b82a..5190492b64 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -129,13 +129,13 @@ class RegConstraint<string C> { // so_imm_neg_XFORM - Return a so_imm value packed into the format described for // so_imm_neg def below. def so_imm_neg_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); + return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32); }]>; // so_imm_not_XFORM - Return a so_imm value packed into the format described for // so_imm_not def below. def so_imm_not_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(~(int)N->getZExtValue(), MVT::i32); + return CurDAG->getTargetConstant(~(int)N->getZExtValue(), EVT::i32); }]>; // rot_imm predicate - True if the 32-bit immediate is equal to 8, 16, or 24. @@ -254,12 +254,12 @@ def so_imm2part : Operand<i32>, def so_imm2part_1 : SDNodeXForm<imm, [{ unsigned V = ARM_AM::getSOImmTwoPartFirst((unsigned)N->getZExtValue()); - return CurDAG->getTargetConstant(V, MVT::i32); + return CurDAG->getTargetConstant(V, EVT::i32); }]>; def so_imm2part_2 : SDNodeXForm<imm, [{ unsigned V = ARM_AM::getSOImmTwoPartSecond((unsigned)N->getZExtValue()); - return CurDAG->getTargetConstant(V, MVT::i32); + return CurDAG->getTargetConstant(V, EVT::i32); }]>; diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index 77bea68352..a028db7784 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -277,33 +277,33 @@ def VST4d32 : VST4D<"vst4.32">; // Extract D sub-registers of Q registers. // (arm_dsubreg_0 is 5; arm_dsubreg_1 is 6) def DSubReg_i8_reg : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, MVT::i32); + return CurDAG->getTargetConstant(5 + N->getZExtValue() / 8, EVT::i32); }]>; def DSubReg_i16_reg : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, MVT::i32); + return CurDAG->getTargetConstant(5 + N->getZExtValue() / 4, EVT::i32); }]>; def DSubReg_i32_reg : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, MVT::i32); + return CurDAG->getTargetConstant(5 + N->getZExtValue() / 2, EVT::i32); }]>; def DSubReg_f64_reg : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(5 + N->getZExtValue(), MVT::i32); + return CurDAG->getTargetConstant(5 + N->getZExtValue(), EVT::i32); }]>; // Extract S sub-registers of Q registers. // (arm_ssubreg_0 is 1; arm_ssubreg_1 is 2; etc.) def SSubReg_f32_reg : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(1 + N->getZExtValue(), MVT::i32); + return CurDAG->getTargetConstant(1 + N->getZExtValue(), EVT::i32); }]>; // Translate lane numbers from Q registers to D subregs. def SubReg_i8_lane : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32); + return CurDAG->getTargetConstant(N->getZExtValue() & 7, EVT::i32); }]>; def SubReg_i16_lane : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32); + return CurDAG->getTargetConstant(N->getZExtValue() & 3, EVT::i32); }]>; def SubReg_i32_lane : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32); + return CurDAG->getTargetConstant(N->getZExtValue() & 1, EVT::i32); }]>; //===----------------------------------------------------------------------===// @@ -1772,7 +1772,7 @@ def VDUPfq : NVDup<0b11101010, 0b1011, 0b00, (outs QPR:$dst), (ins GPR:$src), def SHUFFLE_get_splat_lane : SDNodeXForm<vector_shuffle, [{ ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); - return CurDAG->getTargetConstant(SVOp->getSplatIndex(), MVT::i32); + return CurDAG->getTargetConstant(SVOp->getSplatIndex(), EVT::i32); }]>; def splat_lane : PatFrag<(ops node:$lhs, node:$rhs), diff --git a/lib/Target/ARM/ARMInstrThumb.td b/lib/Target/ARM/ARMInstrThumb.td index 25dbddf0e2..7d27af2df1 100644 --- a/lib/Target/ARM/ARMInstrThumb.td +++ b/lib/Target/ARM/ARMInstrThumb.td @@ -19,10 +19,10 @@ def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; def imm_neg_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); + return CurDAG->getTargetConstant(-(int)N->getZExtValue(), EVT::i32); }]>; def imm_comp_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); + return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32); }]>; @@ -58,12 +58,12 @@ def thumb_immshifted : PatLeaf<(imm), [{ def thumb_immshifted_val : SDNodeXForm<imm, [{ unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); - return CurDAG->getTargetConstant(V, MVT::i32); + return CurDAG->getTargetConstant(V, EVT::i32); }]>; def thumb_immshifted_shamt : SDNodeXForm<imm, [{ unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); - return CurDAG->getTargetConstant(V, MVT::i32); + return CurDAG->getTargetConstant(V, EVT::i32); }]>; // Define Thumb specific addressing modes. diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 5499763667..f7ea0d3d0a 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -37,12 +37,12 @@ def t2_so_reg : Operand<i32>, // reg imm // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); + return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), EVT::i32); }]>; // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); + return CurDAG->getTargetConstant(-((int)N->getZExtValue()), EVT::i32); }]>; // t2_so_imm - Match a 32-bit immediate operand, which is an @@ -97,11 +97,11 @@ def imm0_65535 : PatLeaf<(i32 imm), [{ /// Split a 32-bit immediate into two 16 bit parts. def t2_lo16 : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() & 0xffff, - MVT::i32); + EVT::i32); }]>; def t2_hi16 : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, MVT::i32); + return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, EVT::i32); }]>; def t2_lo16AllZero : PatLeaf<(i32 imm), [{ diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 872f1d3ad7..f862114d3a 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -67,7 +67,7 @@ void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB, } const TargetRegisterClass* -Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, MVT VT) const { +Thumb1RegisterInfo::getPhysicalRegisterRegClass(unsigned Reg, EVT VT) const { if (isARMLowRegister(Reg)) return ARM::tGPRRegisterClass; switch (Reg) { diff --git a/lib/Target/ARM/Thumb1RegisterInfo.h b/lib/Target/ARM/Thumb1RegisterInfo.h index 05b6ae9cef..c45c261d5a 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.h +++ b/lib/Target/ARM/Thumb1RegisterInfo.h @@ -38,7 +38,7 @@ public: /// Code Generation virtual methods... const TargetRegisterClass * - getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; + getPhysicalRegisterRegClass(unsigned Reg, EVT VT = EVT::Other) const; bool requiresRegisterScavenging(const MachineFunction &MF) const; diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 6b2cf70112..d4b4e93210 100644 --- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -152,7 +152,7 @@ namespace { /// getI64Imm - Return a target constant with the specified value, of type /// i64. inline SDValue getI64Imm(int64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i64); + return CurDAG->getTargetConstant(Imm, EVT::i64); } // Select - Convert the specified operand from a target-independent to a @@ -251,8 +251,8 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { case ISD::FrameIndex: { int FI = cast<FrameIndexSDNode>(N)->getIndex(); - return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64, - CurDAG->getTargetFrameIndex(FI, MVT::i32), + return CurDAG->SelectNodeTo(N, Alpha::LDA, EVT::i64, + CurDAG->getTargetFrameIndex(FI, EVT::i32), getI64Imm(0)); } case ISD::GLOBAL_OFFSET_TABLE: @@ -272,16 +272,16 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, N0, Chain.getValue(1)); SDNode *CNode = - CurDAG->getTargetNode(Alpha::JSRs, dl, MVT::Other, MVT::Flag, + CurDAG->getTargetNode(Alpha::JSRs, dl, EVT::Other, EVT::Flag, Chain, Chain.getValue(1)); - Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, MVT::i64, + Chain = CurDAG->getCopyFromReg(Chain, dl, Alpha::R27, EVT::i64, SDValue(CNode, 1)); - return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain); + return CurDAG->SelectNodeTo(N, Alpha::BISr, EVT::i64, Chain, Chain); } case ISD::READCYCLECOUNTER: { SDValue Chain = N->getOperand(0); - return CurDAG->getTargetNode(Alpha::RPCC, dl, MVT::i64, MVT::Other, + return CurDAG->getTargetNode(Alpha::RPCC, dl, EVT::i64, EVT::Other, Chain); } @@ -290,7 +290,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { if (uval == 0) { SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - Alpha::R31, MVT::i64); + Alpha::R31, EVT::i64); ReplaceUses(Op, Result); return NULL; } @@ -306,17 +306,17 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { break; //(zext (LDAH (LDA))) //Else use the constant pool ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval); - SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64); - SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, MVT::i64, CPI, + SDValue CPI = CurDAG->getTargetConstantPool(C, EVT::i64); + SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, dl, EVT::i64, CPI, SDValue(getGlobalBaseReg(), 0)); - return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other, + return CurDAG->SelectNodeTo(N, Alpha::LDQr, EVT::i64, EVT::Other, CPI, SDValue(Tmp, 0), CurDAG->getEntryNode()); } case ISD::TargetConstantFP: case ISD::ConstantFP: { ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N); - bool isDouble = N->getValueType(0) == MVT::f64; - MVT T = isDouble ? MVT::f64 : MVT::f32; + bool isDouble = N->getValueType(0) == EVT::f64; + EVT T = isDouble ? EVT::f64 : EVT::f32; if (CN->getValueAPF().isPosZero()) { return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS, T, CurDAG->getRegister(Alpha::F31, T), @@ -359,18 +359,18 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { }; SDValue tmp1 = N->getOperand(rev?1:0); SDValue tmp2 = N->getOperand(rev?0:1); - SDNode *cmp = CurDAG->getTargetNode(Opc, dl, MVT::f64, tmp1, tmp2); + SDNode *cmp = CurDAG->getTargetNode(Opc, dl, EVT::f64, tmp1, tmp2); if (inv) cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, dl, - MVT::f64, SDValue(cmp, 0), - CurDAG->getRegister(Alpha::F31, MVT::f64)); + EVT::f64, SDValue(cmp, 0), + CurDAG->getRegister(Alpha::F31, EVT::f64)); switch(CC) { case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE: { - SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, MVT::f64, + SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, dl, EVT::f64, tmp1, tmp2); - cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, MVT::f64, + cmp = CurDAG->getTargetNode(Alpha::ADDT, dl, EVT::f64, SDValue(cmp2, 0), SDValue(cmp, 0)); break; } @@ -378,9 +378,9 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { } SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, dl, - MVT::i64, SDValue(cmp, 0)); - return CurDAG->getTargetNode(Alpha::CMPULT, dl, MVT::i64, - CurDAG->getRegister(Alpha::R31, MVT::i64), + EVT::i64, SDValue(cmp, 0)); + return CurDAG->getTargetNode(Alpha::CMPULT, dl, EVT::i64, + CurDAG->getRegister(Alpha::R31, EVT::i64), SDValue(LD,0)); } break; @@ -406,10 +406,10 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { if (get_zapImm(mask)) { SDValue Z = - SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, MVT::i64, + SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, dl, EVT::i64, N->getOperand(0).getOperand(0), getI64Imm(get_zapImm(mask))), 0); - return CurDAG->getTargetNode(Alpha::SRLr, dl, MVT::i64, Z, + return CurDAG->getTargetNode(Alpha::SRLr, dl, EVT::i64, Z, getI64Imm(sval)); } } @@ -434,14 +434,14 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { SDValue GOT = SDValue(getGlobalBaseReg(), 0); Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R29, GOT, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, MVT::Other, - MVT::Flag, Addr.getOperand(0), + Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, dl, EVT::Other, + EVT::Flag, Addr.getOperand(0), Chain, InFlag), 0); } else { Chain = CurDAG->getCopyToReg(Chain, dl, Alpha::R27, Addr, InFlag); InFlag = Chain.getValue(1); - Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, MVT::Other, - MVT::Flag, Chain, InFlag), 0); + Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, dl, EVT::Other, + EVT::Flag, Chain, InFlag), 0); } InFlag = Chain.getValue(1); diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp index c8817b1696..1033753ec7 100644 --- a/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/lib/Target/Alpha/AlphaISelLowering.cpp @@ -46,114 +46,114 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { // Set up the TargetLowering object. //I am having problems with shr n i8 1 - setShiftAmountType(MVT::i64); + setShiftAmountType(EVT::i64); setBooleanContents(ZeroOrOneBooleanContent); setUsesGlobalOffsetTable(true); - addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass); - addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass); - addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass); + addRegisterClass(EVT::i64, Alpha::GPRCRegisterClass); + addRegisterClass(EVT::f64, Alpha::F8RCRegisterClass); + addRegisterClass(EVT::f32, Alpha::F4RCRegisterClass); // We want to custom lower some of our intrinsics. - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom); - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i32, Expand); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i32, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); - // setOperationAction(ISD::BRIND, MVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + // setOperationAction(ISD::BRIND, EVT::Other, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::Other, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); - setOperationAction(ISD::FREM, MVT::f32, Expand); - setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FREM, EVT::f32, Expand); + setOperationAction(ISD::FREM, EVT::f64, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); + setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand); + setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom); + setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand); + setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom); if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) { - setOperationAction(ISD::CTPOP , MVT::i64 , Expand); - setOperationAction(ISD::CTTZ , MVT::i64 , Expand); - setOperationAction(ISD::CTLZ , MVT::i64 , Expand); + setOperationAction(ISD::CTPOP , EVT::i64 , Expand); + setOperationAction(ISD::CTTZ , EVT::i64 , Expand); + setOperationAction(ISD::CTLZ , EVT::i64 , Expand); } - setOperationAction(ISD::BSWAP , MVT::i64, Expand); - setOperationAction(ISD::ROTL , MVT::i64, Expand); - setOperationAction(ISD::ROTR , MVT::i64, Expand); + setOperationAction(ISD::BSWAP , EVT::i64, Expand); + setOperationAction(ISD::ROTL , EVT::i64, Expand); + setOperationAction(ISD::ROTR , EVT::i64, Expand); - setOperationAction(ISD::SREM , MVT::i64, Custom); - setOperationAction(ISD::UREM , MVT::i64, Custom); - setOperationAction(ISD::SDIV , MVT::i64, Custom); - setOperationAction(ISD::UDIV , MVT::i64, Custom); + setOperationAction(ISD::SREM , EVT::i64, Custom); + setOperationAction(ISD::UREM , EVT::i64, Custom); + setOperationAction(ISD::SDIV , EVT::i64, Custom); + setOperationAction(ISD::UDIV , EVT::i64, Custom); - setOperationAction(ISD::ADDC , MVT::i64, Expand); - setOperationAction(ISD::ADDE , MVT::i64, Expand); - setOperationAction(ISD::SUBC , MVT::i64, Expand); - setOperationAction(ISD::SUBE , MVT::i64, Expand); + setOperationAction(ISD::ADDC , EVT::i64, Expand); + setOperationAction(ISD::ADDE , EVT::i64, Expand); + setOperationAction(ISD::SUBC , EVT::i64, Expand); + setOperationAction(ISD::SUBE , EVT::i64, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); - setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, EVT::i64, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i64, Expand); // We don't support sin/cos/sqrt/pow - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSIN , EVT::f64, Expand); + setOperationAction(ISD::FCOS , EVT::f64, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); - setOperationAction(ISD::FSQRT, MVT::f64, Expand); - setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FSQRT, EVT::f64, Expand); + setOperationAction(ISD::FSQRT, EVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f64, Expand); + setOperationAction(ISD::FPOW , EVT::f32, Expand); + setOperationAction(ISD::FPOW , EVT::f64, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Promote); + setOperationAction(ISD::SETCC, EVT::f32, Promote); - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote); + setOperationAction(ISD::BIT_CONVERT, EVT::f32, Promote); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); // Not implemented yet. - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand); // We want to legalize GlobalAddress and ConstantPool and // ExternalSymbols nodes into the appropriate instructions to // materialize the address. - setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); - setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i64, Custom); + setOperationAction(ISD::ConstantPool, EVT::i64, Custom); + setOperationAction(ISD::ExternalSymbol, EVT::i64, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom); - setOperationAction(ISD::VASTART, MVT::Other, Custom); - setOperationAction(ISD::VAEND, MVT::Other, Expand); - setOperationAction(ISD::VACOPY, MVT::Other, Custom); - setOperationAction(ISD::VAARG, MVT::Other, Custom); - setOperationAction(ISD::VAARG, MVT::i32, Custom); + setOperationAction(ISD::VASTART, EVT::Other, Custom); + setOperationAction(ISD::VAEND, EVT::Other, Expand); + setOperationAction(ISD::VACOPY, EVT::Other, Custom); + setOperationAction(ISD::VAARG, EVT::Other, Custom); + setOperationAction(ISD::VAARG, EVT::i32, Custom); - setOperationAction(ISD::JumpTable, MVT::i64, Custom); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::JumpTable, EVT::i64, Custom); + setOperationAction(ISD::JumpTable, EVT::i32, Custom); setStackPointerRegisterToSaveRestore(Alpha::R30); @@ -168,8 +168,8 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) computeRegisterProperties(); } -MVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(MVT VT) const { - return MVT::i64; +EVT::SimpleValueType AlphaTargetLowering::getSetCCResultType(EVT VT) const { + return EVT::i64; } const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const { @@ -196,16 +196,16 @@ unsigned AlphaTargetLowering::getFunctionAlignment(const Function *F) const { } static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); // FIXME there isn't really any debug info here DebugLoc dl = Op.getDebugLoc(); - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, JTI, - DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, JTI, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, JTI, + DAG.getGLOBAL_OFFSET_TABLE(EVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, JTI, Hi); return Lo; } @@ -285,7 +285,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, assert(VA.isMemLoc()); if (StackPtr.getNode() == 0) - StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64); + StackPtr = DAG.getCopyFromReg(Chain, dl, Alpha::R30, EVT::i64); SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, @@ -299,7 +299,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Transform all store nodes into one single node because all store nodes are // independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain and @@ -313,7 +313,7 @@ AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -406,27 +406,27 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain, for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { SDValue argt; - MVT ObjectVT = Ins[ArgNo].VT; + EVT ObjectVT = Ins[ArgNo].VT; SDValue ArgVal; if (ArgNo < 6) { switch (ObjectVT.getSimpleVT()) { default: assert(false && "Invalid value type!"); - case MVT::f64: + case EVT::f64: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F8RCRegClass); ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT); break; - case MVT::f32: + case EVT::f32: args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo], &Alpha::F4RCRegClass); ArgVal = DAG.getCopyFromReg(Chain, dl, args_float[ArgNo], ObjectVT); break; - case MVT::i64: + case EVT::i64: args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo], &Alpha::GPRCRegClass); - ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], MVT::i64); + ArgVal = DAG.getCopyFromReg(Chain, dl, args_int[ArgNo], EVT::i64); break; } } else { //more args @@ -435,7 +435,7 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain, // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDValue FIN = DAG.getFrameIndex(FI, MVT::i64); + SDValue FIN = DAG.getFrameIndex(FI, EVT::i64); ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0); } InVals.push_back(ArgVal); @@ -448,22 +448,22 @@ AlphaTargetLowering::LowerFormalArguments(SDValue Chain, for (int i = 0; i < 6; ++i) { if (TargetRegisterInfo::isPhysicalRegister(args_int[i])) args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass); - SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], MVT::i64); + SDValue argt = DAG.getCopyFromReg(Chain, dl, args_int[i], EVT::i64); int FI = MFI->CreateFixedObject(8, -8 * (6 - i)); if (i == 0) VarArgsBase = FI; - SDValue SDFI = DAG.getFrameIndex(FI, MVT::i64); + SDValue SDFI = DAG.getFrameIndex(FI, EVT::i64); LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0)); if (TargetRegisterInfo::isPhysicalRegister(args_float[i])) args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass); - argt = DAG.getCopyFromReg(Chain, dl, args_float[i], MVT::f64); + argt = DAG.getCopyFromReg(Chain, dl, args_float[i], EVT::f64); FI = MFI->CreateFixedObject(8, - 8 * (12 - i)); - SDFI = DAG.getFrameIndex(FI, MVT::i64); + SDFI = DAG.getFrameIndex(FI, EVT::i64); LS.push_back(DAG.getStore(Chain, dl, argt, SDFI, NULL, 0)); } //Set up a token factor with all the stack traffic - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LS[0], LS.size()); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LS[0], LS.size()); } return Chain; @@ -478,7 +478,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain, SDValue Copy = DAG.getCopyToReg(Chain, dl, Alpha::R26, DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(), - MVT::i64), + EVT::i64), SDValue()); switch (Outs.size()) { default: @@ -487,7 +487,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain, break; //return SDValue(); // ret void is legal case 1: { - MVT ArgVT = Outs[0].Val.getValueType(); + EVT ArgVT = Outs[0].Val.getValueType(); unsigned ArgReg; if (ArgVT.isInteger()) ArgReg = Alpha::R0; @@ -502,7 +502,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain, break; } case 2: { - MVT ArgVT = Outs[0].Val.getValueType(); + EVT ArgVT = Outs[0].Val.getValueType(); unsigned ArgReg1, ArgReg2; if (ArgVT.isInteger()) { ArgReg1 = Alpha::R0; @@ -528,7 +528,7 @@ AlphaTargetLowering::LowerReturn(SDValue Chain, } } return DAG.getNode(AlphaISD::RET_FLAG, dl, - MVT::Other, Copy, Copy.getValue(1)); + EVT::Other, Copy, Copy.getValue(1)); } void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, @@ -538,26 +538,26 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, const Value *VAListS = cast<SrcValueSDNode>(N->getOperand(2))->getValue(); DebugLoc dl = N->getDebugLoc(); - SDValue Base = DAG.getLoad(MVT::i64, dl, Chain, VAListP, VAListS, 0); - SDValue Tmp = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, - DAG.getConstant(8, MVT::i64)); - SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Base.getValue(1), - Tmp, NULL, 0, MVT::i32); - DataPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Base, Offset); + SDValue Base = DAG.getLoad(EVT::i64, dl, Chain, VAListP, VAListS, 0); + SDValue Tmp = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP, + DAG.getConstant(8, EVT::i64)); + SDValue Offset = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Base.getValue(1), + Tmp, NULL, 0, EVT::i32); + DataPtr = DAG.getNode(ISD::ADD, dl, EVT::i64, Base, Offset); if (N->getValueType(0).isFloatingPoint()) { //if fp && Offset < 6*8, then subtract 6*8 from DataPtr - SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, MVT::i64, DataPtr, - DAG.getConstant(8*6, MVT::i64)); - SDValue CC = DAG.getSetCC(dl, MVT::i64, Offset, - DAG.getConstant(8*6, MVT::i64), ISD::SETLT); - DataPtr = DAG.getNode(ISD::SELECT, dl, MVT::i64, CC, FPDataPtr, DataPtr); + SDValue FPDataPtr = DAG.getNode(ISD::SUB, dl, EVT::i64, DataPtr, + DAG.getConstant(8*6, EVT::i64)); + SDValue CC = DAG.getSetCC(dl, EVT::i64, Offset, + DAG.getConstant(8*6, EVT::i64), ISD::SETLT); + DataPtr = DAG.getNode(ISD::SELECT, dl, EVT::i64, CC, FPDataPtr, DataPtr); } - SDValue NewOffset = DAG.getNode(ISD::ADD, dl, MVT::i64, Offset, - DAG.getConstant(8, MVT::i64)); + SDValue NewOffset = DAG.getNode(ISD::ADD, dl, EVT::i64, Offset, + DAG.getConstant(8, EVT::i64)); Chain = DAG.getTruncStore(Offset.getValue(1), dl, NewOffset, Tmp, NULL, 0, - MVT::i32); + EVT::i32); } /// LowerOperation - Provide custom lowering hooks for some operations. @@ -573,7 +573,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { switch (IntNo) { default: break; // Don't custom lower most intrinsics. case Intrinsic::alpha_umulh: - return DAG.getNode(ISD::MULHU, dl, MVT::i64, + return DAG.getNode(ISD::MULHU, dl, EVT::i64, Op.getOperand(1), Op.getOperand(2)); } } @@ -582,23 +582,23 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue ShOpLo = Op.getOperand(0); SDValue ShOpHi = Op.getOperand(1); SDValue ShAmt = Op.getOperand(2); - SDValue bm = DAG.getNode(ISD::SUB, dl, MVT::i64, - DAG.getConstant(64, MVT::i64), ShAmt); - SDValue BMCC = DAG.getSetCC(dl, MVT::i64, bm, - DAG.getConstant(0, MVT::i64), ISD::SETLE); + SDValue bm = DAG.getNode(ISD::SUB, dl, EVT::i64, + DAG.getConstant(64, EVT::i64), ShAmt); + SDValue BMCC = DAG.getSetCC(dl, EVT::i64, bm, + DAG.getConstant(0, EVT::i64), ISD::SETLE); // if 64 - shAmt <= 0 - SDValue Hi_Neg = DAG.getConstant(0, MVT::i64); - SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, MVT::i64, - DAG.getConstant(0, MVT::i64), bm); - SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt_Neg); + SDValue Hi_Neg = DAG.getConstant(0, EVT::i64); + SDValue ShAmt_Neg = DAG.getNode(ISD::SUB, dl, EVT::i64, + DAG.getConstant(0, EVT::i64), bm); + SDValue Lo_Neg = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt_Neg); // else - SDValue carries = DAG.getNode(ISD::SHL, dl, MVT::i64, ShOpHi, bm); - SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpHi, ShAmt); - SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, MVT::i64, ShOpLo, ShAmt); - Lo_Pos = DAG.getNode(ISD::OR, dl, MVT::i64, Lo_Pos, carries); + SDValue carries = DAG.getNode(ISD::SHL, dl, EVT::i64, ShOpHi, bm); + SDValue Hi_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpHi, ShAmt); + SDValue Lo_Pos = DAG.getNode(ISD::SRL, dl, EVT::i64, ShOpLo, ShAmt); + Lo_Pos = DAG.getNode(ISD::OR, dl, EVT::i64, Lo_Pos, carries); // Merge - SDValue Hi = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Hi_Neg, Hi_Pos); - SDValue Lo = DAG.getNode(ISD::SELECT, dl, MVT::i64, BMCC, Lo_Neg, Lo_Pos); + SDValue Hi = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Hi_Neg, Hi_Pos); + SDValue Lo = DAG.getNode(ISD::SELECT, dl, EVT::i64, BMCC, Lo_Neg, Lo_Pos); SDValue Ops[2] = { Lo, Hi }; return DAG.getMergeValues(Ops, 2, dl); } @@ -608,35 +608,35 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::SINT_TO_FP: { - assert(Op.getOperand(0).getValueType() == MVT::i64 && + assert(Op.getOperand(0).getValueType() == EVT::i64 && "Unhandled SINT_TO_FP type in custom expander!"); SDValue LD; - bool isDouble = Op.getValueType() == MVT::f64; - LD = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, Op.getOperand(0)); + bool isDouble = Op.getValueType() == EVT::f64; + LD = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, Op.getOperand(0)); SDValue FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_, dl, - isDouble?MVT::f64:MVT::f32, LD); + isDouble?EVT::f64:EVT::f32, LD); return FP; } case ISD::FP_TO_SINT: { - bool isDouble = Op.getOperand(0).getValueType() == MVT::f64; + bool isDouble = Op.getOperand(0).getValueType() == EVT::f64; SDValue src = Op.getOperand(0); if (!isDouble) //Promote - src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, src); + src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, src); - src = DAG.getNode(AlphaISD::CVTTQ_, dl, MVT::f64, src); + src = DAG.getNode(AlphaISD::CVTTQ_, dl, EVT::f64, src); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, src); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, src); } case ISD::ConstantPool: { ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); - SDValue CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment()); + SDValue CPI = DAG.getTargetConstantPool(C, EVT::i64, CP->getAlignment()); // FIXME there isn't really any debug info here - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, CPI, - DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, CPI, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, CPI, + DAG.getGLOBAL_OFFSET_TABLE(EVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, CPI, Hi); return Lo; } case ISD::GlobalTLSAddress: @@ -644,31 +644,31 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); - SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset()); + SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i64, GSDN->getOffset()); // FIXME there isn't really any debug info here // if (!GV->hasWeakLinkage() && !GV->isDeclaration() && !GV->hasLinkOnceLinkage()) { if (GV->hasLocalLinkage()) { - SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, MVT::i64, GA, - DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); - SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, MVT::i64, GA, Hi); + SDValue Hi = DAG.getNode(AlphaISD::GPRelHi, dl, EVT::i64, GA, + DAG.getGLOBAL_OFFSET_TABLE(EVT::i64)); + SDValue Lo = DAG.getNode(AlphaISD::GPRelLo, dl, EVT::i64, GA, Hi); return Lo; } else - return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, GA, - DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); + return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64, GA, + DAG.getGLOBAL_OFFSET_TABLE(EVT::i64)); } case ISD::ExternalSymbol: { - return DAG.getNode(AlphaISD::RelLit, dl, MVT::i64, + return DAG.getNode(AlphaISD::RelLit, dl, EVT::i64, DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op) - ->getSymbol(), MVT::i64), - DAG.getGLOBAL_OFFSET_TABLE(MVT::i64)); + ->getSymbol(), EVT::i64), + DAG.getGLOBAL_OFFSET_TABLE(EVT::i64)); } case ISD::UREM: case ISD::SREM: //Expand only on constant case if (Op.getOperand(1).getOpcode() == ISD::Constant) { - MVT VT = Op.getNode()->getValueType(0); + EVT VT = Op.getNode()->getValueType(0); SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ? BuildUDIV(Op.getNode(), DAG, NULL) : BuildSDIV(Op.getNode(), DAG, NULL); @@ -692,8 +692,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { } SDValue Tmp1 = Op.getOperand(0), Tmp2 = Op.getOperand(1), - Addr = DAG.getExternalSymbol(opstr, MVT::i64); - return DAG.getNode(AlphaISD::DivCall, dl, MVT::i64, Addr, Tmp1, Tmp2); + Addr = DAG.getExternalSymbol(opstr, EVT::i64); + return DAG.getNode(AlphaISD::DivCall, dl, EVT::i64, Addr, Tmp1, Tmp2); } break; @@ -702,9 +702,9 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { LowerVAARG(Op.getNode(), Chain, DataPtr, DAG); SDValue Result; - if (Op.getValueType() == MVT::i32) - Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Chain, DataPtr, - NULL, 0, MVT::i32); + if (Op.getValueType() == EVT::i32) + Result = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Chain, DataPtr, + NULL, 0, EVT::i32); else Result = DAG.getLoad(Op.getValueType(), dl, Chain, DataPtr, NULL, 0); return Result; @@ -718,13 +718,13 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue Val = DAG.getLoad(getPointerTy(), dl, Chain, SrcP, SrcS, 0); SDValue Result = DAG.getStore(Val.getValue(1), dl, Val, DestP, DestS, 0); - SDValue NP = DAG.getNode(ISD::ADD, dl, MVT::i64, SrcP, - DAG.getConstant(8, MVT::i64)); - Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, MVT::i64, Result, - NP, NULL,0, MVT::i32); - SDValue NPD = DAG.getNode(ISD::ADD, dl, MVT::i64, DestP, - DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, MVT::i32); + SDValue NP = DAG.getNode(ISD::ADD, dl, EVT::i64, SrcP, + DAG.getConstant(8, EVT::i64)); + Val = DAG.getExtLoad(ISD::SEXTLOAD, dl, EVT::i64, Result, + NP, NULL,0, EVT::i32); + SDValue NPD = DAG.getNode(ISD::ADD, dl, EVT::i64, DestP, + DAG.getConstant(8, EVT::i64)); + return DAG.getTruncStore(Val.getValue(1), dl, Val, NPD, NULL, 0, EVT::i32); } case ISD::VASTART: { SDValue Chain = Op.getOperand(0); @@ -732,16 +732,16 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { const Value *VAListS = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); // vastart stores the address of the VarArgsBase and VarArgsOffset - SDValue FR = DAG.getFrameIndex(VarArgsBase, MVT::i64); + SDValue FR = DAG.getFrameIndex(VarArgsBase, EVT::i64); SDValue S1 = DAG.getStore(Chain, dl, FR, VAListP, VAListS, 0); - SDValue SA2 = DAG.getNode(ISD::ADD, dl, MVT::i64, VAListP, - DAG.getConstant(8, MVT::i64)); - return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, MVT::i64), - SA2, NULL, 0, MVT::i32); + SDValue SA2 = DAG.getNode(ISD::ADD, dl, EVT::i64, VAListP, + DAG.getConstant(8, EVT::i64)); + return DAG.getTruncStore(S1, dl, DAG.getConstant(VarArgsOffset, EVT::i64), + SA2, NULL, 0, EVT::i32); } case ISD::RETURNADDR: return DAG.getNode(AlphaISD::GlobalRetAddr, DebugLoc::getUnknownLoc(), - MVT::i64); + EVT::i64); //FIXME: implement case ISD::FRAMEADDR: break; } @@ -753,7 +753,7 @@ void AlphaTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, SelectionDAG &DAG) { DebugLoc dl = N->getDebugLoc(); - assert(N->getValueType(0) == MVT::i32 && + assert(N->getValueType(0) == EVT::i32 && N->getOpcode() == ISD::VAARG && "Unknown node to custom promote!"); @@ -784,7 +784,7 @@ AlphaTargetLowering::getConstraintType(const std::string &Constraint) const { std::vector<unsigned> AlphaTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { default: break; // Unknown constriant letter diff --git a/lib/Target/Alpha/AlphaISelLowering.h b/lib/Target/Alpha/AlphaISelLowering.h index 4e1de33d4f..f18d6fa4e2 100644 --- a/lib/Target/Alpha/AlphaISelLowering.h +++ b/lib/Target/Alpha/AlphaISelLowering.h @@ -67,7 +67,7 @@ namespace llvm { explicit AlphaTargetLowering(TargetMachine &TM); /// getSetCCResultType - Get the SETCC result ValueType - virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const; /// LowerOperation - Provide custom lowering hooks for some operations. /// @@ -92,7 +92,7 @@ namespace llvm { std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; bool hasITOF() { return useITOF; } diff --git a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp index 062b22abe6..3bf8fc5b47 100644 --- a/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp +++ b/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp @@ -94,9 +94,9 @@ SDNode *BlackfinDAGToDAGISel::Select(SDValue Op) { // Selects to ADDpp FI, 0 which in turn will become ADDimm7 SP, imm or ADDpp // SP, Px int FI = cast<FrameIndexSDNode>(N)->getIndex(); - SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i32); - return CurDAG->SelectNodeTo(N, BF::ADDpp, MVT::i32, TFI, - CurDAG->getTargetConstant(0, MVT::i32)); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i32); + return CurDAG->SelectNodeTo(N, BF::ADDpp, EVT::i32, TFI, + CurDAG->getTargetConstant(0, EVT::i32)); } } @@ -109,8 +109,8 @@ bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue &Offset) { FrameIndexSDNode *FIN = 0; if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } if (Addr.getOpcode() == ISD::ADD) { @@ -119,8 +119,8 @@ bool BlackfinDAGToDAGISel::SelectADDRspii(SDValue Op, (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { // Constant positive word offset from frame index - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32); return true; } } @@ -179,9 +179,9 @@ void BlackfinDAGToDAGISel::FixRegisterClasses(SelectionDAG &DAG) { SDNode *Copy = DAG.getTargetNode(TargetInstrInfo::COPY_TO_REGCLASS, NI->getDebugLoc(), - MVT::i32, + EVT::i32, UI.getUse().get(), - DAG.getTargetConstant(BF::DRegClassID, MVT::i32)); + DAG.getTargetConstant(BF::DRegClassID, EVT::i32)); UpdateNodeOperand(DAG, *UI, UI.getOperandNo(), SDValue(Copy, 0)); } } diff --git a/lib/Target/Blackfin/BlackfinISelLowering.cpp b/lib/Target/Blackfin/BlackfinISelLowering.cpp index 8b83791f3e..f40d9585c0 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.cpp +++ b/lib/Target/Blackfin/BlackfinISelLowering.cpp @@ -40,92 +40,92 @@ using namespace llvm; BlackfinTargetLowering::BlackfinTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { - setShiftAmountType(MVT::i16); + setShiftAmountType(EVT::i16); setBooleanContents(ZeroOrOneBooleanContent); setStackPointerRegisterToSaveRestore(BF::SP); setIntDivIsCheap(false); // Set up the legal register classes. - addRegisterClass(MVT::i32, BF::DRegisterClass); - addRegisterClass(MVT::i16, BF::D16RegisterClass); + addRegisterClass(EVT::i32, BF::DRegisterClass); + addRegisterClass(EVT::i16, BF::D16RegisterClass); computeRegisterProperties(); // Blackfin doesn't have i1 loads or stores - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); + setOperationAction(ISD::JumpTable, EVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::Other, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::Other, Expand); // i16 registers don't do much - setOperationAction(ISD::AND, MVT::i16, Promote); - setOperationAction(ISD::OR, MVT::i16, Promote); - setOperationAction(ISD::XOR, MVT::i16, Promote); - setOperationAction(ISD::CTPOP, MVT::i16, Promote); + setOperationAction(ISD::AND, EVT::i16, Promote); + setOperationAction(ISD::OR, EVT::i16, Promote); + setOperationAction(ISD::XOR, EVT::i16, Promote); + setOperationAction(ISD::CTPOP, EVT::i16, Promote); // The expansion of CTLZ/CTTZ uses AND/OR, so we might as well promote // immediately. - setOperationAction(ISD::CTLZ, MVT::i16, Promote); - setOperationAction(ISD::CTTZ, MVT::i16, Promote); - setOperationAction(ISD::SETCC, MVT::i16, Promote); + setOperationAction(ISD::CTLZ, EVT::i16, Promote); + setOperationAction(ISD::CTTZ, EVT::i16, Promote); + setOperationAction(ISD::SETCC, EVT::i16, Promote); // Blackfin has no division - setOperationAction(ISD::SDIV, MVT::i16, Expand); - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i16, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i16, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i16, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i16, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i16, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); - setOperationAction(ISD::MULHS, MVT::i32, Expand); + setOperationAction(ISD::SDIV, EVT::i16, Expand); + setOperationAction(ISD::SDIV, EVT::i32, Expand); + setOperationAction(ISD::SDIVREM, EVT::i16, Expand); + setOperationAction(ISD::SDIVREM, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i16, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::UDIV, EVT::i16, Expand); + setOperationAction(ISD::UDIV, EVT::i32, Expand); + setOperationAction(ISD::UDIVREM, EVT::i16, Expand); + setOperationAction(ISD::UDIVREM, EVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i16, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::MULHU, EVT::i32, Expand); + setOperationAction(ISD::MULHS, EVT::i32, Expand); // No carry-in operations. - setOperationAction(ISD::ADDE, MVT::i32, Custom); - setOperationAction(ISD::SUBE, MVT::i32, Custom); + setOperationAction(ISD::ADDE, EVT::i32, Custom); + setOperationAction(ISD::SUBE, EVT::i32, Custom); // Blackfin has no intrinsics for these particular operations. - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); - setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand); + setOperationAction(ISD::BSWAP, EVT::i32, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); // i32 has native CTPOP, but not CTLZ/CTTZ - setOperationAction(ISD::CTLZ, MVT::i32, Expand); - setOperationAction(ISD::CTTZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, EVT::i32, Expand); + setOperationAction(ISD::CTTZ, EVT::i32, Expand); // READCYCLECOUNTER needs special type legalization. - setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Custom); + setOperationAction(ISD::READCYCLECOUNTER, EVT::i64, Custom); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); - setOperationAction(ISD::DECLARE, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); + setOperationAction(ISD::DECLARE, EVT::Other, Expand); // Use the default implementation. - setOperationAction(ISD::VACOPY, MVT::Other, Expand); - setOperationAction(ISD::VAEND, MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::VACOPY, EVT::Other, Expand); + setOperationAction(ISD::VAEND, EVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); } const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const { @@ -137,10 +137,10 @@ const char *BlackfinTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(MVT VT) const { +EVT::SimpleValueType BlackfinTargetLowering::getSetCCResultType(EVT VT) const { // SETCC always sets the CC register. Technically that is an i1 register, but // that type is not legal, so we treat it as an i32 register. - return MVT::i32; + return EVT::i32; } SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, @@ -148,16 +148,16 @@ SDValue BlackfinTargetLowering::LowerGlobalAddress(SDValue Op, DebugLoc DL = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - Op = DAG.getTargetGlobalAddress(GV, MVT::i32); - return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op); + Op = DAG.getTargetGlobalAddress(GV, EVT::i32); + return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op); } SDValue BlackfinTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { DebugLoc DL = Op.getDebugLoc(); int JTI = cast<JumpTableSDNode>(Op)->getIndex(); - Op = DAG.getTargetJumpTable(JTI, MVT::i32); - return DAG.getNode(BFISD::Wrapper, DL, MVT::i32, Op); + Op = DAG.getTargetJumpTable(JTI, EVT::i32); + return DAG.getNode(BFISD::Wrapper, DL, EVT::i32, Op); } SDValue @@ -181,7 +181,7 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain, CCValAssign &VA = ArgLocs[i]; if (VA.isRegLoc()) { - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); TargetRegisterClass *RC = VA.getLocReg() == BF::P0 ? BF::PRegisterClass : BF::DRegisterClass; assert(RC->contains(VA.getLocReg()) && "Unexpected regclass in CCState"); @@ -209,7 +209,7 @@ BlackfinTargetLowering::LowerFormalArguments(SDValue Chain, assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc"); unsigned ObjSize = VA.getLocVT().getStoreSizeInBits()/8; int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset()); - SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + SDValue FIN = DAG.getFrameIndex(FI, EVT::i32); InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0)); } } @@ -268,9 +268,9 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) { - return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain, Flag); } else { - return DAG.getNode(BFISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(BFISD::RET_FLAG, dl, EVT::Other, Chain); } } @@ -325,10 +325,10 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, assert(VA.isMemLoc() && "CCValAssign must be RegLoc or MemLoc"); int Offset = VA.getLocMemOffset(); assert(Offset%4 == 0 && "Unaligned LocMemOffset"); - assert(VA.getLocVT()==MVT::i32 && "Illegal CCValAssign type"); - SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, MVT::i32); + assert(VA.getLocVT()==EVT::i32 && "Illegal CCValAssign type"); + SDValue SPN = DAG.getCopyFromReg(Chain, dl, BF::SP, EVT::i32); SDValue OffsetN = DAG.getIntPtrConstant(Offset); - OffsetN = DAG.getNode(ISD::ADD, dl, MVT::i32, SPN, OffsetN); + OffsetN = DAG.getNode(ISD::ADD, dl, EVT::i32, SPN, OffsetN); MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, OffsetN, PseudoSourceValue::getStack(), Offset)); @@ -338,7 +338,7 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Transform all store nodes into one single node because // all store nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -356,13 +356,13 @@ BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) - Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32); - std::vector<MVT> NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. + std::vector<EVT> NodeTys; + NodeTys.push_back(EVT::Other); // Returns a chain + NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use. SDValue Ops[] = { Chain, Callee, InFlag }; Chain = DAG.getNode(BFISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); @@ -423,25 +423,25 @@ SDValue BlackfinTargetLowering::LowerADDE(SDValue Op, SelectionDAG &DAG) { unsigned Opcode = Op.getOpcode()==ISD::ADDE ? BF::ADD : BF::SUB; // zext incoming carry flag in AC0 to 32 bits - SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, + SDNode* CarryIn = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32, /* flag= */ Op.getOperand(2)); - CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, MVT::i32, + CarryIn = DAG.getTargetNode(BF::MOVECC_zext, dl, EVT::i32, SDValue(CarryIn, 0)); // Add operands, produce sum and carry flag - SDNode *Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, + SDNode *Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag, Op.getOperand(0), Op.getOperand(1)); // Store intermediate carry from Sum - SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, MVT::i32, + SDNode* Carry1 = DAG.getTargetNode(BF::MOVE_cc_ac0, dl, EVT::i32, /* flag= */ SDValue(Sum, 1)); // Add incoming carry, again producing an output flag - Sum = DAG.getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, + Sum = DAG.getTargetNode(Opcode, dl, EVT::i32, EVT::Flag, SDValue(Sum, 0), SDValue(CarryIn, 0)); // Update AC0 with the intermediate carry, producing a flag. - SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, MVT::Flag, + SDNode *CarryOut = DAG.getTargetNode(BF::OR_ac0_cc, dl, EVT::Flag, SDValue(Carry1, 0)); // Compose (i32, flag) pair @@ -480,10 +480,10 @@ BlackfinTargetLowering::ReplaceNodeResults(SDNode *N, // CYCLES2. Reading CYCLES will latch the value of CYCLES2, so we must read // CYCLES2 last. SDValue TheChain = N->getOperand(0); - SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, MVT::i32); - SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, MVT::i32); + SDValue lo = DAG.getCopyFromReg(TheChain, dl, BF::CYCLES, EVT::i32); + SDValue hi = DAG.getCopyFromReg(lo.getValue(1), dl, BF::CYCLES2, EVT::i32); // Use a buildpair to merge the two 32-bit values into a 64-bit one. - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, lo, hi)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, lo, hi)); // Outgoing chain. If we were to use the chain from lo instead, it would be // possible to entirely eliminate the CYCLES2 read in (i32 (trunc // readcyclecounter)). Unfortunately this could possibly delay the CYCLES2 @@ -549,7 +549,7 @@ BlackfinTargetLowering::getConstraintType(const std::string &Constraint) const { /// getRegForInlineAsmConstraint - Return register no and class for a C_Register /// constraint. std::pair<unsigned, const TargetRegisterClass*> BlackfinTargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const { +getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { typedef std::pair<unsigned, const TargetRegisterClass*> Pair; using namespace BF; @@ -559,7 +559,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const { switch (Constraint[0]) { // Standard constraints case 'r': - return Pair(0U, VT == MVT::i16 ? D16RegisterClass : DPRegisterClass); + return Pair(0U, VT == EVT::i16 ? D16RegisterClass : DPRegisterClass); // Blackfin-specific constraints case 'a': return Pair(0U, PRegisterClass); @@ -585,7 +585,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const { } std::vector<unsigned> BlackfinTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, MVT VT) const { +getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { using namespace BF; if (Constraint.size() != 1) diff --git a/lib/Target/Blackfin/BlackfinISelLowering.h b/lib/Target/Blackfin/BlackfinISelLowering.h index a0e88a952f..1cbb98d1cc 100644 --- a/lib/Target/Blackfin/BlackfinISelLowering.h +++ b/lib/Target/Blackfin/BlackfinISelLowering.h @@ -33,7 +33,7 @@ namespace llvm { int VarArgsFrameOffset; // Frame offset to start of varargs area. public: BlackfinTargetLowering(TargetMachine &TM); - virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const; virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results, @@ -43,10 +43,10 @@ namespace llvm { ConstraintType getConstraintType(const std::string &Constraint) const; std::pair<unsigned, const TargetRegisterClass*> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; + getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; const char *getTargetNodeName(unsigned Opcode) const; unsigned getFunctionAlignment(const Function *F) const; diff --git a/lib/Target/Blackfin/BlackfinInstrInfo.td b/lib/Target/Blackfin/BlackfinInstrInfo.td index b0a2cc13c4..6fc34a8c66 100644 --- a/lib/Target/Blackfin/BlackfinInstrInfo.td +++ b/lib/Target/Blackfin/BlackfinInstrInfo.td @@ -42,21 +42,21 @@ def BfinWrapper: SDNode<"BFISD::Wrapper", SDTIntUnaryOp>; def trailingZeros_xform : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingZeros(), - MVT::i32); + EVT::i32); }]>; def trailingOnes_xform : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant(N->getAPIntValue().countTrailingOnes(), - MVT::i32); + EVT::i32); }]>; def LO16 : SDNodeXForm<imm, [{ - return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), MVT::i16); + return CurDAG->getTargetConstant((unsigned short)N->getZExtValue(), EVT::i16); }]>; def HI16 : SDNodeXForm<imm, [{ // Transformation function: shift the immediate value down into the low bits. - return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, MVT::i16); + return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 16, EVT::i16); }]>; //===----------------------------------------------------------------------===// diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp index 86a955079f..b8fc6acf82 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.cpp +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.cpp @@ -87,7 +87,7 @@ BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const { } const TargetRegisterClass* -BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { +BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the smallest register class of the right type that contains @@ -96,7 +96,7 @@ BlackfinRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) { const TargetRegisterClass* RC = *I; - if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && + if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) && (!BestRC || RC->getNumRegs() < BestRC->getNumRegs())) BestRC = RC; } diff --git a/lib/Target/Blackfin/BlackfinRegisterInfo.h b/lib/Target/Blackfin/BlackfinRegisterInfo.h index 8af65a3ef8..83abc2ef11 100644 --- a/lib/Target/Blackfin/BlackfinRegisterInfo.h +++ b/lib/Target/Blackfin/BlackfinRegisterInfo.h @@ -62,7 +62,7 @@ namespace llvm { } const TargetRegisterClass *getPhysicalRegisterRegClass(unsigned reg, - MVT VT) const; + EVT VT) const; bool hasFP(const MachineFunction &MF) const; diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp index cca52883ff..dd7009f200 100644 --- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp +++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp @@ -103,11 +103,11 @@ namespace { bool isIntS16Immediate(ConstantSDNode *CN, short &Imm) { - MVT vt = CN->getValueType(0); + EVT vt = CN->getValueType(0); Imm = (short) CN->getZExtValue(); - if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) { + if (vt.getSimpleVT() >= EVT::i1 && vt.getSimpleVT() <= EVT::i16) { return true; - } else if (vt == MVT::i32) { + } else if (vt == EVT::i32) { int32_t i_val = (int32_t) CN->getZExtValue(); short s_val = (short) i_val; return i_val == s_val; @@ -132,8 +132,8 @@ namespace { static bool isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm) { - MVT vt = FPN->getValueType(0); - if (vt == MVT::f32) { + EVT vt = FPN->getValueType(0); + if (vt == EVT::f32) { int val = FloatToBits(FPN->getValueAPF().convertToFloat()); int sval = (int) ((val << 16) >> 16); Imm = (short) val; @@ -154,34 +154,34 @@ namespace { } //===------------------------------------------------------------------===// - //! MVT to "useful stuff" mapping structure: + //! EVT to "useful stuff" mapping structure: struct valtype_map_s { - MVT VT; + EVT VT; unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined) bool ldresult_imm; /// LDRESULT instruction requires immediate? unsigned lrinst; /// LR instruction }; const valtype_map_s valtype_map[] = { - { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 }, - { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 }, - { MVT::i32, SPU::ORIr32, true, SPU::LRr32 }, - { MVT::i64, SPU::ORr64, false, SPU::LRr64 }, - { MVT::f32, SPU::ORf32, false, SPU::LRf32 }, - { MVT::f64, SPU::ORf64, false, SPU::LRf64 }, + { EVT::i8, SPU::ORBIr8, true, SPU::LRr8 }, + { EVT::i16, SPU::ORHIr16, true, SPU::LRr16 }, + { EVT::i32, SPU::ORIr32, true, SPU::LRr32 }, + { EVT::i64, SPU::ORr64, false, SPU::LRr64 }, + { EVT::f32, SPU::ORf32, false, SPU::LRf32 }, + { EVT::f64, SPU::ORf64, false, SPU::LRf64 }, // vector types... (sigh!) - { MVT::v16i8, 0, false, SPU::LRv16i8 }, - { MVT::v8i16, 0, false, SPU::LRv8i16 }, - { MVT::v4i32, 0, false, SPU::LRv4i32 }, - { MVT::v2i64, 0, false, SPU::LRv2i64 }, - { MVT::v4f32, 0, false, SPU::LRv4f32 }, - { MVT::v2f64, 0, false, SPU::LRv2f64 } + { EVT::v16i8, 0, false, SPU::LRv16i8 }, + { EVT::v8i16, 0, false, SPU::LRv8i16 }, + { EVT::v4i32, 0, false, SPU::LRv4i32 }, + { EVT::v2i64, 0, false, SPU::LRv2i64 }, + { EVT::v4f32, 0, false, SPU::LRv4f32 }, + { EVT::v2f64, 0, false, SPU::LRv2f64 } }; const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); - const valtype_map_s *getValueTypeMapEntry(MVT VT) + const valtype_map_s *getValueTypeMapEntry(EVT VT) { const valtype_map_s *retval = 0; for (size_t i = 0; i < n_valtype_map; ++i) { @@ -197,7 +197,7 @@ namespace { std::string msg; raw_string_ostream Msg(msg); Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for " - << VT.getMVTString(); + << VT.getEVTString(); llvm_report_error(Msg.str()); } #endif @@ -211,12 +211,12 @@ namespace { // Create the shuffle mask for "rotating" the borrow up one register slot // once the borrow is generated. - ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32)); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, &ShufBytes[0], ShufBytes.size()); } @@ -226,12 +226,12 @@ namespace { // Create the shuffle mask for "rotating" the borrow up one register slot // once the borrow is generated. - ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32)); - ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32)); + ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32)); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, &ShufBytes[0], ShufBytes.size()); } @@ -263,13 +263,13 @@ namespace { /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(uint32_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. inline SDValue getI64Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i64); + return CurDAG->getTargetConstant(Imm, EVT::i64); } /// getSmallIPtrImm - Return a target constant of pointer type. @@ -278,24 +278,24 @@ namespace { } SDNode *emitBuildVector(SDValue build_vec) { - MVT vecVT = build_vec.getValueType(); - MVT eltVT = vecVT.getVectorElementType(); + EVT vecVT = build_vec.getValueType(); + EVT eltVT = vecVT.getVectorElementType(); SDNode *bvNode = build_vec.getNode(); DebugLoc dl = bvNode->getDebugLoc(); // Check to see if this vector can be represented as a CellSPU immediate // constant by invoking all of the instruction selection predicates: - if (((vecVT == MVT::v8i16) && - (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) || - ((vecVT == MVT::v4i32) && - ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || - (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || - (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) || + if (((vecVT == EVT::v8i16) && + (SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i16).getNode() != 0)) || + ((vecVT == EVT::v4i32) && + ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) || + (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) || + (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) || (SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) || - ((vecVT == MVT::v2i64) && - ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || - (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) || - (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0)))) + ((vecVT == EVT::v2i64) && + ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) || + (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) || + (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i64).getNode() != 0)))) return Select(build_vec); // No, need to emit a constant pool spill: @@ -323,19 +323,19 @@ namespace { SDNode *Select(SDValue Op); //! Emit the instruction sequence for i64 shl - SDNode *SelectSHLi64(SDValue &Op, MVT OpVT); + SDNode *SelectSHLi64(SDValue &Op, EVT OpVT); //! Emit the instruction sequence for i64 srl - SDNode *SelectSRLi64(SDValue &Op, MVT OpVT); + SDNode *SelectSRLi64(SDValue &Op, EVT OpVT); //! Emit the instruction sequence for i64 sra - SDNode *SelectSRAi64(SDValue &Op, MVT OpVT); + SDNode *SelectSRAi64(SDValue &Op, EVT OpVT); //! Emit the necessary sequence for loading i64 constants: - SDNode *SelectI64Constant(SDValue &Op, MVT OpVT, DebugLoc dl); + SDNode *SelectI64Constant(SDValue &Op, EVT OpVT, DebugLoc dl); //! Alternate instruction emit sequence for loading i64 constants - SDNode *SelectI64Constant(uint64_t i64const, MVT OpVT, DebugLoc dl); + SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl); //! Returns true if the address N is an A-form (local store) address bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, @@ -434,7 +434,7 @@ bool SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base, SDValue &Index) { // These match the addr256k operand type: - MVT OffsVT = MVT::i16; + EVT OffsVT = EVT::i16; SDValue Zero = CurDAG->getTargetConstant(0, OffsVT); switch (N.getOpcode()) { @@ -514,7 +514,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base, SDValue &Index, int minOffset, int maxOffset) { unsigned Opc = N.getOpcode(); - MVT PtrTy = SPUtli.getPointerTy(); + EVT PtrTy = SPUtli.getPointerTy(); if (Opc == ISD::FrameIndex) { // Stack frame index must be less than 512 (divided by 16): @@ -692,7 +692,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { unsigned Opc = N->getOpcode(); int n_ops = -1; unsigned NewOpc; - MVT OpVT = Op.getValueType(); + EVT OpVT = Op.getValueType(); SDValue Ops[8]; DebugLoc dl = N->getDebugLoc(); @@ -717,45 +717,45 @@ SPUDAGToDAGISel::Select(SDValue Op) { TFI, Imm0), 0); n_ops = 2; } - } else if (Opc == ISD::Constant && OpVT == MVT::i64) { + } else if (Opc == ISD::Constant && OpVT == EVT::i64) { // Catch the i64 constants that end up here. Note: The backend doesn't // attempt to legalize the constant (it's useless because DAGCombiner // will insert 64-bit constants and we can't stop it). return SelectI64Constant(Op, OpVT, Op.getDebugLoc()); } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) - && OpVT == MVT::i64) { + && OpVT == EVT::i64) { SDValue Op0 = Op.getOperand(0); - MVT Op0VT = Op0.getValueType(); - MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits())); - MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); + EVT Op0VT = Op0.getValueType(); + EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits())); + EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); SDValue shufMask; switch (Op0VT.getSimpleVT()) { default: - llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT"); + llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT"); /*NOTREACHED*/ - case MVT::i32: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x00010203, MVT::i32), - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x08090a0b, MVT::i32)); + case EVT::i32: + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x00010203, EVT::i32), + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x08090a0b, EVT::i32)); break; - case MVT::i16: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x80800203, MVT::i32), - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x80800a0b, MVT::i32)); + case EVT::i16: + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x80800203, EVT::i32), + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x80800a0b, EVT::i32)); break; - case MVT::i8: - shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x80808003, MVT::i32), - CurDAG->getConstant(0x80808080, MVT::i32), - CurDAG->getConstant(0x8080800b, MVT::i32)); + case EVT::i8: + shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x80808003, EVT::i32), + CurDAG->getConstant(0x80808080, EVT::i32), + CurDAG->getConstant(0x8080800b, EVT::i32)); break; } @@ -775,21 +775,21 @@ SPUDAGToDAGISel::Select(SDValue Op) { SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle)); return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT, zextShuffle)); - } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { + } else if (Opc == ISD::ADD && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) { SDNode *CGLoad = emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl)); return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); - } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { + } else if (Opc == ISD::SUB && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) { SDNode *CGLoad = emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl)); return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT, Op.getOperand(0), Op.getOperand(1), SDValue(CGLoad, 0))); - } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) { + } else if (Opc == ISD::MUL && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) { SDNode *CGLoad = emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl)); @@ -799,8 +799,8 @@ SPUDAGToDAGISel::Select(SDValue Op) { } else if (Opc == ISD::TRUNCATE) { SDValue Op0 = Op.getOperand(0); if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL) - && OpVT == MVT::i32 - && Op0.getValueType() == MVT::i64) { + && OpVT == EVT::i32 + && Op0.getValueType() == EVT::i64) { // Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32 // // Take advantage of the fact that the upper 32 bits are in the @@ -817,7 +817,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { shift_amt -= 32; if (shift_amt > 0) { // Take care of the additional shift, if present: - SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32); + SDValue shift = CurDAG->getTargetConstant(shift_amt, EVT::i32); unsigned Opc = SPU::ROTMAIr32_i32; if (Op0.getOpcode() == ISD::SRL) @@ -832,19 +832,19 @@ SPUDAGToDAGISel::Select(SDValue Op) { } } } else if (Opc == ISD::SHL) { - if (OpVT == MVT::i64) { + if (OpVT == EVT::i64) { return SelectSHLi64(Op, OpVT); } } else if (Opc == ISD::SRL) { - if (OpVT == MVT::i64) { + if (OpVT == EVT::i64) { return SelectSRLi64(Op, OpVT); } } else if (Opc == ISD::SRA) { - if (OpVT == MVT::i64) { + if (OpVT == EVT::i64) { return SelectSRAi64(Op, OpVT); } } else if (Opc == ISD::FNEG - && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) { + && (OpVT == EVT::f64 || OpVT == EVT::v2f64)) { DebugLoc dl = Op.getDebugLoc(); // Check if the pattern is a special form of DFNMS: // (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC)) @@ -853,7 +853,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { SDValue Op00 = Op0.getOperand(0); if (Op00.getOpcode() == ISD::FMUL) { unsigned Opc = SPU::DFNMSf64; - if (OpVT == MVT::v2f64) + if (OpVT == EVT::v2f64) Opc = SPU::DFNMSv2f64; return CurDAG->getTargetNode(Opc, dl, OpVT, @@ -863,29 +863,29 @@ SPUDAGToDAGISel::Select(SDValue Op) { } } - SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64); + SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, EVT::i64); SDNode *signMask = 0; unsigned Opc = SPU::XORfneg64; - if (OpVT == MVT::f64) { - signMask = SelectI64Constant(negConst, MVT::i64, dl); - } else if (OpVT == MVT::v2f64) { + if (OpVT == EVT::f64) { + signMask = SelectI64Constant(negConst, EVT::i64, dl); + } else if (OpVT == EVT::v2f64) { Opc = SPU::XORfnegvec; signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl, - MVT::v2i64, + EVT::v2i64, negConst, negConst)); } return CurDAG->getTargetNode(Opc, dl, OpVT, Op.getOperand(0), SDValue(signMask, 0)); } else if (Opc == ISD::FABS) { - if (OpVT == MVT::f64) { - SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl); + if (OpVT == EVT::f64) { + SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, EVT::i64, dl); return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT, Op.getOperand(0), SDValue(signMask, 0)); - } else if (OpVT == MVT::v2f64) { - SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64); - SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, + } else if (OpVT == EVT::v2f64) { + SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, EVT::i64); + SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, absConst, absConst); SDNode *signMask = emitBuildVector(absVec); return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT, @@ -893,7 +893,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { } } else if (Opc == SPUISD::LDRESULT) { // Custom select instructions for LDRESULT - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); SDValue Arg = N->getOperand(0); SDValue Chain = N->getOperand(1); SDNode *Result; @@ -903,7 +903,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { std::string msg; raw_string_ostream Msg(msg); Msg << "LDRESULT for unsupported type: " - << VT.getMVTString(); + << VT.getEVTString(); llvm_report_error(Msg.str()); } @@ -911,9 +911,9 @@ SPUDAGToDAGISel::Select(SDValue Op) { if (vtm->ldresult_imm) { SDValue Zero = CurDAG->getTargetConstant(0, VT); - Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Zero, Chain); } else { - Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain); + Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Arg, Chain); } return Result; @@ -924,7 +924,7 @@ SPUDAGToDAGISel::Select(SDValue Op) { // SPUInstrInfo catches the following patterns: // (SPUindirect (SPUhi ...), (SPUlo ...)) // (SPUindirect $sp, imm) - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue Op0 = N->getOperand(0); SDValue Op1 = N->getOperand(1); RegisterSDNode *RN; @@ -967,17 +967,17 @@ SPUDAGToDAGISel::Select(SDValue Op) { * @return The SDNode with the entire instruction sequence */ SDNode * -SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) { +SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) { SDValue Op0 = Op.getOperand(0); - MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); + EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); SDValue ShiftAmt = Op.getOperand(1); - MVT ShiftAmtVT = ShiftAmt.getValueType(); + EVT ShiftAmtVT = ShiftAmt.getValueType(); SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0; SDValue SelMaskVal; DebugLoc dl = Op.getDebugLoc(); VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0); - SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16); + SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, EVT::i16); SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal); ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT, CurDAG->getTargetConstant(0, OpVT)); @@ -1032,11 +1032,11 @@ SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) { * @return The SDNode with the entire instruction sequence */ SDNode * -SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) { +SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) { SDValue Op0 = Op.getOperand(0); - MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); + EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); SDValue ShiftAmt = Op.getOperand(1); - MVT ShiftAmtVT = ShiftAmt.getValueType(); + EVT ShiftAmtVT = ShiftAmt.getValueType(); SDNode *VecOp0, *Shift = 0; DebugLoc dl = Op.getDebugLoc(); @@ -1098,11 +1098,11 @@ SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) { * @return The SDNode with the entire instruction sequence */ SDNode * -SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) { +SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) { // Promote Op0 to vector - MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); + EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits())); SDValue ShiftAmt = Op.getOperand(1); - MVT ShiftAmtVT = ShiftAmt.getValueType(); + EVT ShiftAmtVT = ShiftAmt.getValueType(); DebugLoc dl = Op.getDebugLoc(); SDNode *VecOp0 = @@ -1110,16 +1110,16 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) { SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT); SDNode *SignRot = - CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64, + CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, EVT::v2i64, SDValue(VecOp0, 0), SignRotAmt); SDNode *UpperHalfSign = - CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0)); + CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, EVT::i32, SDValue(SignRot, 0)); SDNode *UpperHalfSignMask = CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0)); SDNode *UpperLowerMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, - CurDAG->getTargetConstant(0xff00ULL, MVT::i16)); + CurDAG->getTargetConstant(0xff00ULL, EVT::i16)); SDNode *UpperLowerSelect = CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT, SDValue(UpperHalfSignMask, 0), @@ -1166,15 +1166,15 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) { /*! Do the necessary magic necessary to load a i64 constant */ -SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT, +SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, EVT OpVT, DebugLoc dl) { ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode()); return SelectI64Constant(CN->getZExtValue(), OpVT, dl); } -SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT, +SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT, DebugLoc dl) { - MVT OpVecVT = MVT::getVectorVT(OpVT, 2); + EVT OpVecVT = EVT::getVectorVT(OpVT, 2); SDValue i64vec = SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl); diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp index 5cf9afe0f7..5c80324011 100644 --- a/lib/Target/CellSPU/SPUISelLowering.cpp +++ b/lib/Target/CellSPU/SPUISelLowering.cpp @@ -40,26 +40,26 @@ using namespace llvm; namespace { std::map<unsigned, const char *> node_names; - //! MVT mapping to useful data for Cell SPU + //! EVT mapping to useful data for Cell SPU struct valtype_map_s { - const MVT valtype; + const EVT valtype; const int prefslot_byte; }; const valtype_map_s valtype_map[] = { - { MVT::i1, 3 }, - { MVT::i8, 3 }, - { MVT::i16, 2 }, - { MVT::i32, 0 }, - { MVT::f32, 0 }, - { MVT::i64, 0 }, - { MVT::f64, 0 }, - { MVT::i128, 0 } + { EVT::i1, 3 }, + { EVT::i8, 3 }, + { EVT::i16, 2 }, + { EVT::i32, 0 }, + { EVT::f32, 0 }, + { EVT::i64, 0 }, + { EVT::f64, 0 }, + { EVT::i128, 0 } }; const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]); - const valtype_map_s *getValueTypeMapEntry(MVT VT) { + const valtype_map_s *getValueTypeMapEntry(EVT VT) { const valtype_map_s *retval = 0; for (size_t i = 0; i < n_valtype_map; ++i) { @@ -74,7 +74,7 @@ namespace { std::string msg; raw_string_ostream Msg(msg); Msg << "getValueTypeMapEntry returns NULL for " - << VT.getMVTString(); + << VT.getEVTString(); llvm_report_error(Msg.str()); } #endif @@ -100,8 +100,8 @@ namespace { TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; for (unsigned i = 0, e = Op.getNumOperands(); i != e; ++i) { - MVT ArgVT = Op.getOperand(i).getValueType(); - const Type *ArgTy = ArgVT.getTypeForMVT(); + EVT ArgVT = Op.getOperand(i).getValueType(); + const Type *ArgTy = ArgVT.getTypeForEVT(); Entry.Node = Op.getOperand(i); Entry.Ty = ArgTy; Entry.isSExt = isSigned; @@ -112,7 +112,7 @@ namespace { TLI.getPointerTy()); // Splice the libcall in wherever FindInputOutputChains tells us to. - const Type *RetTy = Op.getNode()->getValueType(0).getTypeForMVT(); + const Type *RetTy = Op.getNode()->getValueType(0).getTypeForEVT(); std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false, 0, CallingConv::C, false, @@ -138,37 +138,37 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setLibcallName(RTLIB::DIV_F64, "__fast_divdf3"); // Set up the SPU's register classes: - addRegisterClass(MVT::i8, SPU::R8CRegisterClass); - addRegisterClass(MVT::i16, SPU::R16CRegisterClass); - addRegisterClass(MVT::i32, SPU::R32CRegisterClass); - addRegisterClass(MVT::i64, SPU::R64CRegisterClass); - addRegisterClass(MVT::f32, SPU::R32FPRegisterClass); - addRegisterClass(MVT::f64, SPU::R64FPRegisterClass); - addRegisterClass(MVT::i128, SPU::GPRCRegisterClass); + addRegisterClass(EVT::i8, SPU::R8CRegisterClass); + addRegisterClass(EVT::i16, SPU::R16CRegisterClass); + addRegisterClass(EVT::i32, SPU::R32CRegisterClass); + addRegisterClass(EVT::i64, SPU::R64CRegisterClass); + addRegisterClass(EVT::f32, SPU::R32FPRegisterClass); + addRegisterClass(EVT::f64, SPU::R64FPRegisterClass); + addRegisterClass(EVT::i128, SPU::GPRCRegisterClass); // SPU has no sign or zero extended loads for i1, i8, i16: - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); - setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand); - setTruncStoreAction(MVT::i128, MVT::i64, Expand); - setTruncStoreAction(MVT::i128, MVT::i32, Expand); - setTruncStoreAction(MVT::i128, MVT::i16, Expand); - setTruncStoreAction(MVT::i128, MVT::i8, Expand); + setTruncStoreAction(EVT::i128, EVT::i64, Expand); + setTruncStoreAction(EVT::i128, EVT::i32, Expand); + setTruncStoreAction(EVT::i128, EVT::i16, Expand); + setTruncStoreAction(EVT::i128, EVT::i8, Expand); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); // SPU constant load actions are custom lowered: - setOperationAction(ISD::ConstantFP, MVT::f32, Legal); - setOperationAction(ISD::ConstantFP, MVT::f64, Custom); + setOperationAction(ISD::ConstantFP, EVT::f32, Legal); + setOperationAction(ISD::ConstantFP, EVT::f64, Custom); // SPU's loads and stores have to be custom lowered: - for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::i128; + for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::i128; ++sctype) { - MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype; + EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype; setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::STORE, VT, Custom); @@ -176,222 +176,222 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setLoadExtAction(ISD::ZEXTLOAD, VT, Custom); setLoadExtAction(ISD::SEXTLOAD, VT, Custom); - for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::i8; --stype) { - MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype; + for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::i8; --stype) { + EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype; setTruncStoreAction(VT, StoreVT, Expand); } } - for (unsigned sctype = (unsigned) MVT::f32; sctype < (unsigned) MVT::f64; + for (unsigned sctype = (unsigned) EVT::f32; sctype < (unsigned) EVT::f64; ++sctype) { - MVT::SimpleValueType VT = (MVT::SimpleValueType) sctype; + EVT::SimpleValueType VT = (EVT::SimpleValueType) sctype; setOperationAction(ISD::LOAD, VT, Custom); setOperationAction(ISD::STORE, VT, Custom); - for (unsigned stype = sctype - 1; stype >= (unsigned) MVT::f32; --stype) { - MVT::SimpleValueType StoreVT = (MVT::SimpleValueType) stype; + for (unsigned stype = sctype - 1; stype >= (unsigned) EVT::f32; --stype) { + EVT::SimpleValueType StoreVT = (EVT::SimpleValueType) stype; setTruncStoreAction(VT, StoreVT, Expand); } } // Expand the jumptable branches - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::Other, Expand); // Custom lower SELECT_CC for most cases, but expand by default - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); + setOperationAction(ISD::SELECT_CC, EVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::i8, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i16, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i64, Custom); // SPU has no intrinsics for these particular operations: - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand); // SPU has no division/remainder instructions - setOperationAction(ISD::SREM, MVT::i8, Expand); - setOperationAction(ISD::UREM, MVT::i8, Expand); - setOperationAction(ISD::SDIV, MVT::i8, Expand); - setOperationAction(ISD::UDIV, MVT::i8, Expand); - setOperationAction(ISD::SDIVREM, MVT::i8, Expand); - setOperationAction(ISD::UDIVREM, MVT::i8, Expand); - setOperationAction(ISD::SREM, MVT::i16, Expand); - setOperationAction(ISD::UREM, MVT::i16, Expand); - setOperationAction(ISD::SDIV, MVT::i16, Expand); - setOperationAction(ISD::UDIV, MVT::i16, Expand); - setOperationAction(ISD::SDIVREM, MVT::i16, Expand); - setOperationAction(ISD::UDIVREM, MVT::i16, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i64, Expand); - setOperationAction(ISD::UREM, MVT::i64, Expand); - setOperationAction(ISD::SDIV, MVT::i64, Expand); - setOperationAction(ISD::UDIV, MVT::i64, Expand); - setOperationAction(ISD::SDIVREM, MVT::i64, Expand); - setOperationAction(ISD::UDIVREM, MVT::i64, Expand); - setOperationAction(ISD::SREM, MVT::i128, Expand); - setOperationAction(ISD::UREM, MVT::i128, Expand); - setOperationAction(ISD::SDIV, MVT::i128, Expand); - setOperationAction(ISD::UDIV, MVT::i128, Expand); - setOperationAction(ISD::SDIVREM, MVT::i128, Expand); - setOperationAction(ISD::UDIVREM, MVT::i128, Expand); + setOperationAction(ISD::SREM, EVT::i8, Expand); + setOperationAction(ISD::UREM, EVT::i8, Expand); + setOperationAction(ISD::SDIV, EVT::i8, Expand); + setOperationAction(ISD::UDIV, EVT::i8, Expand); + setOperationAction(ISD::SDIVREM, EVT::i8, Expand); + setOperationAction(ISD::UDIVREM, EVT::i8, Expand); + setOperationAction(ISD::SREM, EVT::i16, Expand); + setOperationAction(ISD::UREM, EVT::i16, Expand); + setOperationAction(ISD::SDIV, EVT::i16, Expand); + setOperationAction(ISD::UDIV, EVT::i16, Expand); + setOperationAction(ISD::SDIVREM, EVT::i16, Expand); + setOperationAction(ISD::UDIVREM, EVT::i16, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + setOperationAction(ISD::SDIV, EVT::i32, Expand); + setOperationAction(ISD::UDIV, EVT::i32, Expand); + setOperationAction(ISD::SDIVREM, EVT::i32, Expand); + setOperationAction(ISD::UDIVREM, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i64, Expand); + setOperationAction(ISD::UREM, EVT::i64, Expand); + setOperationAction(ISD::SDIV, EVT::i64, Expand); + setOperationAction(ISD::UDIV, EVT::i64, Expand); + setOperationAction(ISD::SDIVREM, EVT::i64, Expand); + setOperationAction(ISD::UDIVREM, EVT::i64, Expand); + setOperationAction(ISD::SREM, EVT::i128, Expand); + setOperationAction(ISD::UREM, EVT::i128, Expand); + setOperationAction(ISD::SDIV, EVT::i128, Expand); + setOperationAction(ISD::UDIV, EVT::i128, Expand); + setOperationAction(ISD::SDIVREM, EVT::i128, Expand); + setOperationAction(ISD::UDIVREM, EVT::i128, Expand); // We don't support sin/cos/sqrt/fmod - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); + setOperationAction(ISD::FSIN , EVT::f64, Expand); + setOperationAction(ISD::FCOS , EVT::f64, Expand); + setOperationAction(ISD::FREM , EVT::f64, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); + setOperationAction(ISD::FREM , EVT::f32, Expand); // Expand fsqrt to the appropriate libcall (NOTE: should use h/w fsqrt // for f32!) - setOperationAction(ISD::FSQRT, MVT::f64, Expand); - setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FSQRT, EVT::f64, Expand); + setOperationAction(ISD::FSQRT, EVT::f32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand); // SPU can do rotate right and left, so legalize it... but customize for i8 // because instructions don't exist. // FIXME: Change from "expand" to appropriate type once ROTR is supported in // .td files. - setOperationAction(ISD::ROTR, MVT::i32, Expand /*Legal*/); - setOperationAction(ISD::ROTR, MVT::i16, Expand /*Legal*/); - setOperationAction(ISD::ROTR, MVT::i8, Expand /*Custom*/); + setOperationAction(ISD::ROTR, EVT::i32, Expand /*Legal*/); + setOperationAction(ISD::ROTR, EVT::i16, Expand /*Legal*/); + setOperationAction(ISD::ROTR, EVT::i8, Expand /*Custom*/); - setOperationAction(ISD::ROTL, MVT::i32, Legal); - setOperationAction(ISD::ROTL, MVT::i16, Legal); - setOperationAction(ISD::ROTL, MVT::i8, Custom); + setOperationAction(ISD::ROTL, EVT::i32, Legal); + setOperationAction(ISD::ROTL, EVT::i16, Legal); + setOperationAction(ISD::ROTL, EVT::i8, Custom); // SPU has no native version of shift left/right for i8 - setOperationAction(ISD::SHL, MVT::i8, Custom); - setOperationAction(ISD::SRL, MVT::i8, Custom); - setOperationAction(ISD::SRA, MVT::i8, Custom); + setOperationAction(ISD::SHL, EVT::i8, Custom); + setOperationAction(ISD::SRL, EVT::i8, Custom); + setOperationAction(ISD::SRA, EVT::i8, Custom); // Make these operations legal and handle them during instruction selection: - setOperationAction(ISD::SHL, MVT::i64, Legal); - setOperationAction(ISD::SRL, MVT::i64, Legal); - setOperationAction(ISD::SRA, MVT::i64, Legal); + setOperationAction(ISD::SHL, EVT::i64, Legal); + setOperationAction(ISD::SRL, EVT::i64, Legal); + setOperationAction(ISD::SRA, EVT::i64, Legal); // Custom lower i8, i32 and i64 multiplications - setOperationAction(ISD::MUL, MVT::i8, Custom); - setOperationAction(ISD::MUL, MVT::i32, Legal); - setOperationAction(ISD::MUL, MVT::i64, Legal); + setOperationAction(ISD::MUL, EVT::i8, Custom); + setOperationAction(ISD::MUL, EVT::i32, Legal); + setOperationAction(ISD::MUL, EVT::i64, Legal); // Expand double-width multiplication // FIXME: It would probably be reasonable to support some of these operations - setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); - setOperationAction(ISD::MULHU, MVT::i8, Expand); - setOperationAction(ISD::MULHS, MVT::i8, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); - setOperationAction(ISD::MULHU, MVT::i16, Expand); - setOperationAction(ISD::MULHS, MVT::i16, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); - setOperationAction(ISD::MULHS, MVT::i32, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::MULHU, MVT::i64, Expand); - setOperationAction(ISD::MULHS, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand); + setOperationAction(ISD::MULHU, EVT::i8, Expand); + setOperationAction(ISD::MULHS, EVT::i8, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand); + setOperationAction(ISD::MULHU, EVT::i16, Expand); + setOperationAction(ISD::MULHS, EVT::i16, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::MULHU, EVT::i32, Expand); + setOperationAction(ISD::MULHS, EVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand); + setOperationAction(ISD::MULHU, EVT::i64, Expand); + setOperationAction(ISD::MULHS, EVT::i64, Expand); // Need to custom handle (some) common i8, i64 math ops - setOperationAction(ISD::ADD, MVT::i8, Custom); - setOperationAction(ISD::ADD, MVT::i64, Legal); - setOperationAction(ISD::SUB, MVT::i8, Custom); - setOperationAction(ISD::SUB, MVT::i64, Legal); + setOperationAction(ISD::ADD, EVT::i8, Custom); + setOperationAction(ISD::ADD, EVT::i64, Legal); + setOperationAction(ISD::SUB, EVT::i8, Custom); + setOperationAction(ISD::SUB, EVT::i64, Legal); // SPU does not have BSWAP. It does have i32 support CTLZ. // CTPOP has to be custom lowered. - setOperationAction(ISD::BSWAP, MVT::i32, Expand); - setOperationAction(ISD::BSWAP, MVT::i64, Expand); - - setOperationAction(ISD::CTPOP, MVT::i8, Custom); - setOperationAction(ISD::CTPOP, MVT::i16, Custom); - setOperationAction(ISD::CTPOP, MVT::i32, Custom); - setOperationAction(ISD::CTPOP, MVT::i64, Custom); - setOperationAction(ISD::CTPOP, MVT::i128, Expand); - - setOperationAction(ISD::CTTZ , MVT::i8, Expand); - setOperationAction(ISD::CTTZ , MVT::i16, Expand); - setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTTZ , MVT::i64, Expand); - setOperationAction(ISD::CTTZ , MVT::i128, Expand); - - setOperationAction(ISD::CTLZ , MVT::i8, Promote); - setOperationAction(ISD::CTLZ , MVT::i16, Promote); - setOperationAction(ISD::CTLZ , MVT::i32, Legal); - setOperationAction(ISD::CTLZ , MVT::i64, Expand); - setOperationAction(ISD::CTLZ , MVT::i128, Expand); + setOperationAction(ISD::BSWAP, EVT::i32, Expand); + setOperationAction(ISD::BSWAP, EVT::i64, Expand); + + setOperationAction(ISD::CTPOP, EVT::i8, Custom); + setOperationAction(ISD::CTPOP, EVT::i16, Custom); + setOperationAction(ISD::CTPOP, EVT::i32, Custom); + setOperationAction(ISD::CTPOP, EVT::i64, Custom); + setOperationAction(ISD::CTPOP, EVT::i128, Expand); + + setOperationAction(ISD::CTTZ , EVT::i8, Expand); + setOperationAction(ISD::CTTZ , EVT::i16, Expand); + setOperationAction(ISD::CTTZ , EVT::i32, Expand); + setOperationAction(ISD::CTTZ , EVT::i64, Expand); + setOperationAction(ISD::CTTZ , EVT::i128, Expand); + + setOperationAction(ISD::CTLZ , EVT::i8, Promote); + setOperationAction(ISD::CTLZ , EVT::i16, Promote); + setOperationAction(ISD::CTLZ , EVT::i32, Legal); + setOperationAction(ISD::CTLZ , EVT::i64, Expand); + setOperationAction(ISD::CTLZ , EVT::i128, Expand); // SPU has a version of select that implements (a&~c)|(b&c), just like // select ought to work: - setOperationAction(ISD::SELECT, MVT::i8, Legal); - setOperationAction(ISD::SELECT, MVT::i16, Legal); - setOperationAction(ISD::SELECT, MVT::i32, Legal); - setOperationAction(ISD::SELECT, MVT::i64, Legal); + setOperationAction(ISD::SELECT, EVT::i8, Legal); + setOperationAction(ISD::SELECT, EVT::i16, Legal); + setOperationAction(ISD::SELECT, EVT::i32, Legal); + setOperationAction(ISD::SELECT, EVT::i64, Legal); - setOperationAction(ISD::SETCC, MVT::i8, Legal); - setOperationAction(ISD::SETCC, MVT::i16, Legal); - setOperationAction(ISD::SETCC, MVT::i32, Legal); - setOperationAction(ISD::SETCC, MVT::i64, Legal); - setOperationAction(ISD::SETCC, MVT::f64, Custom); + setOperationAction(ISD::SETCC, EVT::i8, Legal); + setOperationAction(ISD::SETCC, EVT::i16, Legal); + setOperationAction(ISD::SETCC, EVT::i32, Legal); + setOperationAction(ISD::SETCC, EVT::i64, Legal); + setOperationAction(ISD::SETCC, EVT::f64, Custom); // Custom lower i128 -> i64 truncates - setOperationAction(ISD::TRUNCATE, MVT::i64, Custom); + setOperationAction(ISD::TRUNCATE, EVT::i64, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::i8, Promote); - setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote); - setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote); - setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote); + setOperationAction(ISD::FP_TO_SINT, EVT::i8, Promote); + setOperationAction(ISD::FP_TO_UINT, EVT::i8, Promote); + setOperationAction(ISD::FP_TO_SINT, EVT::i16, Promote); + setOperationAction(ISD::FP_TO_UINT, EVT::i16, Promote); // SPU has a legal FP -> signed INT instruction for f32, but for f64, need // to expand to a libcall, hence the custom lowering: - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_SINT, MVT::i128, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i128, Expand); + setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand); + setOperationAction(ISD::FP_TO_SINT, EVT::i128, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i128, Expand); // FDIV on SPU requires custom lowering - setOperationAction(ISD::FDIV, MVT::f64, Expand); // to libcall + setOperationAction(ISD::FDIV, EVT::f64, Expand); // to libcall // SPU has [U|S]INT_TO_FP for f32->i32, but not for f64->i32, f64->i64: - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote); - setOperationAction(ISD::SINT_TO_FP, MVT::i8, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote); - setOperationAction(ISD::UINT_TO_FP, MVT::i8, Promote); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom); - - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal); - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal); - setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal); - setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal); + setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom); + setOperationAction(ISD::SINT_TO_FP, EVT::i16, Promote); + setOperationAction(ISD::SINT_TO_FP, EVT::i8, Promote); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Custom); + setOperationAction(ISD::UINT_TO_FP, EVT::i16, Promote); + setOperationAction(ISD::UINT_TO_FP, EVT::i8, Promote); + setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom); + setOperationAction(ISD::UINT_TO_FP, EVT::i64, Custom); + + setOperationAction(ISD::BIT_CONVERT, EVT::i32, Legal); + setOperationAction(ISD::BIT_CONVERT, EVT::f32, Legal); + setOperationAction(ISD::BIT_CONVERT, EVT::i64, Legal); + setOperationAction(ISD::BIT_CONVERT, EVT::f64, Legal); // We cannot sextinreg(i1). Expand to shifts. - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); // We want to legalize GlobalAddress and ConstantPool nodes into the // appropriate instructions to materialize the address. - for (unsigned sctype = (unsigned) MVT::i8; sctype < (unsigned) MVT::f128; + for (unsigned sctype = (unsigned) EVT::i8; sctype < (unsigned) EVT::f128; ++sctype) { - MVT::SimpleValueType VT = (MVT::SimpleValueType)sctype; + EVT::SimpleValueType VT = (EVT::SimpleValueType)sctype; setOperationAction(ISD::GlobalAddress, VT, Custom); setOperationAction(ISD::ConstantPool, VT, Custom); @@ -399,42 +399,42 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) } // VASTART needs to be custom lowered to use the VarArgsFrameIndex - setOperationAction(ISD::VASTART , MVT::Other, Custom); + setOperationAction(ISD::VASTART , EVT::Other, Custom); // Use the default implementation. - setOperationAction(ISD::VAARG , MVT::Other, Expand); - setOperationAction(ISD::VACOPY , MVT::Other, Expand); - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand); + setOperationAction(ISD::VAARG , EVT::Other, Expand); + setOperationAction(ISD::VACOPY , EVT::Other, Expand); + setOperationAction(ISD::VAEND , EVT::Other, Expand); + setOperationAction(ISD::STACKSAVE , EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Expand); // Cell SPU has instructions for converting between i64 and fp. - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom); + setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom); // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Promote); // BUILD_PAIR can't be handled natively, and should be expanded to shl/or - setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); + setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand); // First set operation action for all vector types to expand. Then we // will selectively turn on ones that can be effectively codegen'd. - addRegisterClass(MVT::v16i8, SPU::VECREGRegisterClass); - addRegisterClass(MVT::v8i16, SPU::VECREGRegisterClass); - addRegisterClass(MVT::v4i32, SPU::VECREGRegisterClass); - addRegisterClass(MVT::v2i64, SPU::VECREGRegisterClass); - addRegisterClass(MVT::v4f32, SPU::VECREGRegisterClass); - addRegisterClass(MVT::v2f64, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v16i8, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v8i16, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v4i32, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v2i64, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v4f32, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v2f64, SPU::VECREGRegisterClass); // "Odd size" vector classes that we're willing to support: - addRegisterClass(MVT::v2i32, SPU::VECREGRegisterClass); + addRegisterClass(EVT::v2i32, SPU::VECREGRegisterClass); - for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { - MVT::SimpleValueType VT = (MVT::SimpleValueType)i; + for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) { + EVT::SimpleValueType VT = (EVT::SimpleValueType)i; // add/sub are legal for all supported vector VT's. setOperationAction(ISD::ADD, VT, Legal); @@ -465,14 +465,14 @@ SPUTargetLowering::SPUTargetLowering(SPUTargetMachine &TM) setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); } - setOperationAction(ISD::AND, MVT::v16i8, Custom); - setOperationAction(ISD::OR, MVT::v16i8, Custom); - setOperationAction(ISD::XOR, MVT::v16i8, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); + setOperationAction(ISD::AND, EVT::v16i8, Custom); + setOperationAction(ISD::OR, EVT::v16i8, Custom); + setOperationAction(ISD::XOR, EVT::v16i8, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom); - setOperationAction(ISD::FDIV, MVT::v4f32, Legal); + setOperationAction(ISD::FDIV, EVT::v4f32, Legal); - setShiftAmountType(MVT::i32); + setShiftAmountType(EVT::i32); setBooleanContents(ZeroOrNegativeOneBooleanContent); setStackPointerRegisterToSaveRestore(SPU::R1); @@ -539,11 +539,11 @@ unsigned SPUTargetLowering::getFunctionAlignment(const Function *) const { // Return the Cell SPU's SETCC result type //===----------------------------------------------------------------------===// -MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(MVT VT) const { +EVT::SimpleValueType SPUTargetLowering::getSetCCResultType(EVT VT) const { // i16 and i32 are valid SETCC result types - return ((VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) ? + return ((VT == EVT::i8 || VT == EVT::i16 || VT == EVT::i32) ? VT.getSimpleVT() : - MVT::i32); + EVT::i32); } //===----------------------------------------------------------------------===// @@ -562,7 +562,7 @@ MVT::SimpleValueType SPUTargetLowering::getSetCCResultType(MVT VT) const { within a 16-byte block, we have to rotate to extract the requested element. For extending loads, we also want to ensure that the following sequence is - emitted, e.g. for MVT::f32 extending load to MVT::f64: + emitted, e.g. for EVT::f32 extending load to EVT::f64: \verbatim %1 v16i8,ch = load @@ -576,9 +576,9 @@ static SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { LoadSDNode *LN = cast<LoadSDNode>(Op); SDValue the_chain = LN->getChain(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - MVT InVT = LN->getMemoryVT(); - MVT OutVT = Op.getValueType(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT InVT = LN->getMemoryVT(); + EVT OutVT = Op.getValueType(); ISD::LoadExtType ExtType = LN->getExtensionType(); unsigned alignment = LN->getAlignment(); const valtype_map_s *vtm = getValueTypeMapEntry(InVT); @@ -604,7 +604,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { if (rotamt < 0) rotamt += 16; - rotate = DAG.getConstant(rotamt, MVT::i16); + rotate = DAG.getConstant(rotamt, EVT::i16); // Simplify the base pointer for this case: basePtr = basePtr.getOperand(0); @@ -622,7 +622,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { int64_t rotamt = -vtm->prefslot_byte; if (rotamt < 0) rotamt += 16; - rotate = DAG.getConstant(rotamt, MVT::i16); + rotate = DAG.getConstant(rotamt, EVT::i16); } else { // Offset the rotate amount by the basePtr and the preferred slot // byte offset @@ -670,7 +670,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } // Re-emit as a v16i8 vector load - result = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, + result = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), LN->isVolatile(), 16); @@ -678,12 +678,12 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { the_chain = result.getValue(1); // Rotate into the preferred slot: - result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, MVT::v16i8, + result = DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, EVT::v16i8, result.getValue(0), rotate); // Convert the loaded v16i8 vector to the appropriate vector type // specified by the operand: - MVT vecVT = MVT::getVectorVT(InVT, (128 / InVT.getSizeInBits())); + EVT vecVT = EVT::getVectorVT(InVT, (128 / InVT.getSizeInBits())); result = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, InVT, DAG.getNode(ISD::BIT_CONVERT, dl, vecVT, result)); @@ -701,7 +701,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { result = DAG.getNode(NewOpc, dl, OutVT, result); } - SDVTList retvts = DAG.getVTList(OutVT, MVT::Other); + SDVTList retvts = DAG.getVTList(OutVT, EVT::Other); SDValue retops[2] = { result, the_chain @@ -740,17 +740,17 @@ static SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { StoreSDNode *SN = cast<StoreSDNode>(Op); SDValue Value = SN->getValue(); - MVT VT = Value.getValueType(); - MVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT VT = Value.getValueType(); + EVT StVT = (!SN->isTruncatingStore() ? VT : SN->getMemoryVT()); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); DebugLoc dl = Op.getDebugLoc(); unsigned alignment = SN->getAlignment(); switch (SN->getAddressingMode()) { case ISD::UNINDEXED: { // The vector type we really want to load from the 16-byte chunk. - MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())), - stVecVT = MVT::getVectorVT(StVT, (128 / StVT.getSizeInBits())); + EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())), + stVecVT = EVT::getVectorVT(StVT, (128 / StVT.getSizeInBits())); SDValue alignLoadVec; SDValue basePtr = SN->getBasePtr(); @@ -820,7 +820,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { } // Re-emit as a v16i8 vector load - alignLoadVec = DAG.getLoad(MVT::v16i8, dl, the_chain, basePtr, + alignLoadVec = DAG.getLoad(EVT::v16i8, dl, the_chain, basePtr, SN->getSrcValue(), SN->getSrcValueOffset(), SN->isVolatile(), 16); @@ -859,7 +859,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { result = DAG.getNode(SPUISD::SHUFB, dl, vecVT, vectorizeOp, alignLoadVec, DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::v4i32, insertEltOp)); + EVT::v4i32, insertEltOp)); result = DAG.getStore(the_chain, dl, result, basePtr, LN->getSrcValue(), LN->getSrcValueOffset(), @@ -902,7 +902,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { //! Generate the address of a constant pool entry. static SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); @@ -935,7 +935,7 @@ SPU::LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); @@ -960,7 +960,7 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { static SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); @@ -989,21 +989,21 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) { //! Custom lower double precision floating point constants static SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); // FIXME there is no actual debug info here DebugLoc dl = Op.getDebugLoc(); - if (VT == MVT::f64) { + if (VT == EVT::f64) { ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode()); assert((FP != 0) && "LowerConstantFP: Node is not ConstantFPSDNode"); uint64_t dbits = DoubleToBits(FP->getValueAPF().convertToDouble()); - SDValue T = DAG.getConstant(dbits, MVT::i64); - SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T); + SDValue T = DAG.getConstant(dbits, EVT::i64); + SDValue Tvec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T); return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Tvec)); + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Tvec)); } return SDValue(); @@ -1028,11 +1028,11 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, unsigned ArgRegIdx = 0; unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Add DAG nodes to load the arguments or copy them out of registers. for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { - MVT ObjectVT = Ins[ArgNo].VT; + EVT ObjectVT = Ins[ArgNo].VT; unsigned ObjSize = ObjectVT.getSizeInBits()/8; SDValue ArgVal; @@ -1044,36 +1044,36 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, std::string msg; raw_string_ostream Msg(msg); Msg << "LowerFormalArguments Unhandled argument type: " - << ObjectVT.getMVTString(); + << ObjectVT.getEVTString(); llvm_report_error(Msg.str()); } - case MVT::i8: + case EVT::i8: ArgRegClass = &SPU::R8CRegClass; break; - case MVT::i16: + case EVT::i16: ArgRegClass = &SPU::R16CRegClass; break; - case MVT::i32: + case EVT::i32: ArgRegClass = &SPU::R32CRegClass; break; - case MVT::i64: + case EVT::i64: ArgRegClass = &SPU::R64CRegClass; break; - case MVT::i128: + case EVT::i128: ArgRegClass = &SPU::GPRCRegClass; break; - case MVT::f32: + case EVT::f32: ArgRegClass = &SPU::R32FPRegClass; break; - case MVT::f64: + case EVT::f64: ArgRegClass = &SPU::R64FPRegClass; break; - case MVT::v2f64: - case MVT::v4f32: - case MVT::v2i64: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v2f64: + case EVT::v4f32: + case EVT::v2i64: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: ArgRegClass = &SPU::VECREGRegClass; break; } @@ -1108,7 +1108,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, for (; ArgRegIdx != NumArgRegs; ++ArgRegIdx) { VarArgsFrameIndex = MFI->CreateFixedObject(StackSlotSize, ArgOffset); SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); - SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], MVT::v16i8); + SDValue ArgVal = DAG.getRegister(ArgRegs[ArgRegIdx], EVT::v16i8); SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, NULL, 0); Chain = Store.getOperand(0); MemOps.push_back(Store); @@ -1117,7 +1117,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain, ArgOffset += StackSlotSize; } if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOps[0], MemOps.size()); } @@ -1135,7 +1135,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) { (Addr << 14 >> 14) != Addr) return 0; // Top 14 bits have to be sext of immediate. - return DAG.getConstant((int)C->getZExtValue() >> 2, MVT::i32).getNode(); + return DAG.getConstant((int)C->getZExtValue() >> 2, EVT::i32).getNode(); } SDValue @@ -1154,7 +1154,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const unsigned NumArgRegs = SPURegisterInfo::getNumArgRegs(); // Handy pointer type - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Accumulate how many bytes are to be pushed on the stack, including the // linkage area, and parameter passing area. According to the SPU ABI, @@ -1164,7 +1164,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument // passing. - SDValue StackPtr = DAG.getRegister(SPU::R1, MVT::i32); + SDValue StackPtr = DAG.getRegister(SPU::R1, EVT::i32); // Figure out which arguments are going to go in registers, and which in // memory. @@ -1186,11 +1186,11 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, switch (Arg.getValueType().getSimpleVT()) { default: llvm_unreachable("Unexpected ValueType for argument!"); - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - case MVT::i128: + case EVT::i8: + case EVT::i16: + case EVT::i32: + case EVT::i64: + case EVT::i128: if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { @@ -1198,8 +1198,8 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, ArgOffset += StackSlotSize; } break; - case MVT::f32: - case MVT::f64: + case EVT::f32: + case EVT::f64: if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { @@ -1207,12 +1207,12 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, ArgOffset += StackSlotSize; } break; - case MVT::v2i64: - case MVT::v2f64: - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v2i64: + case EVT::v2f64: + case EVT::v4f32: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: if (ArgRegIdx != NumArgRegs) { RegsToPass.push_back(std::make_pair(ArgRegs[ArgRegIdx++], Arg)); } else { @@ -1230,7 +1230,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (!MemOpChains.empty()) { // Adjust the stack pointer for the stack arguments. - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); } @@ -1251,7 +1251,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // node so that legalize doesn't hack it. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { GlobalValue *GV = G->getGlobal(); - MVT CalleeVT = Callee.getValueType(); + EVT CalleeVT = Callee.getValueType(); SDValue Zero = DAG.getConstant(0, PtrVT); SDValue GA = DAG.getTargetGlobalAddress(GV, CalleeVT); @@ -1275,7 +1275,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, Callee = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, GA, Zero); } } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { - MVT CalleeVT = Callee.getValueType(); + EVT CalleeVT = Callee.getValueType(); SDValue Zero = DAG.getConstant(0, PtrVT); SDValue ExtSym = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType()); @@ -1303,7 +1303,7 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (InFlag.getNode()) Ops.push_back(InFlag); // Returns a chain and a flag for retval copy to use. - Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(MVT::Other, MVT::Flag), + Chain = DAG.getNode(CallOpc, dl, DAG.getVTList(EVT::Other, EVT::Flag), &Ops[0], Ops.size()); InFlag = Chain.getValue(1); @@ -1319,43 +1319,43 @@ SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // If the call has results, copy the values out of the ret val registers. switch (Ins[0].VT.getSimpleVT()) { default: llvm_unreachable("Unexpected ret value!"); - case MVT::Other: break; - case MVT::i32: - if (Ins.size() > 1 && Ins[1].VT == MVT::i32) { + case EVT::Other: break; + case EVT::i32: + if (Ins.size() > 1 && Ins[1].VT == EVT::i32) { Chain = DAG.getCopyFromReg(Chain, dl, SPU::R4, - MVT::i32, InFlag).getValue(1); + EVT::i32, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); - Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32, Chain.getValue(2)).getValue(1); InVals.push_back(Chain.getValue(0)); } else { - Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i32, + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i32, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); } break; - case MVT::i64: - Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i64, + case EVT::i64: + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i64, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); break; - case MVT::i128: - Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, MVT::i128, + case EVT::i128: + Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, EVT::i128, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); break; - case MVT::f32: - case MVT::f64: + case EVT::f32: + case EVT::f64: Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); break; - case MVT::v2f64: - case MVT::v2i64: - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v2f64: + case EVT::v2i64: + case EVT::v4f32: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: Chain = DAG.getCopyFromReg(Chain, dl, SPU::R3, Ins[0].VT, InFlag).getValue(1); InVals.push_back(Chain.getValue(0)); @@ -1395,9 +1395,9 @@ SPUTargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) - return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain, Flag); else - return DAG.getNode(SPUISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(SPUISD::RET_FLAG, dl, EVT::Other, Chain); } @@ -1431,10 +1431,10 @@ getVecImm(SDNode *N) { /// and the value fits into an unsigned 18-bit constant, and if so, return the /// constant SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType) { + EVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getZExtValue(); - if (ValueType == MVT::i64) { + if (ValueType == EVT::i64) { uint64_t UValue = CN->getZExtValue(); uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); @@ -1453,10 +1453,10 @@ SDValue SPU::get_vec_u18imm(SDNode *N, SelectionDAG &DAG, /// and the value fits into a signed 16-bit constant, and if so, return the /// constant SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType) { + EVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSExtValue(); - if (ValueType == MVT::i64) { + if (ValueType == EVT::i64) { uint64_t UValue = CN->getZExtValue(); uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); @@ -1476,10 +1476,10 @@ SDValue SPU::get_vec_i16imm(SDNode *N, SelectionDAG &DAG, /// and the value fits into a signed 10-bit constant, and if so, return the /// constant SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType) { + EVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int64_t Value = CN->getSExtValue(); - if (ValueType == MVT::i64) { + if (ValueType == EVT::i64) { uint64_t UValue = CN->getZExtValue(); uint32_t upper = uint32_t(UValue >> 32); uint32_t lower = uint32_t(UValue); @@ -1502,14 +1502,14 @@ SDValue SPU::get_vec_i10imm(SDNode *N, SelectionDAG &DAG, /// constant vectors. Thus, we test to see if the upper and lower bytes are the /// same value. SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType) { + EVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { int Value = (int) CN->getZExtValue(); - if (ValueType == MVT::i16 + if (ValueType == EVT::i16 && Value <= 0xffff /* truncated from uint64_t */ && ((short) Value >> 8) == ((short) Value & 0xff)) return DAG.getTargetConstant(Value & 0xff, ValueType); - else if (ValueType == MVT::i8 + else if (ValueType == EVT::i8 && (Value & 0xff) == Value) return DAG.getTargetConstant(Value, ValueType); } @@ -1521,12 +1521,12 @@ SDValue SPU::get_vec_i8imm(SDNode *N, SelectionDAG &DAG, /// and the value fits into a signed 16-bit constant, and if so, return the /// constant SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType) { + EVT ValueType) { if (ConstantSDNode *CN = getVecImm(N)) { uint64_t Value = CN->getZExtValue(); - if ((ValueType == MVT::i32 + if ((ValueType == EVT::i32 && ((unsigned) Value & 0xffff0000) == (unsigned) Value) - || (ValueType == MVT::i64 && (Value & 0xffff0000) == Value)) + || (ValueType == EVT::i64 && (Value & 0xffff0000) == Value)) return DAG.getTargetConstant(Value >> 16, ValueType); } @@ -1536,7 +1536,7 @@ SDValue SPU::get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, /// get_v4i32_imm - Catch-all for general 32-bit constant vectors SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) { if (ConstantSDNode *CN = getVecImm(N)) { - return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i32); + return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i32); } return SDValue(); @@ -1545,7 +1545,7 @@ SDValue SPU::get_v4i32_imm(SDNode *N, SelectionDAG &DAG) { /// get_v4i32_imm - Catch-all for general 64-bit constant vectors SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) { if (ConstantSDNode *CN = getVecImm(N)) { - return DAG.getTargetConstant((unsigned) CN->getZExtValue(), MVT::i64); + return DAG.getTargetConstant((unsigned) CN->getZExtValue(), EVT::i64); } return SDValue(); @@ -1554,8 +1554,8 @@ SDValue SPU::get_v2i64_imm(SDNode *N, SelectionDAG &DAG) { //! Lower a BUILD_VECTOR instruction creatively: static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - MVT EltVT = VT.getVectorElementType(); + EVT VT = Op.getValueType(); + EVT EltVT = VT.getVectorElementType(); DebugLoc dl = Op.getDebugLoc(); BuildVectorSDNode *BCN = dyn_cast<BuildVectorSDNode>(Op.getNode()); assert(BCN != 0 && "Expected BuildVectorSDNode in SPU LowerBUILD_VECTOR"); @@ -1580,40 +1580,40 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { std::string msg; raw_string_ostream Msg(msg); Msg << "CellSPU: Unhandled VT in LowerBUILD_VECTOR, VT = " - << VT.getMVTString(); + << VT.getEVTString(); llvm_report_error(Msg.str()); /*NOTREACHED*/ } - case MVT::v4f32: { + case EVT::v4f32: { uint32_t Value32 = uint32_t(SplatBits); assert(SplatBitSize == 32 && "LowerBUILD_VECTOR: Unexpected floating point vector element."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants - SDValue T = DAG.getConstant(Value32, MVT::i32); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, T,T,T,T)); + SDValue T = DAG.getConstant(Value32, EVT::i32); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, T,T,T,T)); break; } - case MVT::v2f64: { + case EVT::v2f64: { uint64_t f64val = uint64_t(SplatBits); assert(SplatBitSize == 64 && "LowerBUILD_VECTOR: 64-bit float vector size > 8 bytes."); // NOTE: pretend the constant is an integer. LLVM won't load FP constants - SDValue T = DAG.getConstant(f64val, MVT::i64); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, T, T)); + SDValue T = DAG.getConstant(f64val, EVT::i64); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, T, T)); break; } - case MVT::v16i8: { + case EVT::v16i8: { // 8-bit constants have to be expanded to 16-bits unsigned short Value16 = SplatBits /* | (SplatBits << 8) */; SmallVector<SDValue, 8> Ops; - Ops.assign(8, DAG.getConstant(Value16, MVT::i16)); + Ops.assign(8, DAG.getConstant(Value16, EVT::i16)); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16, &Ops[0], Ops.size())); + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v8i16, &Ops[0], Ops.size())); } - case MVT::v8i16: { + case EVT::v8i16: { unsigned short Value16 = SplatBits; SDValue T = DAG.getConstant(Value16, EltVT); SmallVector<SDValue, 8> Ops; @@ -1621,15 +1621,15 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { Ops.assign(8, T); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); } - case MVT::v4i32: { + case EVT::v4i32: { SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T, T, T); } - case MVT::v2i32: { + case EVT::v2i32: { SDValue T = DAG.getConstant(unsigned(SplatBits), VT.getVectorElementType()); return DAG.getNode(ISD::BUILD_VECTOR, dl, VT, T, T); } - case MVT::v2i64: { + case EVT::v2i64: { return SPU::LowerV2I64Splat(VT, DAG, SplatBits, dl); } } @@ -1640,16 +1640,16 @@ LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { /*! */ SDValue -SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, +SPU::LowerV2I64Splat(EVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, DebugLoc dl) { uint32_t upper = uint32_t(SplatVal >> 32); uint32_t lower = uint32_t(SplatVal); if (upper == lower) { // Magic constant that can be matched by IL, ILA, et. al. - SDValue Val = DAG.getTargetConstant(upper, MVT::i32); + SDValue Val = DAG.getTargetConstant(upper, EVT::i32); return DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Val, Val, Val, Val)); } else { bool upper_special, lower_special; @@ -1664,8 +1664,8 @@ SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, // Both upper and lower are special, lower to a constant pool load: if (lower_special && upper_special) { - SDValue SplatValCN = DAG.getConstant(SplatVal, MVT::i64); - return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, + SDValue SplatValCN = DAG.getConstant(SplatVal, EVT::i64); + return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64, SplatValCN, SplatValCN); } @@ -1676,17 +1676,17 @@ SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, // Create lower vector if not a special pattern if (!lower_special) { - SDValue LO32C = DAG.getConstant(lower, MVT::i32); + SDValue LO32C = DAG.getConstant(lower, EVT::i32); LO32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, LO32C, LO32C, LO32C, LO32C)); } // Create upper vector if not a special pattern if (!upper_special) { - SDValue HI32C = DAG.getConstant(upper, MVT::i32); + SDValue HI32C = DAG.getConstant(upper, EVT::i32); HI32 = DAG.getNode(ISD::BIT_CONVERT, dl, OpVT, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, HI32C, HI32C, HI32C, HI32C)); } @@ -1720,11 +1720,11 @@ SPU::LowerV2I64Splat(MVT OpVT, SelectionDAG& DAG, uint64_t SplatVal, val |= i * 4 + j + ((i & 1) * 16); } - ShufBytes.push_back(DAG.getConstant(val, MVT::i32)); + ShufBytes.push_back(DAG.getConstant(val, EVT::i32)); } return DAG.getNode(SPUISD::SHUFB, dl, OpVT, HI32, LO32, - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, &ShufBytes[0], ShufBytes.size())); } } @@ -1753,8 +1753,8 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { // If we have a single element being moved from V1 to V2, this can be handled // using the C*[DX] compute mask instructions, but the vector elements have // to be monotonically increasing with one exception element. - MVT VecVT = V1.getValueType(); - MVT EltVT = VecVT.getVectorElementType(); + EVT VecVT = V1.getValueType(); + EVT EltVT = VecVT.getVectorElementType(); unsigned EltsFromV2 = 0; unsigned V2Elt = 0; unsigned V2EltIdx0 = 0; @@ -1765,13 +1765,13 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { bool monotonic = true; bool rotate = true; - if (EltVT == MVT::i8) { + if (EltVT == EVT::i8) { V2EltIdx0 = 16; - } else if (EltVT == MVT::i16) { + } else if (EltVT == EVT::i16) { V2EltIdx0 = 8; - } else if (EltVT == MVT::i32 || EltVT == MVT::f32) { + } else if (EltVT == EVT::i32 || EltVT == EVT::f32) { V2EltIdx0 = 4; - } else if (EltVT == MVT::i64 || EltVT == MVT::f64) { + } else if (EltVT == EVT::i64 || EltVT == EVT::f64) { V2EltIdx0 = 2; } else llvm_unreachable("Unhandled vector type in LowerVECTOR_SHUFFLE"); @@ -1819,14 +1819,14 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Initialize temporary register to 0 SDValue InitTempReg = DAG.getCopyToReg(DAG.getEntryNode(), dl, VReg, DAG.getConstant(0, PtrVT)); // Copy register's contents as index in SHUFFLE_MASK: SDValue ShufMaskOp = - DAG.getNode(SPUISD::SHUFFLE_MASK, dl, MVT::v4i32, - DAG.getTargetConstant(V2Elt, MVT::i32), + DAG.getNode(SPUISD::SHUFFLE_MASK, dl, EVT::v4i32, + DAG.getTargetConstant(V2Elt, EVT::i32), DAG.getCopyFromReg(InitTempReg, dl, VReg, PtrVT)); // Use shuffle mask in SHUFB synthetic instruction: return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V2, V1, @@ -1835,7 +1835,7 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { int rotamt = (MaxElts - V0Elt) * EltVT.getSizeInBits()/8; return DAG.getNode(SPUISD::ROTBYTES_LEFT, dl, V1.getValueType(), - V1, DAG.getConstant(rotamt, MVT::i16)); + V1, DAG.getConstant(rotamt, EVT::i16)); } else { // Convert the SHUFFLE_VECTOR mask's input element units to the // actual bytes. @@ -1846,10 +1846,10 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { unsigned SrcElt = SVN->getMaskElt(i) < 0 ? 0 : SVN->getMaskElt(i); for (unsigned j = 0; j < BytesPerElement; ++j) - ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,MVT::i8)); + ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,EVT::i8)); } - SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8, &ResultMask[0], ResultMask.size()); return DAG.getNode(SPUISD::SHUFB, dl, V1.getValueType(), V1, V2, VPermMask); } @@ -1865,19 +1865,19 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode()); SmallVector<SDValue, 16> ConstVecValues; - MVT VT; + EVT VT; size_t n_copies; // Create a constant vector: switch (Op.getValueType().getSimpleVT()) { default: llvm_unreachable("Unexpected constant value type in " "LowerSCALAR_TO_VECTOR"); - case MVT::v16i8: n_copies = 16; VT = MVT::i8; break; - case MVT::v8i16: n_copies = 8; VT = MVT::i16; break; - case MVT::v4i32: n_copies = 4; VT = MVT::i32; break; - case MVT::v4f32: n_copies = 4; VT = MVT::f32; break; - case MVT::v2i64: n_copies = 2; VT = MVT::i64; break; - case MVT::v2f64: n_copies = 2; VT = MVT::f64; break; + case EVT::v16i8: n_copies = 16; VT = EVT::i8; break; + case EVT::v8i16: n_copies = 8; VT = EVT::i16; break; + case EVT::v4i32: n_copies = 4; VT = EVT::i32; break; + case EVT::v4f32: n_copies = 4; VT = EVT::f32; break; + case EVT::v2i64: n_copies = 2; VT = EVT::i64; break; + case EVT::v2f64: n_copies = 2; VT = EVT::f64; break; } SDValue CValue = DAG.getConstant(CN->getZExtValue(), VT); @@ -1890,12 +1890,12 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { // Otherwise, copy the value from one register to another: switch (Op0.getValueType().getSimpleVT()) { default: llvm_unreachable("Unexpected value type in LowerSCALAR_TO_VECTOR"); - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::i64: - case MVT::f32: - case MVT::f64: + case EVT::i8: + case EVT::i16: + case EVT::i32: + case EVT::i64: + case EVT::f32: + case EVT::f64: return DAG.getNode(SPUISD::PREFSLOT2VEC, dl, Op.getValueType(), Op0, Op0); } } @@ -1904,7 +1904,7 @@ static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { } static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue N = Op.getOperand(0); SDValue Elt = Op.getOperand(1); DebugLoc dl = Op.getDebugLoc(); @@ -1915,16 +1915,16 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { int EltNo = (int) C->getZExtValue(); // sanity checks: - if (VT == MVT::i8 && EltNo >= 16) + if (VT == EVT::i8 && EltNo >= 16) llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i8 extraction slot > 15"); - else if (VT == MVT::i16 && EltNo >= 8) + else if (VT == EVT::i16 && EltNo >= 8) llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i16 extraction slot > 7"); - else if (VT == MVT::i32 && EltNo >= 4) + else if (VT == EVT::i32 && EltNo >= 4) llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i32 extraction slot > 4"); - else if (VT == MVT::i64 && EltNo >= 2) + else if (VT == EVT::i64 && EltNo >= 2) llvm_unreachable("SPU LowerEXTRACT_VECTOR_ELT: i64 extraction slot > 2"); - if (EltNo == 0 && (VT == MVT::i32 || VT == MVT::i64)) { + if (EltNo == 0 && (VT == EVT::i32 || VT == EVT::i64)) { // i32 and i64: Element 0 is the preferred slot return DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, N); } @@ -1936,21 +1936,21 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { switch (VT.getSimpleVT()) { default: assert(false && "Invalid value type!"); - case MVT::i8: { + case EVT::i8: { prefslot_begin = prefslot_end = 3; break; } - case MVT::i16: { + case EVT::i16: { prefslot_begin = 2; prefslot_end = 3; break; } - case MVT::i32: - case MVT::f32: { + case EVT::i32: + case EVT::f32: { prefslot_begin = 0; prefslot_end = 3; break; } - case MVT::i64: - case MVT::f64: { + case EVT::i64: + case EVT::f64: { prefslot_begin = 0; prefslot_end = 7; break; } @@ -1982,11 +1982,11 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { (ShufBytes[bidx+1] << 16) | (ShufBytes[bidx+2] << 8) | ShufBytes[bidx+3]); - ShufMask[i] = DAG.getConstant(bits, MVT::i32); + ShufMask[i] = DAG.getConstant(bits, EVT::i32); } SDValue ShufMaskVec = - DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, &ShufMask[0], sizeof(ShufMask)/sizeof(ShufMask[0])); retval = DAG.getNode(SPUISD::VEC2PREFSLOT, dl, VT, @@ -1995,15 +1995,15 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { } else { // Variable index: Rotate the requested element into slot 0, then replicate // slot 0 across the vector - MVT VecVT = N.getValueType(); + EVT VecVT = N.getValueType(); if (!VecVT.isSimple() || !VecVT.isVector() || !VecVT.is128BitVector()) { llvm_report_error("LowerEXTRACT_VECTOR_ELT: Must have a simple, 128-bit" "vector type!"); } // Make life easier by making sure the index is zero-extended to i32 - if (Elt.getValueType() != MVT::i32) - Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt); + if (Elt.getValueType() != EVT::i32) + Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Elt); // Scale the index to a bit/byte shift quantity APInt scaleFactor = @@ -2013,8 +2013,8 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { if (scaleShift > 0) { // Scale the shift factor: - Elt = DAG.getNode(ISD::SHL, dl, MVT::i32, Elt, - DAG.getConstant(scaleShift, MVT::i32)); + Elt = DAG.getNode(ISD::SHL, dl, EVT::i32, Elt, + DAG.getConstant(scaleShift, EVT::i32)); } vecShift = DAG.getNode(SPUISD::SHLQUAD_L_BYTES, dl, VecVT, N, Elt); @@ -2028,30 +2028,30 @@ static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { llvm_report_error("LowerEXTRACT_VECTOR_ELT(varable): Unhandled vector" "type"); /*NOTREACHED*/ - case MVT::i8: { - SDValue factor = DAG.getConstant(0x00000000, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + case EVT::i8: { + SDValue factor = DAG.getConstant(0x00000000, EVT::i32); + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, factor, factor, factor, factor); break; } - case MVT::i16: { - SDValue factor = DAG.getConstant(0x00010001, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + case EVT::i16: { + SDValue factor = DAG.getConstant(0x00010001, EVT::i32); + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, factor, factor, factor, factor); break; } - case MVT::i32: - case MVT::f32: { - SDValue factor = DAG.getConstant(0x00010203, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + case EVT::i32: + case EVT::f32: { + SDValue factor = DAG.getConstant(0x00010203, EVT::i32); + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, factor, factor, factor, factor); break; } - case MVT::i64: - case MVT::f64: { - SDValue loFactor = DAG.getConstant(0x00010203, MVT::i32); - SDValue hiFactor = DAG.getConstant(0x04050607, MVT::i32); - replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, + case EVT::i64: + case EVT::f64: { + SDValue loFactor = DAG.getConstant(0x00010203, EVT::i32); + SDValue hiFactor = DAG.getConstant(0x04050607, EVT::i32); + replicate = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, loFactor, hiFactor, loFactor, hiFactor); break; } @@ -2070,12 +2070,12 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { SDValue ValOp = Op.getOperand(1); SDValue IdxOp = Op.getOperand(2); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); ConstantSDNode *CN = cast<ConstantSDNode>(IdxOp); assert(CN != 0 && "LowerINSERT_VECTOR_ELT: Index is not constant!"); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Use $sp ($1) because it's always 16-byte aligned and it's available: SDValue Pointer = DAG.getNode(SPUISD::IndirectAddr, dl, PtrVT, DAG.getRegister(SPU::R1, PtrVT), @@ -2086,7 +2086,7 @@ static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { DAG.getNode(SPUISD::SHUFB, dl, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, ValOp), VecOp, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, ShufMask)); + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32, ShufMask)); return result; } @@ -2096,9 +2096,9 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, { SDValue N0 = Op.getOperand(0); // Everything has at least one operand DebugLoc dl = Op.getDebugLoc(); - MVT ShiftVT = TLI.getShiftAmountTy(); + EVT ShiftVT = TLI.getShiftAmountTy(); - assert(Op.getValueType() == MVT::i8); + assert(Op.getValueType() == EVT::i8); switch (Opc) { default: llvm_unreachable("Unhandled i8 math operator"); @@ -2108,10 +2108,10 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, // 8-bit addition: Promote the arguments up to 16-bits and truncate // the result: SDValue N1 = Op.getOperand(1); - N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); - N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, N0, N1)); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0); + N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, N0, N1)); } @@ -2119,17 +2119,17 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, // 8-bit subtraction: Promote the arguments up to 16-bits and truncate // the result: SDValue N1 = Op.getOperand(1); - N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); - N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, N0, N1)); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0); + N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, N0, N1)); } case ISD::ROTR: case ISD::ROTL: { SDValue N1 = Op.getOperand(1); - MVT N1VT = N1.getValueType(); + EVT N1VT = N1.getValueType(); - N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); + N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0); if (!N1VT.bitsEq(ShiftVT)) { unsigned N1Opc = N1.getValueType().bitsLT(ShiftVT) ? ISD::ZERO_EXTEND @@ -2139,20 +2139,20 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, // Replicate lower 8-bits into upper 8: SDValue ExpandArg = - DAG.getNode(ISD::OR, dl, MVT::i16, N0, - DAG.getNode(ISD::SHL, dl, MVT::i16, - N0, DAG.getConstant(8, MVT::i32))); + DAG.getNode(ISD::OR, dl, EVT::i16, N0, + DAG.getNode(ISD::SHL, dl, EVT::i16, + N0, DAG.getConstant(8, EVT::i32))); // Truncate back down to i8 - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, ExpandArg, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, ExpandArg, N1)); } case ISD::SRL: case ISD::SHL: { SDValue N1 = Op.getOperand(1); - MVT N1VT = N1.getValueType(); + EVT N1VT = N1.getValueType(); - N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); + N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, N0); if (!N1VT.bitsEq(ShiftVT)) { unsigned N1Opc = ISD::ZERO_EXTEND; @@ -2162,14 +2162,14 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1); } - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, N0, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, N0, N1)); } case ISD::SRA: { SDValue N1 = Op.getOperand(1); - MVT N1VT = N1.getValueType(); + EVT N1VT = N1.getValueType(); - N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0); if (!N1VT.bitsEq(ShiftVT)) { unsigned N1Opc = ISD::SIGN_EXTEND; @@ -2178,16 +2178,16 @@ static SDValue LowerI8Math(SDValue Op, SelectionDAG &DAG, unsigned Opc, N1 = DAG.getNode(N1Opc, dl, ShiftVT, N1); } - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, N0, N1)); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, N0, N1)); } case ISD::MUL: { SDValue N1 = Op.getOperand(1); - N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N0); - N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, N1); - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, - DAG.getNode(Opc, dl, MVT::i16, N0, N1)); + N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N0); + N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i16, N1); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, + DAG.getNode(Opc, dl, EVT::i16, N0, N1)); break; } } @@ -2200,7 +2200,7 @@ static SDValue LowerByteImmed(SDValue Op, SelectionDAG &DAG) { SDValue ConstVec; SDValue Arg; - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); ConstVec = Op.getOperand(0); @@ -2230,7 +2230,7 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) { HasAnyUndefs, minSplatBits) && minSplatBits <= SplatBitSize) { uint64_t SplatBits = APSplatBits.getZExtValue(); - SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, MVT::i8); + SDValue tc = DAG.getTargetConstant(SplatBits & 0xff, EVT::i8); SmallVector<SDValue, 16> tcVec; tcVec.assign(16, tc); @@ -2251,33 +2251,33 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) { ones per byte, which then have to be accumulated. */ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - MVT vecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + EVT VT = Op.getValueType(); + EVT vecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())); DebugLoc dl = Op.getDebugLoc(); switch (VT.getSimpleVT()) { default: assert(false && "Invalid value type!"); - case MVT::i8: { + case EVT::i8: { SDValue N = Op.getOperand(0); - SDValue Elt0 = DAG.getConstant(0, MVT::i32); + SDValue Elt0 = DAG.getConstant(0, EVT::i32); SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i8, CNTB, Elt0); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i8, CNTB, Elt0); } - case MVT::i16: { + case EVT::i16: { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); unsigned CNTB_reg = RegInfo.createVirtualRegister(&SPU::R16CRegClass); SDValue N = Op.getOperand(0); - SDValue Elt0 = DAG.getConstant(0, MVT::i16); - SDValue Mask0 = DAG.getConstant(0x0f, MVT::i16); - SDValue Shift1 = DAG.getConstant(8, MVT::i32); + SDValue Elt0 = DAG.getConstant(0, EVT::i16); + SDValue Mask0 = DAG.getConstant(0x0f, EVT::i16); + SDValue Shift1 = DAG.getConstant(8, EVT::i32); SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); @@ -2285,22 +2285,22 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, CNTB, Elt0); SDValue CNTB_rescopy = DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); - SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i16); + SDValue Tmp1 = DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i16); - return DAG.getNode(ISD::AND, dl, MVT::i16, - DAG.getNode(ISD::ADD, dl, MVT::i16, - DAG.getNode(ISD::SRL, dl, MVT::i16, + return DAG.getNode(ISD::AND, dl, EVT::i16, + DAG.getNode(ISD::ADD, dl, EVT::i16, + DAG.getNode(ISD::SRL, dl, EVT::i16, Tmp1, Shift1), Tmp1), Mask0); } - case MVT::i32: { + case EVT::i32: { MachineFunction &MF = DAG.getMachineFunction(); MachineRegisterInfo &RegInfo = MF.getRegInfo(); @@ -2308,10 +2308,10 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { unsigned SUM1_reg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); SDValue N = Op.getOperand(0); - SDValue Elt0 = DAG.getConstant(0, MVT::i32); - SDValue Mask0 = DAG.getConstant(0xff, MVT::i32); - SDValue Shift1 = DAG.getConstant(16, MVT::i32); - SDValue Shift2 = DAG.getConstant(8, MVT::i32); + SDValue Elt0 = DAG.getConstant(0, EVT::i32); + SDValue Mask0 = DAG.getConstant(0xff, EVT::i32); + SDValue Shift1 = DAG.getConstant(16, EVT::i32); + SDValue Shift2 = DAG.getConstant(8, EVT::i32); SDValue Promote = DAG.getNode(SPUISD::PREFSLOT2VEC, dl, vecVT, N, N); SDValue CNTB = DAG.getNode(SPUISD::CNTB, dl, vecVT, Promote); @@ -2319,35 +2319,35 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { // CNTB_result becomes the chain to which all of the virtual registers // CNTB_reg, SUM1_reg become associated: SDValue CNTB_result = - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, CNTB, Elt0); + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, CNTB, Elt0); SDValue CNTB_rescopy = DAG.getCopyToReg(CNTB_result, dl, CNTB_reg, CNTB_result); SDValue Comp1 = - DAG.getNode(ISD::SRL, dl, MVT::i32, - DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32), + DAG.getNode(ISD::SRL, dl, EVT::i32, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32), Shift1); SDValue Sum1 = - DAG.getNode(ISD::ADD, dl, MVT::i32, Comp1, - DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, EVT::i32, Comp1, + DAG.getCopyFromReg(CNTB_rescopy, dl, CNTB_reg, EVT::i32)); SDValue Sum1_rescopy = DAG.getCopyToReg(CNTB_result, dl, SUM1_reg, Sum1); SDValue Comp2 = - DAG.getNode(ISD::SRL, dl, MVT::i32, - DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32), + DAG.getNode(ISD::SRL, dl, EVT::i32, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32), Shift2); SDValue Sum2 = - DAG.getNode(ISD::ADD, dl, MVT::i32, Comp2, - DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, MVT::i32)); + DAG.getNode(ISD::ADD, dl, EVT::i32, Comp2, + DAG.getCopyFromReg(Sum1_rescopy, dl, SUM1_reg, EVT::i32)); - return DAG.getNode(ISD::AND, dl, MVT::i32, Sum2, Mask0); + return DAG.getNode(ISD::AND, dl, EVT::i32, Sum2, Mask0); } - case MVT::i64: + case EVT::i64: break; } @@ -2361,12 +2361,12 @@ static SDValue LowerCTPOP(SDValue Op, SelectionDAG &DAG) { */ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SPUTargetLowering &TLI) { - MVT OpVT = Op.getValueType(); + EVT OpVT = Op.getValueType(); SDValue Op0 = Op.getOperand(0); - MVT Op0VT = Op0.getValueType(); + EVT Op0VT = Op0.getValueType(); - if ((OpVT == MVT::i32 && Op0VT == MVT::f64) - || OpVT == MVT::i64) { + if ((OpVT == EVT::i32 && Op0VT == EVT::f64) + || OpVT == EVT::i64) { // Convert f32 / f64 to i32 / i64 via libcall. RTLIB::Libcall LC = (Op.getOpcode() == ISD::FP_TO_SINT) @@ -2387,12 +2387,12 @@ static SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, */ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, SPUTargetLowering &TLI) { - MVT OpVT = Op.getValueType(); + EVT OpVT = Op.getValueType(); SDValue Op0 = Op.getOperand(0); - MVT Op0VT = Op0.getValueType(); + EVT Op0VT = Op0.getValueType(); - if ((OpVT == MVT::f64 && Op0VT == MVT::i32) - || Op0VT == MVT::i64) { + if ((OpVT == EVT::f64 && Op0VT == EVT::i32) + || Op0VT == EVT::i64) { // Convert i32, i64 to f64 via libcall: RTLIB::Libcall LC = (Op.getOpcode() == ISD::SINT_TO_FP) @@ -2408,7 +2408,7 @@ static SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, //! Lower ISD::SETCC /*! - This handles MVT::f64 (double floating point) condition lowering + This handles EVT::f64 (double floating point) condition lowering */ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) { @@ -2418,25 +2418,25 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, SDValue lhs = Op.getOperand(0); SDValue rhs = Op.getOperand(1); - MVT lhsVT = lhs.getValueType(); - assert(lhsVT == MVT::f64 && "LowerSETCC: type other than MVT::64\n"); + EVT lhsVT = lhs.getValueType(); + assert(lhsVT == EVT::f64 && "LowerSETCC: type other than EVT::64\n"); - MVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType()); + EVT ccResultVT = TLI.getSetCCResultType(lhs.getValueType()); APInt ccResultOnes = APInt::getAllOnesValue(ccResultVT.getSizeInBits()); - MVT IntVT(MVT::i64); + EVT IntVT(EVT::i64); // Take advantage of the fact that (truncate (sra arg, 32)) is efficiently // selected to a NOP: SDValue i64lhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, lhs); SDValue lhsHi32 = - DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, DAG.getNode(ISD::SRL, dl, IntVT, - i64lhs, DAG.getConstant(32, MVT::i32))); + i64lhs, DAG.getConstant(32, EVT::i32))); SDValue lhsHi32abs = - DAG.getNode(ISD::AND, dl, MVT::i32, - lhsHi32, DAG.getConstant(0x7fffffff, MVT::i32)); + DAG.getNode(ISD::AND, dl, EVT::i32, + lhsHi32, DAG.getConstant(0x7fffffff, EVT::i32)); SDValue lhsLo32 = - DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, i64lhs); + DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, i64lhs); // SETO and SETUO only use the lhs operand: if (CC->get() == ISD::SETO) { @@ -2453,33 +2453,33 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, return DAG.getNode(ISD::AND, dl, ccResultVT, DAG.getSetCC(dl, ccResultVT, lhsHi32abs, - DAG.getConstant(0x7ff00000, MVT::i32), + DAG.getConstant(0x7ff00000, EVT::i32), ISD::SETGE), DAG.getSetCC(dl, ccResultVT, lhsLo32, - DAG.getConstant(0, MVT::i32), + DAG.getConstant(0, EVT::i32), ISD::SETGT)); } SDValue i64rhs = DAG.getNode(ISD::BIT_CONVERT, dl, IntVT, rhs); SDValue rhsHi32 = - DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, + DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, DAG.getNode(ISD::SRL, dl, IntVT, - i64rhs, DAG.getConstant(32, MVT::i32))); + i64rhs, DAG.getConstant(32, EVT::i32))); // If a value is negative, subtract from the sign magnitude constant: SDValue signMag2TC = DAG.getConstant(0x8000000000000000ULL, IntVT); // Convert the sign-magnitude representation into 2's complement: SDValue lhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, - lhsHi32, DAG.getConstant(31, MVT::i32)); + lhsHi32, DAG.getConstant(31, EVT::i32)); SDValue lhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64lhs); SDValue lhsSelect = DAG.getNode(ISD::SELECT, dl, IntVT, lhsSelectMask, lhsSignMag2TC, i64lhs); SDValue rhsSelectMask = DAG.getNode(ISD::SRA, dl, ccResultVT, - rhsHi32, DAG.getConstant(31, MVT::i32)); + rhsHi32, DAG.getConstant(31, EVT::i32)); SDValue rhsSignMag2TC = DAG.getNode(ISD::SUB, dl, IntVT, signMag2TC, i64rhs); SDValue rhsSelect = DAG.getNode(ISD::SELECT, dl, IntVT, @@ -2517,10 +2517,10 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, if ((CC->get() & 0x8) == 0) { // Ordered comparison: SDValue lhsNaN = DAG.getSetCC(dl, ccResultVT, - lhs, DAG.getConstantFP(0.0, MVT::f64), + lhs, DAG.getConstantFP(0.0, EVT::f64), ISD::SETO); SDValue rhsNaN = DAG.getSetCC(dl, ccResultVT, - rhs, DAG.getConstantFP(0.0, MVT::f64), + rhs, DAG.getConstantFP(0.0, EVT::f64), ISD::SETO); SDValue ordered = DAG.getNode(ISD::AND, dl, ccResultVT, lhsNaN, rhsNaN); @@ -2544,7 +2544,7 @@ static SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG, static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue lhs = Op.getOperand(0); SDValue rhs = Op.getOperand(1); SDValue trueval = Op.getOperand(2); @@ -2573,25 +2573,25 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG, static SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) { // Type to truncate to - MVT VT = Op.getValueType(); - MVT::SimpleValueType simpleVT = VT.getSimpleVT(); - MVT VecVT = MVT::getVectorVT(VT, (128 / VT.getSizeInBits())); + EVT VT = Op.getValueType(); + EVT::SimpleValueType simpleVT = VT.getSimpleVT(); + EVT VecVT = EVT::getVectorVT(VT, (128 / VT.getSizeInBits())); DebugLoc dl = Op.getDebugLoc(); // Type to truncate from SDValue Op0 = Op.getOperand(0); - MVT Op0VT = Op0.getValueType(); + EVT Op0VT = Op0.getValueType(); - if (Op0VT.getSimpleVT() == MVT::i128 && simpleVT == MVT::i64) { + if (Op0VT.getSimpleVT() == EVT::i128 && simpleVT == EVT::i64) { // Create shuffle mask, least significant doubleword of quadword unsigned maskHigh = 0x08090a0b; unsigned maskLow = 0x0c0d0e0f; // Use a shuffle to perform the truncation - SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, - DAG.getConstant(maskHigh, MVT::i32), - DAG.getConstant(maskLow, MVT::i32), - DAG.getConstant(maskHigh, MVT::i32), - DAG.getConstant(maskLow, MVT::i32)); + SDValue shufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, + DAG.getConstant(maskHigh, EVT::i32), + DAG.getConstant(maskLow, EVT::i32), + DAG.getConstant(maskHigh, EVT::i32), + DAG.getConstant(maskLow, EVT::i32)); SDValue truncShuffle = DAG.getNode(SPUISD::SHUFB, dl, VecVT, Op0, Op0, shufMask); @@ -2611,7 +2611,7 @@ SDValue SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { unsigned Opc = (unsigned) Op.getOpcode(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); switch (Opc) { default: { @@ -2647,7 +2647,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) case ISD::SRL: case ISD::SHL: case ISD::SRA: { - if (VT == MVT::i8) + if (VT == EVT::i8) return LowerI8Math(Op, DAG, Opc, *this); break; } @@ -2680,7 +2680,7 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) // Vector and i8 multiply: case ISD::MUL: - if (VT == MVT::i8) + if (VT == EVT::i8) return LowerI8Math(Op, DAG, Opc, *this); case ISD::CTPOP: @@ -2705,7 +2705,7 @@ void SPUTargetLowering::ReplaceNodeResults(SDNode *N, { #if 0 unsigned Opc = (unsigned) N->getOpcode(); - MVT OpVT = N->getValueType(0); + EVT OpVT = N->getValueType(0); switch (Opc) { default: { @@ -2735,8 +2735,8 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const const SPUSubtarget *ST = SPUTM.getSubtargetImpl(); SelectionDAG &DAG = DCI.DAG; SDValue Op0 = N->getOperand(0); // everything has at least one operand - MVT NodeVT = N->getValueType(0); // The node's value type - MVT Op0VT = Op0.getValueType(); // The first operand's result + EVT NodeVT = N->getValueType(0); // The node's value type + EVT Op0VT = Op0.getValueType(); // The first operand's result SDValue Result; // Initially, empty result DebugLoc dl = N->getDebugLoc(); @@ -2938,20 +2938,20 @@ SPUTargetLowering::getConstraintType(const std::string &ConstraintLetter) const std::pair<unsigned, const TargetRegisterClass*> SPUTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const + EVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { case 'b': // R1-R31 case 'r': // R0-R31 - if (VT == MVT::i64) + if (VT == EVT::i64) return std::make_pair(0U, SPU::R64CRegisterClass); return std::make_pair(0U, SPU::R32CRegisterClass); case 'f': - if (VT == MVT::f32) + if (VT == EVT::f32) return std::make_pair(0U, SPU::R32FPRegisterClass); - else if (VT == MVT::f64) + else if (VT == EVT::f64) return std::make_pair(0U, SPU::R64FPRegisterClass); break; case 'v': @@ -3006,10 +3006,10 @@ SPUTargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, return 1; case ISD::SETCC: { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); - if (VT != MVT::i8 && VT != MVT::i16 && VT != MVT::i32) { - VT = MVT::i32; + if (VT != EVT::i8 && VT != EVT::i16 && VT != EVT::i32) { + VT = EVT::i32; } return VT.getSizeInBits(); } diff --git a/lib/Target/CellSPU/SPUISelLowering.h b/lib/Target/CellSPU/SPUISelLowering.h index a042e7d310..07811e4f33 100644 --- a/lib/Target/CellSPU/SPUISelLowering.h +++ b/lib/Target/CellSPU/SPUISelLowering.h @@ -64,22 +64,22 @@ namespace llvm { //! Utility functions specific to CellSPU: namespace SPU { SDValue get_vec_u18imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType); + EVT ValueType); SDValue get_vec_i16imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType); + EVT ValueType); SDValue get_vec_i10imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType); + EVT ValueType); SDValue get_vec_i8imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType); + EVT ValueType); SDValue get_ILHUvec_imm(SDNode *N, SelectionDAG &DAG, - MVT ValueType); + EVT ValueType); SDValue get_v4i32_imm(SDNode *N, SelectionDAG &DAG); SDValue get_v2i64_imm(SDNode *N, SelectionDAG &DAG); SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUTargetMachine &TM); - //! Simplify a MVT::v2i64 constant splat to CellSPU-ready form - SDValue LowerV2I64Splat(MVT OpVT, SelectionDAG &DAG, uint64_t splat, + //! Simplify a EVT::v2i64 constant splat to CellSPU-ready form + SDValue LowerV2I64Splat(EVT OpVT, SelectionDAG &DAG, uint64_t splat, DebugLoc dl); } @@ -109,7 +109,7 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ValueType for ISD::SETCC - virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const; //! Custom lowering hooks virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG); @@ -134,7 +134,7 @@ namespace llvm { std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, bool hasMemory, diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td index 802628f899..4db8e86ec1 100644 --- a/lib/Target/CellSPU/SPUOperands.td +++ b/lib/Target/CellSPU/SPUOperands.td @@ -144,7 +144,7 @@ def imm18 : PatLeaf<(imm), [{ def lo16 : PatLeaf<(imm), [{ // lo16 predicate - returns true if the immediate has all zeros in the // low order bits and is a 32-bit constant: - if (N->getValueType(0) == MVT::i32) { + if (N->getValueType(0) == EVT::i32) { uint32_t val = N->getZExtValue(); return ((val & 0x0000ffff) == val); } @@ -155,10 +155,10 @@ def lo16 : PatLeaf<(imm), [{ def hi16 : PatLeaf<(imm), [{ // hi16 predicate - returns true if the immediate has all zeros in the // low order bits and is a 32-bit constant: - if (N->getValueType(0) == MVT::i32) { + if (N->getValueType(0) == EVT::i32) { uint32_t val = uint32_t(N->getZExtValue()); return ((val & 0xffff0000) == val); - } else if (N->getValueType(0) == MVT::i64) { + } else if (N->getValueType(0) == EVT::i64) { uint64_t val = N->getZExtValue(); return ((val & 0xffff0000ULL) == val); } @@ -208,7 +208,7 @@ def fpimmSExt16 : PatLeaf<(fpimm), [{ // Does the SFP constant only have upp 16 bits set? def hi16_f32 : PatLeaf<(fpimm), [{ - if (N->getValueType(0) == MVT::f32) { + if (N->getValueType(0) == EVT::f32) { uint32_t val = FloatToBits(N->getValueAPF().convertToFloat()); return ((val & 0xffff0000) == val); } @@ -218,7 +218,7 @@ def hi16_f32 : PatLeaf<(fpimm), [{ // Does the SFP constant fit into 18 bits? def fpimm18 : PatLeaf<(fpimm), [{ - if (N->getValueType(0) == MVT::f32) { + if (N->getValueType(0) == EVT::f32) { uint32_t Value = FloatToBits(N->getValueAPF().convertToFloat()); return ((Value & ((1 << 19) - 1)) == Value); } @@ -238,7 +238,7 @@ def fpimm18 : PatLeaf<(fpimm), [{ // immediate constant load for v16i8 vectors. N.B.: The incoming constant has // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a). def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8); + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8); }]>; // v16i8SExt8Imm: Predicate test for 8-bit sign extended immediate constant @@ -246,14 +246,14 @@ def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{ // incoming constant being a 16-bit quantity, where the upper and lower bytes // are EXACTLY the same (e.g., 0x2a2a) def v16i8SExt8Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0; + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0; }], v16i8SExt8Imm_xform>; // v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit // immediate constant load for v16i8 vectors. N.B.: The incoming constant has // to be a 16-bit quantity with the upper and lower bytes equal (e.g., 0x2a2a). def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8); + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8); }]>; // v16i8U8Imm: Predicate test for unsigned 8-bit immediate constant @@ -261,114 +261,114 @@ def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{ // incoming constant being a 16-bit quantity, where the upper and lower bytes // are EXACTLY the same (e.g., 0x2a2a) def v16i8U8Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0; + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i8).getNode() != 0; }], v16i8U8Imm_xform>; // v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended // immediate constant load for v8i16 vectors. def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16); + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16); }]>; // v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant // load, works in conjunction with its transform function. def v8i16SExt8Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0; + return SPU::get_vec_i8imm(N, *CurDAG, EVT::i16).getNode() != 0; }], v8i16SExt8Imm_xform>; // v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended // immediate constant load for v8i16 vectors. def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16); + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16); }]>; // v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant // load, works in conjunction with its transform function. def v8i16SExt10Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0; + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0; }], v8i16SExt10Imm_xform>; // v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned // immediate constant load for v8i16 vectors. def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16); + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16); }]>; // v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant // load, works in conjunction with its transform function. def v8i16Uns10Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0; + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i16).getNode() != 0; }], v8i16Uns10Imm_xform>; // v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended // immediate constant load for v8i16 vectors. def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16); + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16); }]>; // v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant // load, works in conjunction with its transform function. def v8i16SExt16Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0; + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i16).getNode() != 0; }], v8i16Uns16Imm_xform>; // v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended // immediate constant load for v4i32 vectors. def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32); + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32); }]>; // v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant // load, works in conjunction with its transform function. def v4i32SExt10Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0; + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0; }], v4i32SExt10Imm_xform>; // v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned // immediate constant load for v4i32 vectors. def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32); + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32); }]>; // v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant // load, works in conjunction with its transform function. def v4i32Uns10Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0; + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i32).getNode() != 0; }], v4i32Uns10Imm_xform>; // v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended // immediate constant load for v4i32 vectors. def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32); + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32); }]>; // v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant // load, works in conjunction with its transform function. def v4i32SExt16Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0; + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i32).getNode() != 0; }], v4i32SExt16Imm_xform>; // v4i32Uns18Imm_xform function: convert build_vector to 18-bit unsigned // immediate constant load for v4i32 vectors. def v4i32Uns18Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32); + return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32); }]>; // v4i32Uns18Imm: Predicate test for 18-bit unsigned immediate constant load, // works in conjunction with its transform function. def v4i32Uns18Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i32).getNode() != 0; + return SPU::get_vec_u18imm(N, *CurDAG, EVT::i32).getNode() != 0; }], v4i32Uns18Imm_xform>; // ILHUvec_get_imm xform function: convert build_vector to ILHUvec imm constant // load. def ILHUvec_get_imm: SDNodeXForm<build_vector, [{ - return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32); + return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32); }]>; /// immILHUvec: Predicate test for a ILHU constant vector. def immILHUvec: PatLeaf<(build_vector), [{ - return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i32).getNode() != 0; + return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i32).getNode() != 0; }], ILHUvec_get_imm>; // Catch-all for any other i32 vector constants @@ -383,42 +383,42 @@ def v4i32Imm: PatLeaf<(build_vector), [{ // v2i64SExt10Imm_xform function: convert build_vector to 10-bit sign extended // immediate constant load for v2i64 vectors. def v2i64SExt10Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64); + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64); }]>; // v2i64SExt10Imm: Predicate test for 10-bit sign extended immediate constant // load, works in conjunction with its transform function. def v2i64SExt10Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i10imm(N, *CurDAG, MVT::i64).getNode() != 0; + return SPU::get_vec_i10imm(N, *CurDAG, EVT::i64).getNode() != 0; }], v2i64SExt10Imm_xform>; // v2i64SExt16Imm_xform function: convert build_vector to 16-bit sign extended // immediate constant load for v2i64 vectors. def v2i64SExt16Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64); + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64); }]>; // v2i64SExt16Imm: Predicate test for 16-bit sign extended immediate constant // load, works in conjunction with its transform function. def v2i64SExt16Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_i16imm(N, *CurDAG, MVT::i64).getNode() != 0; + return SPU::get_vec_i16imm(N, *CurDAG, EVT::i64).getNode() != 0; }], v2i64SExt16Imm_xform>; // v2i64Uns18Imm_xform function: convert build_vector to 18-bit unsigned // immediate constant load for v2i64 vectors. def v2i64Uns18Imm_xform: SDNodeXForm<build_vector, [{ - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64); + return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64); }]>; // v2i64Uns18Imm: Predicate test for 18-bit unsigned immediate constant load, // works in conjunction with its transform function. def v2i64Uns18Imm: PatLeaf<(build_vector), [{ - return SPU::get_vec_u18imm(N, *CurDAG, MVT::i64).getNode() != 0; + return SPU::get_vec_u18imm(N, *CurDAG, EVT::i64).getNode() != 0; }], v2i64Uns18Imm_xform>; /// immILHUvec: Predicate test for a ILHU constant vector. def immILHUvec_i64: PatLeaf<(build_vector), [{ - return SPU::get_ILHUvec_imm(N, *CurDAG, MVT::i64).getNode() != 0; + return SPU::get_ILHUvec_imm(N, *CurDAG, EVT::i64).getNode() != 0; }], ILHUvec_get_imm>; // Catch-all for any other i32 vector constants diff --git a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp index 6dd3b2a254..bb3439b1ae 100644 --- a/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp +++ b/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp @@ -78,8 +78,8 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Disp) { // Try to match frame address first. if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16); - Disp = CurDAG->getTargetConstant(0, MVT::i16); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16); + Disp = CurDAG->getTargetConstant(0, EVT::i16); return true; } @@ -92,11 +92,11 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr, if (((CVal << 48) >> 48) == CVal) { SDValue N0 = Addr.getOperand(0); if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(N0)) - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i16); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i16); else Base = N0; - Disp = CurDAG->getTargetConstant(CVal, MVT::i16); + Disp = CurDAG->getTargetConstant(CVal, EVT::i16); return true; } } @@ -105,18 +105,18 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue Op, SDValue Addr, SDValue N0 = Addr.getOperand(0); if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { Base = CurDAG->getTargetGlobalAddress(G->getGlobal(), - MVT::i16, G->getOffset()); - Disp = CurDAG->getTargetConstant(0, MVT::i16); + EVT::i16, G->getOffset()); + Disp = CurDAG->getTargetConstant(0, EVT::i16); return true; } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(N0)) { - Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), MVT::i16); - Disp = CurDAG->getTargetConstant(0, MVT::i16); + Base = CurDAG->getTargetExternalSymbol(E->getSymbol(), EVT::i16); + Disp = CurDAG->getTargetConstant(0, EVT::i16); } break; }; Base = Addr; - Disp = CurDAG->getTargetConstant(0, MVT::i16); + Disp = CurDAG->getTargetConstant(0, EVT::i16); return true; } @@ -168,14 +168,14 @@ SDNode *MSP430DAGToDAGISel::Select(SDValue Op) { switch (Node->getOpcode()) { default: break; case ISD::FrameIndex: { - assert(Op.getValueType() == MVT::i16); + assert(Op.getValueType() == EVT::i16); int FI = cast<FrameIndexSDNode>(Node)->getIndex(); - SDValue TFI = CurDAG->getTargetFrameIndex(FI, MVT::i16); + SDValue TFI = CurDAG->getTargetFrameIndex(FI, EVT::i16); if (Node->hasOneUse()) - return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, MVT::i16, - TFI, CurDAG->getTargetConstant(0, MVT::i16)); - return CurDAG->getTargetNode(MSP430::ADD16ri, dl, MVT::i16, - TFI, CurDAG->getTargetConstant(0, MVT::i16)); + return CurDAG->SelectNodeTo(Node, MSP430::ADD16ri, EVT::i16, + TFI, CurDAG->getTargetConstant(0, EVT::i16)); + return CurDAG->getTargetNode(MSP430::ADD16ri, dl, EVT::i16, + TFI, CurDAG->getTargetConstant(0, EVT::i16)); } } diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index d1a504b7dd..a5c4e9ffc5 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -42,8 +42,8 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : Subtarget(*tm.getSubtargetImpl()), TM(tm) { // Set up the register classes. - addRegisterClass(MVT::i8, MSP430::GR8RegisterClass); - addRegisterClass(MVT::i16, MSP430::GR16RegisterClass); + addRegisterClass(EVT::i8, MSP430::GR8RegisterClass); + addRegisterClass(EVT::i16, MSP430::GR16RegisterClass); // Compute derived properties from the register classes computeRegisterProperties(); @@ -55,75 +55,75 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : // Even if we have only 1 bit shift here, we can perform // shifts of the whole bitwidth 1 bit per step. - setShiftAmountType(MVT::i8); + setShiftAmountType(EVT::i8); setStackPointerRegisterToSaveRestore(MSP430::SPW); setBooleanContents(ZeroOrOneBooleanContent); setSchedulingPreference(SchedulingForLatency); - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::i16, Expand); // We don't have any truncstores - setTruncStoreAction(MVT::i16, MVT::i8, Expand); - - setOperationAction(ISD::SRA, MVT::i8, Custom); - setOperationAction(ISD::SHL, MVT::i8, Custom); - setOperationAction(ISD::SRL, MVT::i8, Custom); - setOperationAction(ISD::SRA, MVT::i16, Custom); - setOperationAction(ISD::SHL, MVT::i16, Custom); - setOperationAction(ISD::SRL, MVT::i16, Custom); - setOperationAction(ISD::ROTL, MVT::i8, Expand); - setOperationAction(ISD::ROTR, MVT::i8, Expand); - setOperationAction(ISD::ROTL, MVT::i16, Expand); - setOperationAction(ISD::ROTR, MVT::i16, Expand); - setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); - setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::i8, Custom); - setOperationAction(ISD::BR_CC, MVT::i16, Custom); - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::SETCC, MVT::i8, Expand); - setOperationAction(ISD::SETCC, MVT::i16, Expand); - setOperationAction(ISD::SELECT, MVT::i8, Expand); - setOperationAction(ISD::SELECT, MVT::i16, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i16, Custom); - setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Custom); - - setOperationAction(ISD::CTTZ, MVT::i8, Expand); - setOperationAction(ISD::CTTZ, MVT::i16, Expand); - setOperationAction(ISD::CTLZ, MVT::i8, Expand); - setOperationAction(ISD::CTLZ, MVT::i16, Expand); - setOperationAction(ISD::CTPOP, MVT::i8, Expand); - setOperationAction(ISD::CTPOP, MVT::i16, Expand); - - setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i16, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i16, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i16, Expand); - - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setTruncStoreAction(EVT::i16, EVT::i8, Expand); + + setOperationAction(ISD::SRA, EVT::i8, Custom); + setOperationAction(ISD::SHL, EVT::i8, Custom); + setOperationAction(ISD::SRL, EVT::i8, Custom); + setOperationAction(ISD::SRA, EVT::i16, Custom); + setOperationAction(ISD::SHL, EVT::i16, Custom); + setOperationAction(ISD::SRL, EVT::i16, Custom); + setOperationAction(ISD::ROTL, EVT::i8, Expand); + setOperationAction(ISD::ROTR, EVT::i8, Expand); + setOperationAction(ISD::ROTL, EVT::i16, Expand); + setOperationAction(ISD::ROTR, EVT::i16, Expand); + setOperationAction(ISD::GlobalAddress, EVT::i16, Custom); + setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BRIND, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::i8, Custom); + setOperationAction(ISD::BR_CC, EVT::i16, Custom); + setOperationAction(ISD::BRCOND, EVT::Other, Expand); + setOperationAction(ISD::SETCC, EVT::i8, Expand); + setOperationAction(ISD::SETCC, EVT::i16, Expand); + setOperationAction(ISD::SELECT, EVT::i8, Expand); + setOperationAction(ISD::SELECT, EVT::i16, Expand); + setOperationAction(ISD::SELECT_CC, EVT::i8, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i16, Custom); + setOperationAction(ISD::SIGN_EXTEND, EVT::i16, Custom); + + setOperationAction(ISD::CTTZ, EVT::i8, Expand); + setOperationAction(ISD::CTTZ, EVT::i16, Expand); + setOperationAction(ISD::CTLZ, EVT::i8, Expand); + setOperationAction(ISD::CTLZ, EVT::i16, Expand); + setOperationAction(ISD::CTPOP, EVT::i8, Expand); + setOperationAction(ISD::CTPOP, EVT::i16, Expand); + + setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i16, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i16, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i16, Expand); + + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); // FIXME: Implement efficiently multiplication by a constant - setOperationAction(ISD::MUL, MVT::i16, Expand); - setOperationAction(ISD::MULHS, MVT::i16, Expand); - setOperationAction(ISD::MULHU, MVT::i16, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i16, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i16, Expand); - - setOperationAction(ISD::UDIV, MVT::i16, Expand); - setOperationAction(ISD::UDIVREM, MVT::i16, Expand); - setOperationAction(ISD::UREM, MVT::i16, Expand); - setOperationAction(ISD::SDIV, MVT::i16, Expand); - setOperationAction(ISD::SDIVREM, MVT::i16, Expand); - setOperationAction(ISD::SREM, MVT::i16, Expand); + setOperationAction(ISD::MUL, EVT::i16, Expand); + setOperationAction(ISD::MULHS, EVT::i16, Expand); + setOperationAction(ISD::MULHU, EVT::i16, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i16, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i16, Expand); + + setOperationAction(ISD::UDIV, EVT::i16, Expand); + setOperationAction(ISD::UDIVREM, EVT::i16, Expand); + setOperationAction(ISD::UREM, EVT::i16, Expand); + setOperationAction(ISD::SDIV, EVT::i16, Expand); + setOperationAction(ISD::SDIVREM, EVT::i16, Expand); + setOperationAction(ISD::SREM, EVT::i16, Expand); } SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { @@ -220,7 +220,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain, CCValAssign &VA = ArgLocs[i]; if (VA.isRegLoc()) { // Arguments passed in registers - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); switch (RegVT.getSimpleVT()) { default: { @@ -230,7 +230,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain, #endif llvm_unreachable(0); } - case MVT::i16: + case EVT::i16: unsigned VReg = RegInfo.createVirtualRegister(MSP430::GR16RegisterClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); @@ -266,7 +266,7 @@ MSP430TargetLowering::LowerCCCArguments(SDValue Chain, // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDValue FIN = DAG.getFrameIndex(FI, MVT::i16); + SDValue FIN = DAG.getFrameIndex(FI, EVT::i16); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, PseudoSourceValue::getFixedStack(FI), 0)); } @@ -315,10 +315,10 @@ MSP430TargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) - return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain, Flag); // Return Void - return DAG.getNode(MSP430ISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(MSP430ISD::RET_FLAG, dl, EVT::Other, Chain); } /// LowerCCCCallTo - functions arguments are copied from virtual regs to @@ -395,7 +395,7 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, // Transform all store nodes into one single node because all store nodes are // independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain and @@ -412,12 +412,12 @@ MSP430TargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i16); + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i16); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) - Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i16); + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i16); // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -479,7 +479,7 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) { unsigned Opc = Op.getOpcode(); SDNode* N = Op.getNode(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = N->getDebugLoc(); // We currently only lower shifts of constant argument. @@ -564,7 +564,7 @@ static SDValue EmitCMP(SDValue &LHS, SDValue &RHS, unsigned &TargetCC, break; } - return DAG.getNode(MSP430ISD::CMP, dl, MVT::Flag, LHS, RHS); + return DAG.getNode(MSP430ISD::CMP, dl, EVT::Flag, LHS, RHS); } @@ -581,7 +581,7 @@ SDValue MSP430TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(MSP430ISD::BR_CC, dl, Op.getValueType(), Chain, - Dest, DAG.getConstant(TargetCC, MVT::i8), + Dest, DAG.getConstant(TargetCC, EVT::i8), Flag); } @@ -596,11 +596,11 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { unsigned TargetCC = MSP430::COND_INVALID; SDValue Flag = EmitCMP(LHS, RHS, TargetCC, CC, dl, DAG); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); + SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag); SmallVector<SDValue, 4> Ops; Ops.push_back(TrueV); Ops.push_back(FalseV); - Ops.push_back(DAG.getConstant(TargetCC, MVT::i8)); + Ops.push_back(DAG.getConstant(TargetCC, EVT::i8)); Ops.push_back(Flag); return DAG.getNode(MSP430ISD::SELECT_CC, dl, VTs, &Ops[0], Ops.size()); @@ -609,10 +609,10 @@ SDValue MSP430TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue MSP430TargetLowering::LowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) { SDValue Val = Op.getOperand(0); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); - assert(VT == MVT::i16 && "Only support i16 for now!"); + assert(VT == EVT::i16 && "Only support i16 for now!"); return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, VT, DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 33819b2a5c..b03f7859c7 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -95,7 +95,7 @@ private: // getI32Imm - Return a target constant with the specified // value, of type i32. inline SDValue getI32Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } @@ -142,8 +142,8 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base) { // if Address is FI, get the TargetFrameIndex. if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -151,7 +151,7 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base) if (TM.getRelocationModel() == Reloc::PIC_) { if ((Addr.getOpcode() == ISD::TargetGlobalAddress) || (Addr.getOpcode() == ISD::TargetJumpTable)){ - Base = CurDAG->getRegister(Mips::GP, MVT::i32); + Base = CurDAG->getRegister(Mips::GP, EVT::i32); Offset = Addr; return true; } @@ -169,19 +169,19 @@ SelectAddr(SDValue Op, SDValue Addr, SDValue &Offset, SDValue &Base) // If the first operand is a FI, get the TargetFI Node if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode> (Addr.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); } else { Base = Addr.getOperand(0); } - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32); return true; } } } Base = Addr; - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -243,12 +243,12 @@ Select(SDValue N) SDValue LHS = Node->getOperand(0); SDValue RHS = Node->getOperand(1); - MVT VT = LHS.getValueType(); + EVT VT = LHS.getValueType(); SDNode *Carry = CurDAG->getTargetNode(Mips::SLTu, dl, VT, Ops, 2); SDNode *AddCarry = CurDAG->getTargetNode(Mips::ADDu, dl, VT, SDValue(Carry,0), RHS); - return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, MVT::Flag, + return CurDAG->SelectNodeTo(N.getNode(), MOp, VT, EVT::Flag, LHS, SDValue(AddCarry,0)); } @@ -266,13 +266,13 @@ Select(SDValue N) else Op = (Opcode == ISD::UDIVREM ? Mips::DIVu : Mips::DIV); - SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, - MVT::Flag, InFlag); + SDNode *Lo = CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32, + EVT::Flag, InFlag); InFlag = SDValue(Lo,1); - SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); + SDNode *Hi = CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag); if (!N.getValue(0).use_empty()) ReplaceUses(N.getValue(0), SDValue(Lo,0)); @@ -292,14 +292,14 @@ Select(SDValue N) unsigned MulOp = (Opcode == ISD::MULHU ? Mips::MULTu : Mips::MULT); SDNode *MulNode = CurDAG->getTargetNode(MulOp, dl, - MVT::Flag, MulOp1, MulOp2); + EVT::Flag, MulOp1, MulOp2); SDValue InFlag = SDValue(MulNode, 0); if (MulOp == ISD::MUL) - return CurDAG->getTargetNode(Mips::MFLO, dl, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFLO, dl, EVT::i32, InFlag); else - return CurDAG->getTargetNode(Mips::MFHI, dl, MVT::i32, InFlag); + return CurDAG->getTargetNode(Mips::MFHI, dl, EVT::i32, InFlag); } /// Div/Rem operations @@ -318,10 +318,10 @@ Select(SDValue N) Op = (Opcode == ISD::SREM ? Mips::DIV : Mips::DIVu); MOp = Mips::MFHI; } - SDNode *Node = CurDAG->getTargetNode(Op, dl, MVT::Flag, Op1, Op2); + SDNode *Node = CurDAG->getTargetNode(Op, dl, EVT::Flag, Op1, Op2); SDValue InFlag = SDValue(Node, 0); - return CurDAG->getTargetNode(MOp, dl, MVT::i32, InFlag); + return CurDAG->getTargetNode(MOp, dl, EVT::i32, InFlag); } // Get target GOT address. @@ -337,19 +337,19 @@ Select(SDValue N) //bool isCodeLarge = (TM.getCodeModel() == CodeModel::Large); SDValue Chain = Node->getOperand(0); SDValue Callee = Node->getOperand(1); - SDValue T9Reg = CurDAG->getRegister(Mips::T9, MVT::i32); + SDValue T9Reg = CurDAG->getRegister(Mips::T9, EVT::i32); SDValue InFlag(0, 0); if ( (isa<GlobalAddressSDNode>(Callee)) || (isa<ExternalSymbolSDNode>(Callee)) ) { /// Direct call for global addresses and external symbols - SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32); + SDValue GPReg = CurDAG->getRegister(Mips::GP, EVT::i32); // Use load to get GOT target SDValue Ops[] = { Callee, GPReg, Chain }; - SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, MVT::i32, - MVT::Other, Ops, 3), 0); + SDValue Load = SDValue(CurDAG->getTargetNode(Mips::LW, dl, EVT::i32, + EVT::Other, Ops, 3), 0); Chain = Load.getValue(1); // Call target must be on T9 @@ -359,8 +359,8 @@ Select(SDValue N) Chain = CurDAG->getCopyToReg(Chain, dl, T9Reg, Callee, InFlag); // Emit Jump and Link Register - SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, MVT::Other, - MVT::Flag, T9Reg, Chain); + SDNode *ResNode = CurDAG->getTargetNode(Mips::JALR, dl, EVT::Other, + EVT::Flag, T9Reg, Chain); Chain = SDValue(ResNode, 0); InFlag = SDValue(ResNode, 1); ReplaceUses(SDValue(Node, 0), Chain); diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index 54d260e8df..005827266d 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -65,108 +65,108 @@ MipsTargetLowering(MipsTargetMachine &TM) setUsesGlobalOffsetTable(true); // Set up the register classes - addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); - addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); + addRegisterClass(EVT::i32, Mips::CPURegsRegisterClass); + addRegisterClass(EVT::f32, Mips::FGR32RegisterClass); // When dealing with single precision only, use libcalls if (!Subtarget->isSingleFloat()) if (!Subtarget->isFP64bit()) - addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); + addRegisterClass(EVT::f64, Mips::AFGR64RegisterClass); // Legal fp constants addLegalFPImmediate(APFloat(+0.0f)); // Load extented operations for i1 types must be promoted - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); // MIPS doesn't have extending float->double load/store - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); // Used by legalize types to correctly generate the setcc result. // Without this, every float setcc comes with a AND/OR with the result, // we don't want this, since the fpcmp result goes to a flag register, // which is used implicitly by brcond and select operations. - AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); + AddPromotedToType(ISD::SETCC, EVT::i1, EVT::i32); // Mips Custom Operations - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::SELECT, MVT::f32, Custom); - setOperationAction(ISD::SELECT, MVT::f64, Custom); - setOperationAction(ISD::SELECT, MVT::i32, Custom); - setOperationAction(ISD::SETCC, MVT::f32, Custom); - setOperationAction(ISD::SETCC, MVT::f64, Custom); - setOperationAction(ISD::BRCOND, MVT::Other, Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom); + setOperationAction(ISD::JumpTable, EVT::i32, Custom); + setOperationAction(ISD::ConstantPool, EVT::i32, Custom); + setOperationAction(ISD::SELECT, EVT::f32, Custom); + setOperationAction(ISD::SELECT, EVT::f64, Custom); + setOperationAction(ISD::SELECT, EVT::i32, Custom); + setOperationAction(ISD::SETCC, EVT::f32, Custom); + setOperationAction(ISD::SETCC, EVT::f64, Custom); + setOperationAction(ISD::BRCOND, EVT::Other, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom); // We custom lower AND/OR to handle the case where the DAG contain 'ands/ors' // with operands comming from setcc fp comparions. This is necessary since // the result from these setcc are in a flag registers (FCR31). - setOperationAction(ISD::AND, MVT::i32, Custom); - setOperationAction(ISD::OR, MVT::i32, Custom); + setOperationAction(ISD::AND, EVT::i32, Custom); + setOperationAction(ISD::OR, EVT::i32, Custom); // Operations not directly supported by Mips. - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTTZ, MVT::i32, Expand); - setOperationAction(ISD::ROTL, MVT::i32, Expand); - setOperationAction(ISD::ROTR, MVT::i32, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FSIN, MVT::f32, Expand); - setOperationAction(ISD::FCOS, MVT::f32, Expand); - setOperationAction(ISD::FPOWI, MVT::f32, Expand); - setOperationAction(ISD::FPOW, MVT::f32, Expand); - setOperationAction(ISD::FLOG, MVT::f32, Expand); - setOperationAction(ISD::FLOG2, MVT::f32, Expand); - setOperationAction(ISD::FLOG10, MVT::f32, Expand); - setOperationAction(ISD::FEXP, MVT::f32, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::Other, Expand); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); + setOperationAction(ISD::CTPOP, EVT::i32, Expand); + setOperationAction(ISD::CTTZ, EVT::i32, Expand); + setOperationAction(ISD::ROTL, EVT::i32, Expand); + setOperationAction(ISD::ROTR, EVT::i32, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FSIN, EVT::f32, Expand); + setOperationAction(ISD::FCOS, EVT::f32, Expand); + setOperationAction(ISD::FPOWI, EVT::f32, Expand); + setOperationAction(ISD::FPOW, EVT::f32, Expand); + setOperationAction(ISD::FLOG, EVT::f32, Expand); + setOperationAction(ISD::FLOG2, EVT::f32, Expand); + setOperationAction(ISD::FLOG10, EVT::f32, Expand); + setOperationAction(ISD::FEXP, EVT::f32, Expand); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); // Use the default for now - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand); if (Subtarget->isSingleFloat()) - setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); + setOperationAction(ISD::SELECT_CC, EVT::f64, Expand); if (!Subtarget->hasSEInReg()) { - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand); } if (!Subtarget->hasBitCount()) - setOperationAction(ISD::CTLZ, MVT::i32, Expand); + setOperationAction(ISD::CTLZ, EVT::i32, Expand); if (!Subtarget->hasSwap()) - setOperationAction(ISD::BSWAP, MVT::i32, Expand); + setOperationAction(ISD::BSWAP, EVT::i32, Expand); setStackPointerRegisterToSaveRestore(Mips::SP); computeRegisterProperties(); } -MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(MVT VT) const { - return MVT::i32; +EVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const { + return EVT::i32; } /// getFunctionAlignment - Return the Log2 alignment of this function. @@ -358,22 +358,22 @@ LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) SDValue Src = Op.getOperand(0); // Set the condition register - SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32); + SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, EVT::i32); CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg); - CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32); + CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, EVT::i32); - SDValue Cst = DAG.getConstant(3, MVT::i32); - SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst); - Cst = DAG.getConstant(2, MVT::i32); - SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst); + SDValue Cst = DAG.getConstant(3, EVT::i32); + SDValue Or = DAG.getNode(ISD::OR, dl, EVT::i32, CondReg, Cst); + Cst = DAG.getConstant(2, EVT::i32); + SDValue Xor = DAG.getNode(ISD::XOR, dl, EVT::i32, Or, Cst); SDValue InFlag(0, 0); CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag); // Emit the round instruction and bit convert to integer - SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32, + SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, EVT::f32, Src, CondReg.getValue(1)); - SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Trunc); + SDValue BitCvt = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Trunc); return BitCvt; } @@ -385,11 +385,11 @@ LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) DebugLoc dl = Op.getDebugLoc(); // Get a reference from Mips stack pointer - SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); + SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, EVT::i32); // Subtract the dynamic size from the actual stack size to // obtain the new stack size. - SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); + SDValue Sub = DAG.getNode(ISD::SUB, dl, EVT::i32, StackPointer, Size); // The Sub result contains the new stack start address, so it // must be placed in the stack pointer register. @@ -411,15 +411,15 @@ LowerANDOR(SDValue Op, SelectionDAG &DAG) if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp) return Op; - SDValue True = DAG.getConstant(1, MVT::i32); - SDValue False = DAG.getConstant(0, MVT::i32); + SDValue True = DAG.getConstant(1, EVT::i32); + SDValue False = DAG.getConstant(0, EVT::i32); SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), LHS, True, False, LHS.getOperand(2)); SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(), RHS, True, False, RHS.getOperand(2)); - return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL); + return DAG.getNode(Op.getOpcode(), dl, EVT::i32, LSEL, RSEL); } SDValue MipsTargetLowering:: @@ -438,7 +438,7 @@ LowerBRCOND(SDValue Op, SelectionDAG &DAG) SDValue CCNode = CondRes.getOperand(2); Mips::CondCode CC = (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); - SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); + SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), EVT::i32); return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, Dest, CondRes); @@ -457,7 +457,7 @@ LowerSETCC(SDValue Op, SelectionDAG &DAG) ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS, - DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); + DAG.getConstant(FPCondCCodeToFCC(CC), EVT::i32)); } SDValue MipsTargetLowering:: @@ -491,23 +491,23 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32); if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, GA); - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); - return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, GA); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo); } else { // Abicall relocations, TODO: make this cleaner. - SDValue ResNode = DAG.getLoad(MVT::i32, dl, + SDValue ResNode = DAG.getLoad(EVT::i32, dl, DAG.getEntryNode(), GA, NULL, 0); // On functions and global targets not internal linked only // a load from got/GP is necessary for PIC to work. if (!GV->hasLocalLinkage() || isa<Function>(GV)) return ResNode; - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA); - return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, EVT::i32, ResNode, Lo); } llvm_unreachable("Dont know how to handle GlobalAddress"); @@ -529,19 +529,19 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { - SDVTList VTs = DAG.getVTList(MVT::i32); + SDVTList VTs = DAG.getVTList(EVT::i32); SDValue Ops[] = { JTI }; HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, Ops, 1); } else // Emit Load from Global Pointer - HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); + HiPart = DAG.getLoad(EVT::i32, dl, DAG.getEntryNode(), JTI, NULL, 0); - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI); - ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, JTI); + ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo); return ResNode; } @@ -552,7 +552,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) SDValue ResNode; ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); Constant *C = N->getConstVal(); - SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); + SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment()); // FIXME there isn't actually debug info here DebugLoc dl = Op.getDebugLoc(); @@ -562,13 +562,13 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) // hacking it. This feature should come soon so we can uncomment the // stuff below. //if (IsInSmallSection(C->getType())) { - // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); - // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); - // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); + // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, EVT::i32, CP); + // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(EVT::i32); + // ResNode = DAG.getNode(ISD::ADD, EVT::i32, GOT, GPRelNode); //} else { // %hi/%lo relocation - SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP); - SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP); - ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); + SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, EVT::i32, CP); + SDValue Lo = DAG.getNode(MipsISD::Lo, dl, EVT::i32, CP); + ResNode = DAG.getNode(ISD::ADD, dl, EVT::i32, HiPart, Lo); //} return ResNode; @@ -593,8 +593,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) // go to stack. //===----------------------------------------------------------------------===// -static bool CC_MipsO32(unsigned ValNo, MVT ValVT, - MVT LocVT, CCValAssign::LocInfo LocInfo, +static bool CC_MipsO32(unsigned ValNo, EVT ValVT, + EVT LocVT, CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags, CCState &State) { static const unsigned IntRegsSize=4, FloatRegsSize=2; @@ -614,8 +614,8 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, bool IntRegUsed = (IntRegs[UnallocIntReg] != (unsigned (Mips::A0))); // Promote i8 and i16 - if (LocVT == MVT::i8 || LocVT == MVT::i16) { - LocVT = MVT::i32; + if (LocVT == EVT::i8 || LocVT == EVT::i16) { + LocVT = EVT::i32; if (ArgFlags.isSExt()) LocInfo = CCValAssign::SExt; else if (ArgFlags.isZExt()) @@ -624,20 +624,20 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, LocInfo = CCValAssign::AExt; } - if (ValVT == MVT::i32 || (ValVT == MVT::f32 && IntRegUsed)) { + if (ValVT == EVT::i32 || (ValVT == EVT::f32 && IntRegUsed)) { Reg = State.AllocateReg(IntRegs, IntRegsSize); IntRegUsed = true; - LocVT = MVT::i32; + LocVT = EVT::i32; } if (ValVT.isFloatingPoint() && !IntRegUsed) { - if (ValVT == MVT::f32) + if (ValVT == EVT::f32) Reg = State.AllocateReg(F32Regs, FloatRegsSize); else Reg = State.AllocateReg(F64Regs, FloatRegsSize); } - if (ValVT == MVT::f64 && IntRegUsed) { + if (ValVT == EVT::f64 && IntRegUsed) { if (UnallocIntReg != IntRegsSize) { // If we hit register A3 as the first not allocated, we must // mark it as allocated (shadow) and use the stack instead. @@ -646,7 +646,7 @@ static bool CC_MipsO32(unsigned ValNo, MVT ValVT, for (;UnallocIntReg < IntRegsSize; ++UnallocIntReg) State.AllocateReg(UnallocIntReg); } - LocVT = MVT::i32; + LocVT = EVT::i32; } if (!Reg) { @@ -686,7 +686,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // To meet O32 ABI, Mips must always allocate 16 bytes on // the stack (even if less than 4 are used as arguments) if (Subtarget->isABI_O32()) { - int VTsize = MVT(MVT::i32).getSizeInBits()/8; + int VTsize = EVT(EVT::i32).getSizeInBits()/8; MFI->CreateFixedObject(VTsize, (VTsize*3)); CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); } else @@ -715,13 +715,13 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, default: llvm_unreachable("Unknown loc info!"); case CCValAssign::Full: if (Subtarget->isABI_O32() && VA.isRegLoc()) { - if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) - Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Arg); - if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { - Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, + if (VA.getValVT() == EVT::f32 && VA.getLocVT() == EVT::i32) + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Arg); + if (VA.getValVT() == EVT::f64 && VA.getLocVT() == EVT::i32) { + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg, DAG.getConstant(0, getPointerTy())); - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg, + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Arg, DAG.getConstant(1, getPointerTy())); RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo)); RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi)); @@ -768,7 +768,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Transform all store nodes into one single node because all store // nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -794,7 +794,7 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // = Chain, Callee, Reg#1, Reg#2, ... // // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -838,9 +838,9 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Reload GP value. FI = MipsFI->getGPFI(); SDValue FIN = DAG.getFrameIndex(FI,getPointerTy()); - SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN, NULL, 0); + SDValue GPLoad = DAG.getLoad(EVT::i32, dl, Chain, FIN, NULL, 0); Chain = GPLoad.getValue(1); - Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32), + Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, EVT::i32), GPLoad, SDValue(0,0)); InFlag = Chain.getValue(1); } @@ -919,14 +919,14 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // Arguments stored on registers if (VA.isRegLoc()) { - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); TargetRegisterClass *RC = 0; - if (RegVT == MVT::i32) + if (RegVT == EVT::i32) RC = Mips::CPURegsRegisterClass; - else if (RegVT == MVT::f32) + else if (RegVT == EVT::f32) RC = Mips::FGR32RegisterClass; - else if (RegVT == MVT::f64) { + else if (RegVT == EVT::f64) { if (!Subtarget->isSingleFloat()) RC = Mips::AFGR64RegisterClass; } else @@ -954,15 +954,15 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 if (Subtarget->isABI_O32()) { - if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) - ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); - if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { + if (RegVT == EVT::i32 && VA.getValVT() == EVT::f32) + ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue); + if (RegVT == EVT::i32 && VA.getValVT() == EVT::f64) { unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg()+1, RC); SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); - SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue); - SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, ArgValue2); - ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::f64, Lo, Hi); + SDValue Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue); + SDValue Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, ArgValue2); + ArgValue = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::f64, Lo, Hi); } } @@ -1021,11 +1021,11 @@ MipsTargetLowering::LowerFormalArguments(SDValue Chain, if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { unsigned Reg = MipsFI->getSRetReturnReg(); if (!Reg) { - Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i32)); MipsFI->setSRetReturnReg(Reg); } SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain); } return Chain; @@ -1094,11 +1094,11 @@ MipsTargetLowering::LowerReturn(SDValue Chain, // Return on Mips is always a "jr $ra" if (Flag.getNode()) - return DAG.getNode(MipsISD::Ret, dl, MVT::Other, - Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); + return DAG.getNode(MipsISD::Ret, dl, EVT::Other, + Chain, DAG.getRegister(Mips::RA, EVT::i32), Flag); else // Return Void - return DAG.getNode(MipsISD::Ret, dl, MVT::Other, - Chain, DAG.getRegister(Mips::RA, MVT::i32)); + return DAG.getNode(MipsISD::Ret, dl, EVT::Other, + Chain, DAG.getRegister(Mips::RA, EVT::i32)); } //===----------------------------------------------------------------------===// @@ -1135,16 +1135,16 @@ getConstraintType(const std::string &Constraint) const /// return a list of registers that can be used to satisfy the constraint. /// This should only be used for C_RegisterClass constraints. std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: -getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const +getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': return std::make_pair(0U, Mips::CPURegsRegisterClass); case 'f': - if (VT == MVT::f32) + if (VT == EVT::f32) return std::make_pair(0U, Mips::FGR32RegisterClass); - if (VT == MVT::f64) + if (VT == EVT::f64) if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) return std::make_pair(0U, Mips::AFGR64RegisterClass); } @@ -1157,7 +1157,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const /// pointer. std::vector<unsigned> MipsTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const + EVT VT) const { if (Constraint.size() != 1) return std::vector<unsigned>(); @@ -1174,7 +1174,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, Mips::T8, 0); case 'f': - if (VT == MVT::f32) { + if (VT == EVT::f32) { if (Subtarget->isSingleFloat()) return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5, Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, @@ -1187,7 +1187,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, Mips::F28, Mips::F30, 0); } - if (VT == MVT::f64) + if (VT == EVT::f64) if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4, Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, diff --git a/lib/Target/Mips/MipsISelLowering.h b/lib/Target/Mips/MipsISelLowering.h index 5e5aacdea0..667356ac68 100644 --- a/lib/Target/Mips/MipsISelLowering.h +++ b/lib/Target/Mips/MipsISelLowering.h @@ -80,7 +80,7 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - get the ISD::SETCC result ValueType - MVT::SimpleValueType getSetCCResultType(MVT VT) const; + EVT::SimpleValueType getSetCCResultType(EVT VT) const; /// getFunctionAlignment - Return the Log2 alignment of this function. virtual unsigned getFunctionAlignment(const Function *F) const; @@ -137,11 +137,11 @@ namespace llvm { std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; }; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index b9276fe495..53d6d613a9 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -96,7 +96,7 @@ def HI16 : SDNodeXForm<imm, [{ // Node immediate fits as 16-bit sign extended on target immediate. // e.g. addi, andi def immSExt16 : PatLeaf<(imm), [{ - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); else return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); @@ -107,7 +107,7 @@ def immSExt16 : PatLeaf<(imm), [{ // immediate are caught. // e.g. addiu, sltiu def immZExt16 : PatLeaf<(imm), [{ - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); else return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue(); diff --git a/lib/Target/PIC16/PIC16ISelLowering.cpp b/lib/Target/PIC16/PIC16ISelLowering.cpp index a98604b8ff..72cc1e2a0d 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.cpp +++ b/lib/Target/PIC16/PIC16ISelLowering.cpp @@ -147,9 +147,9 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM) Subtarget = &TM.getSubtarget<PIC16Subtarget>(); - addRegisterClass(MVT::i8, PIC16::GPRRegisterClass); + addRegisterClass(EVT::i8, PIC16::GPRRegisterClass); - setShiftAmountType(MVT::i8); + setShiftAmountType(EVT::i8); // Std lib call names setLibcallName(RTLIB::COS_F32, getStdLibCallName(RTLIB::COS_F32)); @@ -243,65 +243,65 @@ PIC16TargetLowering::PIC16TargetLowering(PIC16TargetMachine &TM) setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); setCmpLibcallCC(RTLIB::O_F32, ISD::SETEQ); - setOperationAction(ISD::GlobalAddress, MVT::i16, Custom); - setOperationAction(ISD::ExternalSymbol, MVT::i16, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i16, Custom); + setOperationAction(ISD::ExternalSymbol, EVT::i16, Custom); - setOperationAction(ISD::LOAD, MVT::i8, Legal); - setOperationAction(ISD::LOAD, MVT::i16, Custom); - setOperationAction(ISD::LOAD, MVT::i32, Custom); + setOperationAction(ISD::LOAD, EVT::i8, Legal); + setOperationAction(ISD::LOAD, EVT::i16, Custom); + setOperationAction(ISD::LOAD, EVT::i32, Custom); - setOperationAction(ISD::STORE, MVT::i8, Legal); - setOperationAction(ISD::STORE, MVT::i16, Custom); - setOperationAction(ISD::STORE, MVT::i32, Custom); - setOperationAction(ISD::STORE, MVT::i64, Custom); + setOperationAction(ISD::STORE, EVT::i8, Legal); + setOperationAction(ISD::STORE, EVT::i16, Custom); + setOperationAction(ISD::STORE, EVT::i32, Custom); + setOperationAction(ISD::STORE, EVT::i64, Custom); - setOperationAction(ISD::ADDE, MVT::i8, Custom); - setOperationAction(ISD::ADDC, MVT::i8, Custom); - setOperationAction(ISD::SUBE, MVT::i8, Custom); - setOperationAction(ISD::SUBC, MVT::i8, Custom); - setOperationAction(ISD::SUB, MVT::i8, Custom); - setOperationAction(ISD::ADD, MVT::i8, Custom); - setOperationAction(ISD::ADD, MVT::i16, Custom); + setOperationAction(ISD::ADDE, EVT::i8, Custom); + setOperationAction(ISD::ADDC, EVT::i8, Custom); + setOperationAction(ISD::SUBE, EVT::i8, Custom); + setOperationAction(ISD::SUBC, EVT::i8, Custom); + setOperationAction(ISD::SUB, EVT::i8, Custom); + setOperationAction(ISD::ADD, EVT::i8, Custom); + setOperationAction(ISD::ADD, EVT::i16, Custom); - setOperationAction(ISD::OR, MVT::i8, Custom); - setOperationAction(ISD::AND, MVT::i8, Custom); - setOperationAction(ISD::XOR, MVT::i8, Custom); + setOperationAction(ISD::OR, EVT::i8, Custom); + setOperationAction(ISD::AND, EVT::i8, Custom); + setOperationAction(ISD::XOR, EVT::i8, Custom); - setOperationAction(ISD::FrameIndex, MVT::i16, Custom); + setOperationAction(ISD::FrameIndex, EVT::i16, Custom); - setOperationAction(ISD::MUL, MVT::i8, Custom); + setOperationAction(ISD::MUL, EVT::i8, Custom); - setOperationAction(ISD::SMUL_LOHI, MVT::i8, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i8, Expand); - setOperationAction(ISD::MULHU, MVT::i8, Expand); - setOperationAction(ISD::MULHS, MVT::i8, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i8, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i8, Expand); + setOperationAction(ISD::MULHU, EVT::i8, Expand); + setOperationAction(ISD::MULHS, EVT::i8, Expand); - setOperationAction(ISD::SRA, MVT::i8, Custom); - setOperationAction(ISD::SHL, MVT::i8, Custom); - setOperationAction(ISD::SRL, MVT::i8, Custom); + setOperationAction(ISD::SRA, EVT::i8, Custom); + setOperationAction(ISD::SHL, EVT::i8, Custom); + setOperationAction(ISD::SRL, EVT::i8, Custom); - setOperationAction(ISD::ROTL, MVT::i8, Expand); - setOperationAction(ISD::ROTR, MVT::i8, Expand); + setOperationAction(ISD::ROTL, EVT::i8, Expand); + setOperationAction(ISD::ROTR, EVT::i8, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); // PIC16 does not support shift parts - setOperationAction(ISD::SRA_PARTS, MVT::i8, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i8, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i8, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i8, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i8, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i8, Expand); // PIC16 does not have a SETCC, expand it to SELECT_CC. - setOperationAction(ISD::SETCC, MVT::i8, Expand); - setOperationAction(ISD::SELECT, MVT::i8, Expand); - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::Other, Expand); + setOperationAction(ISD::SETCC, EVT::i8, Expand); + setOperationAction(ISD::SELECT, EVT::i8, Expand); + setOperationAction(ISD::BRCOND, EVT::Other, Expand); + setOperationAction(ISD::BRIND, EVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i8, Custom); - setOperationAction(ISD::BR_CC, MVT::i8, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i8, Custom); + setOperationAction(ISD::BR_CC, EVT::i8, Custom); - //setOperationAction(ISD::TRUNCATE, MVT::i16, Custom); - setTruncStoreAction(MVT::i16, MVT::i8, Custom); + //setOperationAction(ISD::TRUNCATE, EVT::i16, Custom); + setTruncStoreAction(EVT::i16, EVT::i8, Custom); // Now deduce the information based on the above mentioned // actions @@ -313,7 +313,7 @@ static SDValue getOutFlag(SDValue &Op) { // Flag is the last value of the node. SDValue Flag = Op.getValue(Op.getNode()->getNumValues() - 1); - assert (Flag.getValueType() == MVT::Flag + assert (Flag.getValueType() == EVT::Flag && "Node does not have an out Flag"); return Flag; @@ -340,12 +340,12 @@ static SDValue getChain(SDValue &Op) { // If the last value returned in Flag then the chain is // second last value returned. - if (Chain.getValueType() == MVT::Flag) + if (Chain.getValueType() == EVT::Flag) Chain = Op.getValue(Op.getNode()->getNumValues() - 2); // All nodes may not produce a chain. Therefore following assert // verifies that the node is returning a chain only. - assert (Chain.getValueType() == MVT::Other + assert (Chain.getValueType() == EVT::Other && "Node does not have a chain"); return Chain; @@ -365,9 +365,9 @@ static void PopulateResults(SDValue N, SmallVectorImpl<SDValue>&Results) { Results.push_back(N); } -MVT::SimpleValueType -PIC16TargetLowering::getSetCCResultType(MVT ValType) const { - return MVT::i8; +EVT::SimpleValueType +PIC16TargetLowering::getSetCCResultType(EVT ValType) const { + return EVT::i8; } /// The type legalizer framework of generating legalizer can generate libcalls @@ -389,7 +389,7 @@ PIC16TargetLowering::getPIC16LibcallName(PIC16ISD::PIC16Libcall Call) { SDValue PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, - MVT RetVT, const SDValue *Ops, + EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SelectionDAG &DAG, DebugLoc dl) { @@ -399,14 +399,14 @@ PIC16TargetLowering::MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, TargetLowering::ArgListEntry Entry; for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; - Entry.Ty = Entry.Node.getValueType().getTypeForMVT(); + Entry.Ty = Entry.Node.getValueType().getTypeForEVT(); Entry.isSExt = isSigned; Entry.isZExt = !isSigned; Args.push_back(Entry); } - SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), MVT::i16); + SDValue Callee = DAG.getExternalSymbol(getPIC16LibcallName(Call), EVT::i16); - const Type *RetTy = RetVT.getTypeForMVT(); + const Type *RetTy = RetVT.getTypeForEVT(); std::pair<SDValue,SDValue> CallInfo = LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, false, 0, CallingConv::C, false, @@ -477,11 +477,11 @@ void PIC16TargetLowering::ReplaceNodeResults(SDNode *N, SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) { - // Currently handling FrameIndex of size MVT::i16 only + // Currently handling FrameIndex of size EVT::i16 only // One example of this scenario is when return value is written on // FrameIndex#0 - if (N->getValueType(0) != MVT::i16) + if (N->getValueType(0) != EVT::i16) return SDValue(); // Expand the FrameIndex into ExternalSymbol and a Constant node @@ -503,9 +503,9 @@ SDValue PIC16TargetLowering::ExpandFrameIndex(SDNode *N, SelectionDAG &DAG) { int FrameOffset; SDValue FI = SDValue(N,0); LegalizeFrameIndex(FI, DAG, ES, FrameOffset); - SDValue Offset = DAG.getConstant(FrameOffset, MVT::i8); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, ES, Offset); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, ES, Offset); + SDValue Offset = DAG.getConstant(FrameOffset, EVT::i8); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, ES, Offset); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, ES, Offset); return DAG.getNode(ISD::BUILD_PAIR, dl, N->getValueType(0), Lo, Hi); } @@ -515,19 +515,19 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { SDValue Chain = St->getChain(); SDValue Src = St->getValue(); SDValue Ptr = St->getBasePtr(); - MVT ValueType = Src.getValueType(); + EVT ValueType = Src.getValueType(); unsigned StoreOffset = 0; DebugLoc dl = N->getDebugLoc(); SDValue PtrLo, PtrHi; LegalizeAddress(Ptr, DAG, PtrLo, PtrHi, StoreOffset, dl); - if (ValueType == MVT::i8) { - return DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, Src, + if (ValueType == EVT::i8) { + return DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, Src, PtrLo, PtrHi, - DAG.getConstant (0 + StoreOffset, MVT::i8)); + DAG.getConstant (0 + StoreOffset, EVT::i8)); } - else if (ValueType == MVT::i16) { + else if (ValueType == EVT::i16) { // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR. SDValue SrcLo, SrcHi; GetExpandedParts(Src, DAG, SrcLo, SrcHi); @@ -536,19 +536,19 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { ChainLo = Chain.getOperand(0); ChainHi = Chain.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainLo, SrcLo, PtrLo, PtrHi, - DAG.getConstant (0 + StoreOffset, MVT::i8)); + DAG.getConstant (0 + StoreOffset, EVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi, SrcHi, PtrLo, PtrHi, - DAG.getConstant (1 + StoreOffset, MVT::i8)); + DAG.getConstant (1 + StoreOffset, EVT::i8)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, getChain(Store1), + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(Store1), getChain(Store2)); } - else if (ValueType == MVT::i32) { + else if (ValueType == EVT::i32) { // Get the Lo and Hi parts from MERGE_VALUE or BUILD_PAIR. SDValue SrcLo, SrcHi; GetExpandedParts(Src, DAG, SrcLo, SrcHi); @@ -573,30 +573,30 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { ChainHi1 = ChainHi.getOperand(0); ChainHi2 = ChainHi.getOperand(1); } - SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, + SDValue Store1 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainLo1, SrcLo1, PtrLo, PtrHi, - DAG.getConstant (0 + StoreOffset, MVT::i8)); + DAG.getConstant (0 + StoreOffset, EVT::i8)); - SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainLo2, + SDValue Store2 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainLo2, SrcLo2, PtrLo, PtrHi, - DAG.getConstant (1 + StoreOffset, MVT::i8)); + DAG.getConstant (1 + StoreOffset, EVT::i8)); - SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi1, + SDValue Store3 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi1, SrcHi1, PtrLo, PtrHi, - DAG.getConstant (2 + StoreOffset, MVT::i8)); + DAG.getConstant (2 + StoreOffset, EVT::i8)); - SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, MVT::Other, ChainHi2, + SDValue Store4 = DAG.getNode(PIC16ISD::PIC16Store, dl, EVT::Other, ChainHi2, SrcHi2, PtrLo, PtrHi, - DAG.getConstant (3 + StoreOffset, MVT::i8)); + DAG.getConstant (3 + StoreOffset, EVT::i8)); - SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + SDValue RetLo = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(Store1), getChain(Store2)); - SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + SDValue RetHi = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(Store3), getChain(Store4)); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, RetLo, RetHi); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, RetLo, RetHi); - } else if (ValueType == MVT::i64) { + } else if (ValueType == EVT::i64) { SDValue SrcLo, SrcHi; GetExpandedParts(Src, DAG, SrcLo, SrcHi); SDValue ChainLo = Chain, ChainHi = Chain; @@ -612,7 +612,7 @@ SDValue PIC16TargetLowering::ExpandStore(SDNode *N, SelectionDAG &DAG) { SDValue Store2 = DAG.getStore(ChainHi, dl, SrcHi, Ptr, NULL, 1 + StoreOffset); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2); } else { assert (0 && "value type not supported"); @@ -626,12 +626,12 @@ SDValue PIC16TargetLowering::ExpandExternalSymbol(SDNode *N, SelectionDAG &DAG) // FIXME there isn't really debug info here DebugLoc dl = ES->getDebugLoc(); - SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); - SDValue Offset = DAG.getConstant(0, MVT::i8); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TES, Offset); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TES, Offset); + SDValue TES = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8); + SDValue Offset = DAG.getConstant(0, EVT::i8); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TES, Offset); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TES, Offset); - return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi); } // ExpandGlobalAddress - @@ -640,14 +640,14 @@ SDValue PIC16TargetLowering::ExpandGlobalAddress(SDNode *N, SelectionDAG &DAG) { // FIXME there isn't really debug info here DebugLoc dl = G->getDebugLoc(); - SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i8, + SDValue TGA = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i8, G->getOffset()); - SDValue Offset = DAG.getConstant(0, MVT::i8); - SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, MVT::i8, TGA, Offset); - SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, MVT::i8, TGA, Offset); + SDValue Offset = DAG.getConstant(0, EVT::i8); + SDValue Lo = DAG.getNode(PIC16ISD::Lo, dl, EVT::i8, TGA, Offset); + SDValue Hi = DAG.getNode(PIC16ISD::Hi, dl, EVT::i8, TGA, Offset); - return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, Lo, Hi); } bool PIC16TargetLowering::isDirectAddress(const SDValue &Op) { @@ -690,15 +690,15 @@ void PIC16TargetLowering::GetExpandedParts(SDValue Op, SelectionDAG &DAG, SDValue &Lo, SDValue &Hi) { SDNode *N = Op.getNode(); DebugLoc dl = N->getDebugLoc(); - MVT NewVT = getTypeToTransformTo(N->getValueType(0)); + EVT NewVT = getTypeToTransformTo(N->getValueType(0)); // Extract the lo component. Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op, - DAG.getConstant(0, MVT::i8)); + DAG.getConstant(0, EVT::i8)); // extract the hi component Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NewVT, Op, - DAG.getConstant(1, MVT::i8)); + DAG.getConstant(1, EVT::i8)); } // Legalize FrameIndex into ExternalSymbol and offset. @@ -722,7 +722,7 @@ PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, const char *tmpName; if (FIndex < ReservedFrameCount) { tmpName = createESName(PAN::getFrameLabel(Name)); - ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8); + ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8); Offset = 0; for (unsigned i=0; i<FIndex ; ++i) { Offset += MFI->getObjectSize(i); @@ -730,7 +730,7 @@ PIC16TargetLowering::LegalizeFrameIndex(SDValue Op, SelectionDAG &DAG, } else { // FrameIndex has been made for some temporary storage tmpName = createESName(PAN::getTempdataLabel(Name)); - ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8); + ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8); Offset = GetTmpOffsetForFI(FIndex, MFI->getObjectSize(FIndex)); } @@ -776,11 +776,11 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, // then treat it as direct address. // One example for such case is storing and loading // from function frame during a call - if (Ptr.getValueType() == MVT::i8) { + if (Ptr.getValueType() == EVT::i8) { switch (Ptr.getOpcode()) { case ISD::TargetExternalSymbol: Lo = Ptr; - Hi = DAG.getConstant(1, MVT::i8); + Hi = DAG.getConstant(1, EVT::i8); return; } } @@ -791,14 +791,14 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, int FrameOffset; if (TFI.getOpcode() == ISD::TargetFrameIndex) { LegalizeFrameIndex(TFI, DAG, Lo, FrameOffset); - Hi = DAG.getConstant(1, MVT::i8); + Hi = DAG.getConstant(1, EVT::i8); Offset += FrameOffset; return; } else if (TFI.getOpcode() == ISD::TargetExternalSymbol) { // FrameIndex has already been expanded. // Now just make use of its expansion Lo = TFI; - Hi = DAG.getConstant(1, MVT::i8); + Hi = DAG.getConstant(1, EVT::i8); SDValue FOffset = Ptr.getOperand(0).getOperand(1); assert (FOffset.getOpcode() == ISD::Constant && "Invalid operand of PIC16ISD::Lo"); @@ -816,7 +816,7 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, // signifies that banksel needs to generated for it. Value 0 for // the constant signifies that banksel does not need to be generated // for it. Mark it as 1 now and optimize later. - Hi = DAG.getConstant(1, MVT::i8); + Hi = DAG.getConstant(1, EVT::i8); return; } @@ -824,8 +824,8 @@ void PIC16TargetLowering::LegalizeAddress(SDValue Ptr, SelectionDAG &DAG, GetExpandedParts(Ptr, DAG, Lo, Hi); // Put the hi and lo parts into FSR. - Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Lo); - Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Hi); + Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Lo); + Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Hi); return; } @@ -838,7 +838,7 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { SDValue Load, Offset; SDVTList Tys; - MVT VT, NewVT; + EVT VT, NewVT; SDValue PtrLo, PtrHi; unsigned LoadOffset; @@ -851,12 +851,12 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { unsigned NumLoads = VT.getSizeInBits() / 8; std::vector<SDValue> PICLoads; unsigned iter; - MVT MemVT = LD->getMemoryVT(); + EVT MemVT = LD->getMemoryVT(); if(ISD::isNON_EXTLoad(N)) { for (iter=0; iter<NumLoads ; ++iter) { // Add the pointer offset if any - Offset = DAG.getConstant(iter + LoadOffset, MVT::i8); - Tys = DAG.getVTList(MVT::i8, MVT::Other); + Offset = DAG.getConstant(iter + LoadOffset, EVT::i8); + Tys = DAG.getVTList(EVT::i8, EVT::Other); Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi, Offset); PICLoads.push_back(Load); @@ -869,20 +869,20 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { // For extended loads this is the memory value type // i.e. without any extension - MVT MemVT = LD->getMemoryVT(); + EVT MemVT = LD->getMemoryVT(); unsigned MemBytes = MemVT.getSizeInBits() / 8; - // if MVT::i1 is extended to MVT::i8 then MemBytes will be zero + // if EVT::i1 is extended to EVT::i8 then MemBytes will be zero // So set it to one if (MemBytes == 0) MemBytes = 1; unsigned ExtdBytes = VT.getSizeInBits() / 8; - Offset = DAG.getConstant(LoadOffset, MVT::i8); + Offset = DAG.getConstant(LoadOffset, EVT::i8); - Tys = DAG.getVTList(MVT::i8, MVT::Other); + Tys = DAG.getVTList(EVT::i8, EVT::Other); // For MemBytes generate PIC16Load with proper offset for (iter=0; iter < MemBytes; ++iter) { // Add the pointer offset if any - Offset = DAG.getConstant(iter + LoadOffset, MVT::i8); + Offset = DAG.getConstant(iter + LoadOffset, EVT::i8); Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Chain, PtrLo, PtrHi, Offset); PICLoads.push_back(Load); @@ -892,15 +892,15 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { if (ISD::isSEXTLoad(N)) { // For all ExtdBytes use the Right Shifted(Arithmetic) Value of the // highest MemByte - SDValue SRA = DAG.getNode(ISD::SRA, dl, MVT::i8, Load, - DAG.getConstant(7, MVT::i8)); + SDValue SRA = DAG.getNode(ISD::SRA, dl, EVT::i8, Load, + DAG.getConstant(7, EVT::i8)); for (iter=MemBytes; iter<ExtdBytes; ++iter) { PICLoads.push_back(SRA); } } else if (ISD::isZEXTLoad(N) || ISD::isEXTLoad(N)) { //} else if (ISD::isZEXTLoad(N)) { // ZeroExtendedLoad -- For all ExtdBytes use constant 0 - SDValue ConstZero = DAG.getConstant(0, MVT::i8); + SDValue ConstZero = DAG.getConstant(0, EVT::i8); for (iter=MemBytes; iter<ExtdBytes; ++iter) { PICLoads.push_back(ConstZero); } @@ -908,46 +908,46 @@ SDValue PIC16TargetLowering::ExpandLoad(SDNode *N, SelectionDAG &DAG) { } SDValue BP; - if (VT == MVT::i8) { + if (VT == EVT::i8) { // Operand of Load is illegal -- Load itself is legal return PICLoads[0]; } - else if (VT == MVT::i16) { + else if (VT == EVT::i16) { BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, PICLoads[0], PICLoads[1]); - if (MemVT == MVT::i8) + if (MemVT == EVT::i8) Chain = getChain(PICLoads[0]); else - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(PICLoads[0]), getChain(PICLoads[1])); - } else if (VT == MVT::i32) { + } else if (VT == EVT::i32) { SDValue BPs[2]; - BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, + BPs[0] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, PICLoads[0], PICLoads[1]); - BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i16, + BPs[1] = DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i16, PICLoads[2], PICLoads[3]); BP = DAG.getNode(ISD::BUILD_PAIR, dl, VT, BPs[0], BPs[1]); - if (MemVT == MVT::i8) + if (MemVT == EVT::i8) Chain = getChain(PICLoads[0]); - else if (MemVT == MVT::i16) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + else if (MemVT == EVT::i16) + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(PICLoads[0]), getChain(PICLoads[1])); else { SDValue Chains[2]; - Chains[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chains[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(PICLoads[0]), getChain(PICLoads[1])); - Chains[1] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chains[1] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, getChain(PICLoads[2]), getChain(PICLoads[3])); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Chains[0], Chains[1]); } } - Tys = DAG.getVTList(VT, MVT::Other); + Tys = DAG.getVTList(VT, EVT::Other); return DAG.getNode(ISD::MERGE_VALUES, dl, Tys, BP, Chain); } SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. - assert (Op.getValueType() == MVT::i8 && "illegal shift to lower"); + assert (Op.getValueType() == EVT::i8 && "illegal shift to lower"); SDNode *N = Op.getNode(); SDValue Value = N->getOperand(0); @@ -977,7 +977,7 @@ SDValue PIC16TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. - assert (Op.getValueType() == MVT::i8 && "illegal multiply to lower"); + assert (Op.getValueType() == EVT::i8 && "illegal multiply to lower"); SDNode *N = Op.getNode(); SmallVector<SDValue, 2> Ops(2); @@ -1050,7 +1050,7 @@ SDValue PIC16TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op, SelectionDAG &DAG, DebugLoc dl) { - assert (Op.getValueType() == MVT::i8 + assert (Op.getValueType() == EVT::i8 && "illegal value type to store on stack."); MachineFunction &MF = DAG.getMachineFunction(); @@ -1062,22 +1062,22 @@ SDValue PIC16TargetLowering::ConvertToMemOperand(SDValue Op, // Get a stack slot index and convert to es. int FI = MF.getFrameInfo()->CreateStackObject(1, 1); const char *tmpName = createESName(PAN::getTempdataLabel(FuncName)); - SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8); + SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8); // Store the value to ES. - SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, + SDValue Store = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, DAG.getEntryNode(), Op, ES, - DAG.getConstant (1, MVT::i8), // Banksel. + DAG.getConstant (1, EVT::i8), // Banksel. DAG.getConstant (GetTmpOffsetForFI(FI, 1), - MVT::i8)); + EVT::i8)); // Load the value from ES. - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other); SDValue Load = DAG.getNode(PIC16ISD::PIC16Load, dl, Tys, Store, - ES, DAG.getConstant (1, MVT::i8), + ES, DAG.getConstant (1, EVT::i8), DAG.getConstant (GetTmpOffsetForFI(FI, 1), - MVT::i8)); + EVT::i8)); return Load.getValue(0); } @@ -1094,7 +1094,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag, return Chain; std::vector<SDValue> Ops; - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue Arg, StoreRet; // For PIC16 ABI the arguments come after the return value. @@ -1108,7 +1108,7 @@ LowerIndirectCallArguments(SDValue Chain, SDValue InFlag, Ops.push_back(Arg); Ops.push_back(DataAddr_Lo); Ops.push_back(DataAddr_Hi); - Ops.push_back(DAG.getConstant(ArgOffset, MVT::i8)); + Ops.push_back(DAG.getConstant(ArgOffset, EVT::i8)); Ops.push_back(InFlag); StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size()); @@ -1127,7 +1127,7 @@ LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag, unsigned NumOps = Outs.size(); std::string Name; SDValue Arg, StoreAt; - MVT ArgVT; + EVT ArgVT; unsigned Size=0; // If call has no arguments then do nothing and return. @@ -1145,7 +1145,7 @@ LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag, SDValue StoreRet; std::vector<SDValue> Ops; - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); for (unsigned i=0, Offset = 0; i<NumOps; i++) { // Get the argument Arg = Outs[i].Val; @@ -1158,7 +1158,7 @@ LowerDirectCallArguments(SDValue ArgLabel, SDValue Chain, SDValue InFlag, Ops.push_back(Arg); Ops.push_back(PtrLo); Ops.push_back(PtrHi); - Ops.push_back(DAG.getConstant(StoreOffset, MVT::i8)); + Ops.push_back(DAG.getConstant(StoreOffset, EVT::i8)); Ops.push_back(InFlag); StoreRet = DAG.getNode (PIC16ISD::PIC16StWF, dl, Tys, &Ops[0], Ops.size()); @@ -1191,10 +1191,10 @@ LowerIndirectCallReturn(SDValue Chain, SDValue InFlag, // Call has something to return SDValue LoadRet; - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag); for(unsigned i=0;i<RetVals;i++) { LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, DataAddr_Lo, - DataAddr_Hi, DAG.getConstant(i, MVT::i8), + DataAddr_Hi, DAG.getConstant(i, EVT::i8), InFlag); InFlag = getOutFlag(LoadRet); Chain = getChain(LoadRet); @@ -1224,13 +1224,13 @@ LowerDirectCallReturn(SDValue RetLabel, SDValue Chain, SDValue InFlag, unsigned LdOffset; LegalizeAddress(RetLabel, DAG, LdLo, LdHi, LdOffset, dl); - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag); SDValue LoadRet; for(unsigned i=0, Offset=0;i<RetVals;i++) { LoadRet = DAG.getNode(PIC16ISD::PIC16LdWF, dl, Tys, Chain, LdLo, LdHi, - DAG.getConstant(LdOffset + Offset, MVT::i8), + DAG.getConstant(LdOffset + Offset, EVT::i8), InFlag); InFlag = getOutFlag(LoadRet); @@ -1259,18 +1259,18 @@ PIC16TargetLowering::LowerReturn(SDValue Chain, std::string FuncName = F->getName(); const char *tmpName = createESName(PAN::getFrameLabel(FuncName)); - SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other); - SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8); - SDValue BS = DAG.getConstant(1, MVT::i8); + SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other); + SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8); + SDValue BS = DAG.getConstant(1, EVT::i8); SDValue RetVal; for(unsigned i=0;i<NumRet; ++i) { RetVal = Outs[i].Val; - Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, MVT::Other, Chain, RetVal, + Chain = DAG.getNode (PIC16ISD::PIC16Store, dl, EVT::Other, Chain, RetVal, ES, BS, - DAG.getConstant (i, MVT::i8)); + DAG.getConstant (i, EVT::i8)); } - return DAG.getNode(PIC16ISD::RET, dl, MVT::Other, Chain); + return DAG.getNode(PIC16ISD::RET, dl, EVT::Other, Chain); } void PIC16TargetLowering:: @@ -1279,7 +1279,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, SelectionDAG &DAG) { assert (Callee.getOpcode() == PIC16ISD::PIC16Connect && "Don't know what to do of such callee!!"); - SDValue ZeroOperand = DAG.getConstant(0, MVT::i8); + SDValue ZeroOperand = DAG.getConstant(0, EVT::i8); SDValue SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand); Chain = getChain(SeqStart); SDValue OperFlag = getOutFlag(SeqStart); // To manage the data dependency @@ -1289,15 +1289,15 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, SDValue Hi = Callee.getOperand(1); SDValue Data_Lo, Data_Hi; - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Other, EVT::Flag); // Subtract 2 from Address to get the Lower part of DataAddress. - SDVTList VTList = DAG.getVTList(MVT::i8, MVT::Flag); + SDVTList VTList = DAG.getVTList(EVT::i8, EVT::Flag); Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo, - DAG.getConstant(2, MVT::i8)); - SDValue Ops[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)}; + DAG.getConstant(2, EVT::i8)); + SDValue Ops[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)}; Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, Ops, 3); - SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi); - Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH); + SDValue PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi); + Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH); SDValue Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(Call); @@ -1308,7 +1308,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, OperFlag = getOutFlag(SeqEnd); // Low part of Data Address - DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, MVT::i8, Call, OperFlag); + DataAddr_Lo = DAG.getNode(PIC16ISD::MTLO, dl, EVT::i8, Call, OperFlag); // Make the second call. SeqStart = DAG.getCALLSEQ_START(Chain, ZeroOperand); @@ -1317,13 +1317,13 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, // Subtract 1 from Address to get high part of data address. Data_Lo = DAG.getNode(ISD::SUBC, dl, VTList, Lo, - DAG.getConstant(1, MVT::i8)); - SDValue HiOps[3] = { Hi, DAG.getConstant(0, MVT::i8), Data_Lo.getValue(1)}; + DAG.getConstant(1, EVT::i8)); + SDValue HiOps[3] = { Hi, DAG.getConstant(0, EVT::i8), Data_Lo.getValue(1)}; Data_Hi = DAG.getNode(ISD::SUBE, dl, VTList, HiOps, 3); - PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, Data_Hi); + PCLATH = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, Data_Hi); // Use new Lo to make another CALLW - Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Data_Lo, PCLATH); + Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Data_Lo, PCLATH); Call = DAG.getNode(PIC16ISD::CALLW, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(Call); OperFlag = getOutFlag(Call); @@ -1332,7 +1332,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain, Chain = getChain(SeqEnd); OperFlag = getOutFlag(SeqEnd); // Hi part of Data Address - DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, MVT::i8, Call, OperFlag); + DataAddr_Hi = DAG.getNode(PIC16ISD::MTHI, dl, EVT::i8, Call, OperFlag); } SDValue @@ -1344,7 +1344,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) { - assert(Callee.getValueType() == MVT::i16 && + assert(Callee.getValueType() == EVT::i16 && "Don't know how to legalize this call node!!!"); // The flag to track if this is a direct or indirect call. @@ -1367,7 +1367,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Indirect addresses. Get the hi and lo parts of ptr. GetExpandedParts(Callee, DAG, Lo, Hi); // Connect Lo and Hi parts of the callee with the PIC16Connect - Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, Lo, Hi); + Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, Lo, Hi); // Read DataAddress only if we have to pass arguments or // read return value. @@ -1375,7 +1375,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, GetDataAddress(dl, Callee, Chain, DataAddr_Lo, DataAddr_Hi, DAG); } - SDValue ZeroOperand = DAG.getConstant(0, MVT::i8); + SDValue ZeroOperand = DAG.getConstant(0, EVT::i8); // Start the call sequence. // Carring the Constant 0 along the CALLSEQSTART @@ -1392,32 +1392,32 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Considering the GlobalAddressNode case here. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { GlobalValue *GV = G->getGlobal(); - Callee = DAG.getTargetGlobalAddress(GV, MVT::i8); + Callee = DAG.getTargetGlobalAddress(GV, EVT::i8); Name = G->getGlobal()->getName(); } else {// Considering the ExternalSymbol case here ExternalSymbolSDNode *ES = dyn_cast<ExternalSymbolSDNode>(Callee); - Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), MVT::i8); + Callee = DAG.getTargetExternalSymbol(ES->getSymbol(), EVT::i8); Name = ES->getSymbol(); } // Label for argument passing const char *argFrame = createESName(PAN::getArgsLabel(Name)); - ArgLabel = DAG.getTargetExternalSymbol(argFrame, MVT::i8); + ArgLabel = DAG.getTargetExternalSymbol(argFrame, EVT::i8); // Label for reading return value const char *retName = createESName(PAN::getRetvalLabel(Name)); - RetLabel = DAG.getTargetExternalSymbol(retName, MVT::i8); + RetLabel = DAG.getTargetExternalSymbol(retName, EVT::i8); } else { // if indirect call SDValue CodeAddr_Lo = Callee.getOperand(0); SDValue CodeAddr_Hi = Callee.getOperand(1); - /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, MVT::i8, CodeAddr_Lo, - DAG.getConstant(2, MVT::i8));*/ + /*CodeAddr_Lo = DAG.getNode(ISD::ADD, dl, EVT::i8, CodeAddr_Lo, + DAG.getConstant(2, EVT::i8));*/ // move Hi part in PCLATH - CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, MVT::i8, CodeAddr_Hi); - Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, MVT::i8, CodeAddr_Lo, + CodeAddr_Hi = DAG.getNode(PIC16ISD::MTPCLATH, dl, EVT::i8, CodeAddr_Hi); + Callee = DAG.getNode(PIC16ISD::PIC16Connect, dl, EVT::i8, CodeAddr_Lo, CodeAddr_Hi); } @@ -1435,7 +1435,7 @@ PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, OperFlag = getOutFlag(CallArgs); } - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue PICCall = DAG.getNode(PIC16ISD::CALL, dl, Tys, Chain, Callee, OperFlag); Chain = getChain(PICCall); @@ -1500,14 +1500,14 @@ SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. - assert (Op.getValueType() == MVT::i8 && "illegal Op to lower"); + assert (Op.getValueType() == EVT::i8 && "illegal Op to lower"); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { // Put one value on stack. SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); - return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1), + return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1), NewVal); } else { @@ -1519,7 +1519,7 @@ SDValue PIC16TargetLowering::LowerBinOp(SDValue Op, SelectionDAG &DAG) { // that affects carry. SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) { // We should have handled larger operands in type legalizer itself. - assert (Op.getValueType() == MVT::i8 && "illegal add to lower"); + assert (Op.getValueType() == EVT::i8 && "illegal add to lower"); DebugLoc dl = Op.getDebugLoc(); unsigned MemOp = 1; if (NeedToConvertToMemOp(Op, MemOp)) { @@ -1527,7 +1527,7 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) { SDValue NewVal = ConvertToMemOperand (Op.getOperand(MemOp), DAG, dl); // ADDC and ADDE produce two results. - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag); // ADDE has three operands, the last one is the carry bit. if (Op.getOpcode() == ISD::ADDE) @@ -1539,7 +1539,7 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) { NewVal); // ADD it is. It produces only one result. else - return DAG.getNode(Op.getOpcode(), dl, MVT::i8, Op.getOperand(MemOp ^ 1), + return DAG.getNode(Op.getOpcode(), dl, EVT::i8, Op.getOperand(MemOp ^ 1), NewVal); } else @@ -1549,7 +1549,7 @@ SDValue PIC16TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) { SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); // We should have handled larger operands in type legalizer itself. - assert (Op.getValueType() == MVT::i8 && "illegal sub to lower"); + assert (Op.getValueType() == EVT::i8 && "illegal sub to lower"); // Nothing to do if the first operand is already a direct load and it has // only one use. @@ -1559,7 +1559,7 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { // Put first operand on stack. SDValue NewVal = ConvertToMemOperand (Op.getOperand(0), DAG, dl); - SDVTList Tys = DAG.getVTList(MVT::i8, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::i8, EVT::Flag); switch (Op.getOpcode()) { default: assert (0 && "Opcode unknown."); @@ -1571,7 +1571,7 @@ SDValue PIC16TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) { return DAG.getNode(Op.getOpcode(), dl, Tys, NewVal, Op.getOperand(1)); break; case ISD::SUB: - return DAG.getNode(Op.getOpcode(), dl, MVT::i8, NewVal, Op.getOperand(1)); + return DAG.getNode(Op.getOpcode(), dl, EVT::i8, NewVal, Op.getOperand(1)); break; } } @@ -1613,13 +1613,13 @@ PIC16TargetLowering::LowerFormalArguments(SDValue Chain, // Create the <fname>.args external symbol. const char *tmpName = createESName(PAN::getArgsLabel(FuncName)); - SDValue ES = DAG.getTargetExternalSymbol(tmpName, MVT::i8); + SDValue ES = DAG.getTargetExternalSymbol(tmpName, EVT::i8); // Load arg values from the label + offset. - SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Other); - SDValue BS = DAG.getConstant(1, MVT::i8); + SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Other); + SDValue BS = DAG.getConstant(1, EVT::i8); for (unsigned i = 0; i < NumArgVals ; ++i) { - SDValue Offset = DAG.getConstant(i, MVT::i8); + SDValue Offset = DAG.getConstant(i, EVT::i8); SDValue PICLoad = DAG.getNode(PIC16ISD::PIC16LdArg, dl, VTs, Chain, ES, BS, Offset); Chain = getChain(PICLoad); @@ -1751,16 +1751,16 @@ SDValue PIC16TargetLowering::getPIC16Cmp(SDValue LHS, SDValue RHS, } } - PIC16CC = DAG.getConstant(CondCode, MVT::i8); + PIC16CC = DAG.getConstant(CondCode, EVT::i8); // These are signed comparisons. - SDValue Mask = DAG.getConstant(128, MVT::i8); + SDValue Mask = DAG.getConstant(128, EVT::i8); if (isSignedComparison(CondCode)) { - LHS = DAG.getNode (ISD::XOR, dl, MVT::i8, LHS, Mask); - RHS = DAG.getNode (ISD::XOR, dl, MVT::i8, RHS, Mask); + LHS = DAG.getNode (ISD::XOR, dl, EVT::i8, LHS, Mask); + RHS = DAG.getNode (ISD::XOR, dl, EVT::i8, RHS, Mask); } - SDVTList VTs = DAG.getVTList (MVT::i8, MVT::Flag); + SDVTList VTs = DAG.getVTList (EVT::i8, EVT::Flag); // We can use a subtract operation to set the condition codes. But // we need to put one operand in memory if required. // Nothing to do if the first operand is already a valid type (direct load @@ -1875,7 +1875,7 @@ SDValue PIC16TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) { SDValue PIC16CC; SDValue Cmp = getPIC16Cmp(LHS, RHS, ORIGCC, PIC16CC, DAG, dl); - return DAG.getNode(PIC16ISD::BRCOND, dl, MVT::Other, Chain, Dest, PIC16CC, + return DAG.getNode(PIC16ISD::BRCOND, dl, EVT::Other, Chain, Dest, PIC16CC, Cmp.getValue(1)); } diff --git a/lib/Target/PIC16/PIC16ISelLowering.h b/lib/Target/PIC16/PIC16ISelLowering.h index 968374c970..50691538c4 100644 --- a/lib/Target/PIC16/PIC16ISelLowering.h +++ b/lib/Target/PIC16/PIC16ISelLowering.h @@ -82,7 +82,7 @@ namespace llvm { /// DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT::SimpleValueType getSetCCResultType(MVT ValType) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT ValType) const; SDValue LowerShift(SDValue Op, SelectionDAG &DAG); SDValue LowerMUL(SDValue Op, SelectionDAG &DAG); SDValue LowerADD(SDValue Op, SelectionDAG &DAG); @@ -230,7 +230,7 @@ namespace llvm { const char *getPIC16LibcallName(PIC16ISD::PIC16Libcall Call); // Make PIC16 Libcall. - SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, MVT RetVT, + SDValue MakePIC16Libcall(PIC16ISD::PIC16Libcall Call, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, SelectionDAG &DAG, DebugLoc dl); diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index d77ce57189..77f1b12cfa 100644 --- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -64,13 +64,13 @@ namespace { /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } /// getI64Imm - Return a target constant with the specified value, of type /// i64. inline SDValue getI64Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i64); + return CurDAG->getTargetConstant(Imm, EVT::i64); } /// getSmallIPtrImm - Return a target constant of pointer type. @@ -286,7 +286,7 @@ SDNode *PPCDAGToDAGISel::getGlobalBaseReg() { MachineBasicBlock::iterator MBBI = FirstMBB.begin(); DebugLoc dl = DebugLoc::getUnknownLoc(); - if (PPCLowering.getPointerTy() == MVT::i32) { + if (PPCLowering.getPointerTy() == EVT::i32) { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); @@ -309,7 +309,7 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { return false; Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); else return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); @@ -323,7 +323,7 @@ static bool isIntS16Immediate(SDValue Op, short &Imm) { /// isInt32Immediate - This method tests to see if the node is a 32-bit constant /// operand. If so Imm will receive the 32-bit value. static bool isInt32Immediate(SDNode *N, unsigned &Imm) { - if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { + if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i32) { Imm = cast<ConstantSDNode>(N)->getZExtValue(); return true; } @@ -333,7 +333,7 @@ static bool isInt32Immediate(SDNode *N, unsigned &Imm) { /// isInt64Immediate - This method tests to see if the node is a 64-bit constant /// operand. If so Imm will receive the 64-bit value. static bool isInt64Immediate(SDNode *N, uint64_t &Imm) { - if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { + if (N->getOpcode() == ISD::Constant && N->getValueType(0) == EVT::i64) { Imm = cast<ConstantSDNode>(N)->getZExtValue(); return true; } @@ -381,7 +381,7 @@ bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask, unsigned &MB, unsigned &ME) { // Don't even go down this path for i64, since different logic will be // necessary for rldicl/rldicr/rldimi. - if (N->getValueType(0) != MVT::i32) + if (N->getValueType(0) != EVT::i32) return false; unsigned Shift = 32; @@ -485,7 +485,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) { SH &= 31; SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5); } } return 0; @@ -498,17 +498,17 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // Always select the LHS. unsigned Opc; - if (LHS.getValueType() == MVT::i32) { + if (LHS.getValueType() == EVT::i32) { unsigned Imm; if (CC == ISD::SETEQ || CC == ISD::SETNE) { if (isInt32Immediate(RHS, Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16((int)Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -520,36 +520,36 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // xoris r0,r3,0x1234 // cmplwi cr0,r0,0x5678 // beq cr0,L6 - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, MVT::i32, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, dl, EVT::i32, LHS, getI32Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, Xor, getI32Imm(Imm & 0xFFFF)), 0); } Opc = PPC::CMPLW; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt32Immediate(RHS, Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, dl, EVT::i32, LHS, getI32Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLW; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, MVT::i32, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPWI, dl, EVT::i32, LHS, getI32Imm((int)SImm & 0xFFFF)), 0); Opc = PPC::CMPW; } - } else if (LHS.getValueType() == MVT::i64) { + } else if (LHS.getValueType() == EVT::i64) { uint64_t Imm; if (CC == ISD::SETEQ || CC == ISD::SETNE) { if (isInt64Immediate(RHS.getNode(), Imm)) { // SETEQ/SETNE comparison with 16-bit immediate, fold it. if (isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // If this is a 16-bit signed immediate, fold it. if (isInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS, getI32Imm(Imm & 0xFFFF)), 0); // For non-equality comparisons, the default code would materialize the @@ -562,33 +562,33 @@ SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS, // cmpldi cr0,r0,0x5678 // beq cr0,L6 if (isUInt32(Imm)) { - SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, MVT::i64, LHS, + SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, dl, EVT::i64, LHS, getI64Imm(Imm >> 16)), 0); - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, Xor, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, Xor, getI64Imm(Imm & 0xFFFF)), 0); } } Opc = PPC::CMPLD; } else if (ISD::isUnsignedIntSetCC(CC)) { if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, dl, EVT::i64, LHS, getI64Imm(Imm & 0xFFFF)), 0); Opc = PPC::CMPLD; } else { short SImm; if (isIntS16Immediate(RHS, SImm)) - return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, MVT::i64, LHS, + return SDValue(CurDAG->getTargetNode(PPC::CMPDI, dl, EVT::i64, LHS, getI64Imm(SImm & 0xFFFF)), 0); Opc = PPC::CMPD; } - } else if (LHS.getValueType() == MVT::f32) { + } else if (LHS.getValueType() == EVT::f32) { Opc = PPC::FCMPUS; } else { - assert(LHS.getValueType() == MVT::f64 && "Unknown vt!"); + assert(LHS.getValueType() == EVT::f64 && "Unknown vt!"); Opc = PPC::FCMPUD; } - return SDValue(CurDAG->getTargetNode(Opc, dl, MVT::i32, LHS, RHS), 0); + return SDValue(CurDAG->getTargetNode(Opc, dl, EVT::i32, LHS, RHS), 0); } static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { @@ -670,27 +670,27 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { switch (CC) { default: break; case ISD::SETEQ: { - Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, MVT::i32, Op), 0); + Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, dl, EVT::i32, Op), 0); SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } case ISD::SETNE: { SDValue AD = - SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag, Op, getI32Imm(~0U)), 0); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op, + return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, AD, Op, AD.getValue(1)); } case ISD::SETLT: { SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } case ISD::SETGT: { SDValue T = - SDValue(CurDAG->getTargetNode(PPC::NEG, dl, MVT::i32, Op), 0); - T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, MVT::i32, T, Op), 0); + SDValue(CurDAG->getTargetNode(PPC::NEG, dl, EVT::i32, Op), 0); + T = SDValue(CurDAG->getTargetNode(PPC::ANDC, dl, EVT::i32, T, Op), 0); SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } } } else if (Imm == ~0U) { // setcc op, -1 @@ -698,33 +698,33 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { switch (CC) { default: break; case ISD::SETEQ: - Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag, Op, getI32Imm(1)), 0); - return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32, SDValue(CurDAG->getTargetNode(PPC::LI, dl, - MVT::i32, + EVT::i32, getI32Imm(0)), 0), Op.getValue(1)); case ISD::SETNE: { - Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, MVT::i32, Op, Op), 0); - SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + Op = SDValue(CurDAG->getTargetNode(PPC::NOR, dl, EVT::i32, Op, Op), 0); + SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag, Op, getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0), + return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, SDValue(AD, 0), Op, SDValue(AD, 1)); } case ISD::SETLT: { - SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, MVT::i32, Op, + SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, dl, EVT::i32, Op, getI32Imm(1)), 0); - SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, MVT::i32, AD, + SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, dl, EVT::i32, AD, Op), 0); SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } case ISD::SETGT: { SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) }; - Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), + Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op, + return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Op, getI32Imm(1)); } } @@ -738,29 +738,29 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { SDValue IntCR; // Force the ccreg into CR7. - SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32); + SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, EVT::i32); SDValue InFlag(0, 0); // Null incoming flag value. CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg, InFlag).getValue(1); if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1) - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg, + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32, CR7Reg, CCReg), 0); else - IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, CCReg), 0); + IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, CCReg), 0); SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31), getI32Imm(31), getI32Imm(31) }; if (OtherCondIdx == -1 && !Inv) - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); // Get the specified bit. SDValue Tmp = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0); if (Inv) { assert(OtherCondIdx == -1 && "Can't have split plus negation"); - return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1)); + return CurDAG->SelectNodeTo(N, PPC::XORI, EVT::i32, Tmp, getI32Imm(1)); } // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT. @@ -769,9 +769,9 @@ SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) { // Get the other bit of the comparison. Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31); SDValue OtherCond = - SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, MVT::i32, Ops, 4), 0); + SDValue(CurDAG->getTargetNode(PPC::RLWINM, dl, EVT::i32, Ops, 4), 0); - return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond); + return CurDAG->SelectNodeTo(N, PPC::OR, EVT::i32, Tmp, OtherCond); } @@ -787,7 +787,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { default: break; case ISD::Constant: { - if (N->getValueType(0) == MVT::i64) { + if (N->getValueType(0) == EVT::i64) { // Get 64 bit value. int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); // Assume no remaining bits. @@ -822,17 +822,17 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Simple value. if (isInt16(Imm)) { // Just the Lo bits. - Result = CurDAG->getTargetNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo)); + Result = CurDAG->getTargetNode(PPC::LI8, dl, EVT::i64, getI32Imm(Lo)); } else if (Lo) { // Handle the Hi bits. unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8; - Result = CurDAG->getTargetNode(OpC, dl, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getTargetNode(OpC, dl, EVT::i64, getI32Imm(Hi)); // And Lo bits. - Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64, SDValue(Result, 0), getI32Imm(Lo)); } else { // Just the Hi bits. - Result = CurDAG->getTargetNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi)); + Result = CurDAG->getTargetNode(PPC::LIS8, dl, EVT::i64, getI32Imm(Hi)); } // If no shift, we're done. @@ -840,18 +840,18 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // Shift for next step if the upper 32-bits were not zero. if (Imm) { - Result = CurDAG->getTargetNode(PPC::RLDICR, dl, MVT::i64, + Result = CurDAG->getTargetNode(PPC::RLDICR, dl, EVT::i64, SDValue(Result, 0), getI32Imm(Shift), getI32Imm(63 - Shift)); } // Add in the last bits as required. if ((Hi = (Remainder >> 16) & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORIS8, dl, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORIS8, dl, EVT::i64, SDValue(Result, 0), getI32Imm(Hi)); } if ((Lo = Remainder & 0xFFFF)) { - Result = CurDAG->getTargetNode(PPC::ORI8, dl, MVT::i64, + Result = CurDAG->getTargetNode(PPC::ORI8, dl, EVT::i64, SDValue(Result, 0), getI32Imm(Lo)); } @@ -868,7 +868,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { case ISD::FrameIndex: { int FI = cast<FrameIndexSDNode>(N)->getIndex(); SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType()); - unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8; + unsigned Opc = Op.getValueType() == EVT::i32 ? PPC::ADDI : PPC::ADDI8; if (N->hasOneUse()) return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI, getSmallIPtrImm(0)); @@ -880,10 +880,10 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue InFlag = N->getOperand(1); // Use MFOCRF if supported. if (PPCSubTarget.isGigaProcessor()) - return CurDAG->getTargetNode(PPC::MFOCRF, dl, MVT::i32, + return CurDAG->getTargetNode(PPC::MFOCRF, dl, EVT::i32, N->getOperand(0), InFlag); else - return CurDAG->getTargetNode(PPC::MFCR, dl, MVT::i32, InFlag); + return CurDAG->getTargetNode(PPC::MFCR, dl, EVT::i32, InFlag); } case ISD::SDIV: { @@ -897,19 +897,19 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue N0 = N->getOperand(0); if ((signed)Imm > 0 && isPowerOf2_32(Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag, N0, getI32Imm(Log2_32(Imm))); - return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32, + return CurDAG->SelectNodeTo(N, PPC::ADDZE, EVT::i32, SDValue(Op, 0), SDValue(Op, 1)); } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) { SDNode *Op = - CurDAG->getTargetNode(PPC::SRAWI, dl, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::SRAWI, dl, EVT::i32, EVT::Flag, N0, getI32Imm(Log2_32(-Imm))); SDValue PT = - SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, MVT::i32, + SDValue(CurDAG->getTargetNode(PPC::ADDZE, dl, EVT::i32, SDValue(Op, 0), SDValue(Op, 1)), 0); - return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT); + return CurDAG->SelectNodeTo(N, PPC::NEG, EVT::i32, PT); } } @@ -920,7 +920,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { case ISD::LOAD: { // Handle preincrement loads. LoadSDNode *LD = cast<LoadSDNode>(Op); - MVT LoadedVT = LD->getMemoryVT(); + EVT LoadedVT = LD->getMemoryVT(); // Normal loads are handled by code generated from the .td file. if (LD->getAddressingMode() != ISD::PRE_INC) @@ -932,28 +932,28 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { unsigned Opcode; bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD; - if (LD->getValueType(0) != MVT::i64) { + if (LD->getValueType(0) != EVT::i64) { // Handle PPC32 integer and normal FP loads. - assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { default: llvm_unreachable("Invalid PPC load type!"); - case MVT::f64: Opcode = PPC::LFDU; break; - case MVT::f32: Opcode = PPC::LFSU; break; - case MVT::i32: Opcode = PPC::LWZU; break; - case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; - case MVT::i1: - case MVT::i8: Opcode = PPC::LBZU; break; + case EVT::f64: Opcode = PPC::LFDU; break; + case EVT::f32: Opcode = PPC::LFSU; break; + case EVT::i32: Opcode = PPC::LWZU; break; + case EVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break; + case EVT::i1: + case EVT::i8: Opcode = PPC::LBZU; break; } } else { - assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!"); - assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load"); + assert(LD->getValueType(0) == EVT::i64 && "Unknown load result type!"); + assert((!isSExt || LoadedVT == EVT::i16) && "Invalid sext update load"); switch (LoadedVT.getSimpleVT()) { default: llvm_unreachable("Invalid PPC load type!"); - case MVT::i64: Opcode = PPC::LDU; break; - case MVT::i32: Opcode = PPC::LWZU8; break; - case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; - case MVT::i1: - case MVT::i8: Opcode = PPC::LBZU8; break; + case EVT::i64: Opcode = PPC::LDU; break; + case EVT::i32: Opcode = PPC::LWZU8; break; + case EVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break; + case EVT::i1: + case EVT::i8: Opcode = PPC::LBZU8; break; } } @@ -963,7 +963,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { // FIXME: PPC64 return CurDAG->getTargetNode(Opcode, dl, LD->getValueType(0), PPCLowering.getPointerTy(), - MVT::Other, Ops, 3); + EVT::Other, Ops, 3); } else { llvm_unreachable("R+R preindex loads not supported yet!"); } @@ -978,7 +978,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) { SDValue Val = N->getOperand(0).getOperand(0); SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } // If this is just a masked value where the input is not handled above, and // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm @@ -987,7 +987,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { N->getOperand(0).getOpcode() != ISD::ROTL) { SDValue Val = N->getOperand(0); SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } // AND X, 0 -> 0, not "rlwinm 32". if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) { @@ -1005,7 +1005,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue Ops[] = { N->getOperand(0).getOperand(0), N->getOperand(0).getOperand(1), getI32Imm(0), getI32Imm(MB),getI32Imm(ME) }; - return CurDAG->getTargetNode(PPC::RLWIMI, dl, MVT::i32, Ops, 5); + return CurDAG->getTargetNode(PPC::RLWIMI, dl, EVT::i32, Ops, 5); } } @@ -1013,7 +1013,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { break; } case ISD::OR: - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) if (SDNode *I = SelectBitfieldInsert(N)) return I; @@ -1025,7 +1025,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { isRotateAndMask(N, Imm, true, SH, MB, ME)) { SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } // Other cases are autogenerated. @@ -1037,7 +1037,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { isRotateAndMask(N, Imm, true, SH, MB, ME)) { SDValue Ops[] = { N->getOperand(0).getOperand(0), getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) }; - return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::RLWINM, EVT::i32, Ops, 4); } // Other cases are autogenerated. @@ -1053,11 +1053,11 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { if (N1C->isNullValue() && N3C->isNullValue() && N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && // FIXME: Implement this optzn for PPC64. - N->getValueType(0) == MVT::i32) { + N->getValueType(0) == EVT::i32) { SDNode *Tmp = - CurDAG->getTargetNode(PPC::ADDIC, dl, MVT::i32, MVT::Flag, + CurDAG->getTargetNode(PPC::ADDIC, dl, EVT::i32, EVT::Flag, N->getOperand(0), getI32Imm(~0U)); - return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, + return CurDAG->SelectNodeTo(N, PPC::SUBFE, EVT::i32, SDValue(Tmp, 0), N->getOperand(0), SDValue(Tmp, 1)); } @@ -1066,13 +1066,13 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { unsigned BROpc = getPredicateForSetCC(CC); unsigned SelectCCOp; - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) SelectCCOp = PPC::SELECT_CC_I4; - else if (N->getValueType(0) == MVT::i64) + else if (N->getValueType(0) == EVT::i64) SelectCCOp = PPC::SELECT_CC_I8; - else if (N->getValueType(0) == MVT::f32) + else if (N->getValueType(0) == EVT::f32) SelectCCOp = PPC::SELECT_CC_F4; - else if (N->getValueType(0) == MVT::f64) + else if (N->getValueType(0) == EVT::f64) SelectCCOp = PPC::SELECT_CC_F8; else SelectCCOp = PPC::SELECT_CC_VRRC; @@ -1092,23 +1092,23 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()); SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3), N->getOperand(0), N->getOperand(4) }; - return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5); + return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 5); } case ISD::BR_CC: { ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, N->getOperand(4), N->getOperand(0) }; - return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4); + return CurDAG->SelectNodeTo(N, PPC::BCC, EVT::Other, Ops, 4); } case ISD::BRIND: { // FIXME: Should custom lower this. SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); - unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; - Chain = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Target, + unsigned Opc = Target.getValueType() == EVT::i32 ? PPC::MTCTR : PPC::MTCTR8; + Chain = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Target, Chain), 0); - return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); + return CurDAG->SelectNodeTo(N, PPC::BCTR, EVT::Other, Chain); } case ISD::DECLARE: { SDValue Chain = N->getOperand(0); @@ -1149,7 +1149,7 @@ SDNode *PPCDAGToDAGISel::Select(SDValue Op) { SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy()); SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy()); return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE, - MVT::Other, Tmp1, Tmp2, Chain); + EVT::Other, Tmp1, Tmp2, Chain); } } diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index a63bacd456..0debf67c87 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -38,17 +38,17 @@ #include "llvm/DerivedTypes.h" using namespace llvm; -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, - MVT &LocVT, +static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, + EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); -static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, - MVT &LocVT, +static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, + EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State); @@ -74,216 +74,216 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) setUseUnderscoreLongJmp(true); // Set up the register classes. - addRegisterClass(MVT::i32, PPC::GPRCRegisterClass); - addRegisterClass(MVT::f32, PPC::F4RCRegisterClass); - addRegisterClass(MVT::f64, PPC::F8RCRegisterClass); + addRegisterClass(EVT::i32, PPC::GPRCRegisterClass); + addRegisterClass(EVT::f32, PPC::F4RCRegisterClass); + addRegisterClass(EVT::f64, PPC::F8RCRegisterClass); // PowerPC has an i16 but no i8 (or i1) SEXTLOAD - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); // PowerPC has pre-inc load and store's. - setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); - setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); - setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); - setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); - setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); - setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); - setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); - setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); - setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); - setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); + setIndexedLoadAction(ISD::PRE_INC, EVT::i1, Legal); + setIndexedLoadAction(ISD::PRE_INC, EVT::i8, Legal); + setIndexedLoadAction(ISD::PRE_INC, EVT::i16, Legal); + setIndexedLoadAction(ISD::PRE_INC, EVT::i32, Legal); + setIndexedLoadAction(ISD::PRE_INC, EVT::i64, Legal); + setIndexedStoreAction(ISD::PRE_INC, EVT::i1, Legal); + setIndexedStoreAction(ISD::PRE_INC, EVT::i8, Legal); + setIndexedStoreAction(ISD::PRE_INC, EVT::i16, Legal); + setIndexedStoreAction(ISD::PRE_INC, EVT::i32, Legal); + setIndexedStoreAction(ISD::PRE_INC, EVT::i64, Legal); // This is used in the ppcf128->int sequence. Note it has different semantics // from FP_ROUND: that rounds to nearest, this rounds to zero. - setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom); + setOperationAction(ISD::FP_ROUND_INREG, EVT::ppcf128, Custom); // PowerPC has no SREM/UREM instructions - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i64, Expand); - setOperationAction(ISD::UREM, MVT::i64, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i64, Expand); + setOperationAction(ISD::UREM, EVT::i64, Expand); // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM. - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i64, Expand); - setOperationAction(ISD::SDIVREM, MVT::i64, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand); + setOperationAction(ISD::UDIVREM, EVT::i32, Expand); + setOperationAction(ISD::SDIVREM, EVT::i32, Expand); + setOperationAction(ISD::UDIVREM, EVT::i64, Expand); + setOperationAction(ISD::SDIVREM, EVT::i64, Expand); // We don't support sin/cos/sqrt/fmod/pow - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); - setOperationAction(ISD::FPOW , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f32, Expand); + setOperationAction(ISD::FSIN , EVT::f64, Expand); + setOperationAction(ISD::FCOS , EVT::f64, Expand); + setOperationAction(ISD::FREM , EVT::f64, Expand); + setOperationAction(ISD::FPOW , EVT::f64, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); + setOperationAction(ISD::FREM , EVT::f32, Expand); + setOperationAction(ISD::FPOW , EVT::f32, Expand); - setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom); + setOperationAction(ISD::FLT_ROUNDS_, EVT::i32, Custom); // If we're enabling GP optimizations, use hardware square root if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) { - setOperationAction(ISD::FSQRT, MVT::f64, Expand); - setOperationAction(ISD::FSQRT, MVT::f32, Expand); + setOperationAction(ISD::FSQRT, EVT::f64, Expand); + setOperationAction(ISD::FSQRT, EVT::f32, Expand); } - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand); // PowerPC does not have BSWAP, CTPOP or CTTZ - setOperationAction(ISD::BSWAP, MVT::i32 , Expand); - setOperationAction(ISD::CTPOP, MVT::i32 , Expand); - setOperationAction(ISD::CTTZ , MVT::i32 , Expand); - setOperationAction(ISD::BSWAP, MVT::i64 , Expand); - setOperationAction(ISD::CTPOP, MVT::i64 , Expand); - setOperationAction(ISD::CTTZ , MVT::i64 , Expand); + setOperationAction(ISD::BSWAP, EVT::i32 , Expand); + setOperationAction(ISD::CTPOP, EVT::i32 , Expand); + setOperationAction(ISD::CTTZ , EVT::i32 , Expand); + setOperationAction(ISD::BSWAP, EVT::i64 , Expand); + setOperationAction(ISD::CTPOP, EVT::i64 , Expand); + setOperationAction(ISD::CTTZ , EVT::i64 , Expand); // PowerPC does not have ROTR - setOperationAction(ISD::ROTR, MVT::i32 , Expand); - setOperationAction(ISD::ROTR, MVT::i64 , Expand); + setOperationAction(ISD::ROTR, EVT::i32 , Expand); + setOperationAction(ISD::ROTR, EVT::i64 , Expand); // PowerPC does not have Select - setOperationAction(ISD::SELECT, MVT::i32, Expand); - setOperationAction(ISD::SELECT, MVT::i64, Expand); - setOperationAction(ISD::SELECT, MVT::f32, Expand); - setOperationAction(ISD::SELECT, MVT::f64, Expand); + setOperationAction(ISD::SELECT, EVT::i32, Expand); + setOperationAction(ISD::SELECT, EVT::i64, Expand); + setOperationAction(ISD::SELECT, EVT::f32, Expand); + setOperationAction(ISD::SELECT, EVT::f64, Expand); // PowerPC wants to turn select_cc of FP into fsel when possible. - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f64, Custom); // PowerPC wants to optimize integer setcc a bit - setOperationAction(ISD::SETCC, MVT::i32, Custom); + setOperationAction(ISD::SETCC, EVT::i32, Custom); // PowerPC does not have BRCOND which requires SetCC - setOperationAction(ISD::BRCOND, MVT::Other, Expand); + setOperationAction(ISD::BRCOND, EVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores. - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom); // PowerPC does not have [U|S]INT_TO_FP - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::SINT_TO_FP, EVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::i64, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::f64, Expand); // We cannot sextinreg(i1). Expand to shifts. - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); // Support label based line numbers. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); - setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); - setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); - setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); - setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); + setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand); + setOperationAction(ISD::EHSELECTION, EVT::i64, Expand); + setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand); + setOperationAction(ISD::EHSELECTION, EVT::i32, Expand); // We want to legalize GlobalAddress and ConstantPool nodes into the // appropriate instructions to materialize the address. - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); - setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); - setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::JumpTable, MVT::i64, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom); + setOperationAction(ISD::ConstantPool, EVT::i32, Custom); + setOperationAction(ISD::JumpTable, EVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i64, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom); + setOperationAction(ISD::ConstantPool, EVT::i64, Custom); + setOperationAction(ISD::JumpTable, EVT::i64, Custom); // TRAP is legal. - setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::TRAP, EVT::Other, Legal); // TRAMPOLINE is custom lowered. - setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); + setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom); // VASTART needs to be custom lowered to use the VarArgsFrameIndex - setOperationAction(ISD::VASTART , MVT::Other, Custom); + setOperationAction(ISD::VASTART , EVT::Other, Custom); // VAARG is custom lowered with the SVR4 ABI if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) - setOperationAction(ISD::VAARG, MVT::Other, Custom); + setOperationAction(ISD::VAARG, EVT::Other, Custom); else - setOperationAction(ISD::VAARG, MVT::Other, Expand); + setOperationAction(ISD::VAARG, EVT::Other, Expand); // Use the default implementation. - setOperationAction(ISD::VACOPY , MVT::Other, Expand); - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom); + setOperationAction(ISD::VACOPY , EVT::Other, Expand); + setOperationAction(ISD::VAEND , EVT::Other, Expand); + setOperationAction(ISD::STACKSAVE , EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE , EVT::Other, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64 , Custom); // We want to custom lower some of our intrinsics. - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom); // Comparisons that require checking two conditions. - setCondCodeAction(ISD::SETULT, MVT::f32, Expand); - setCondCodeAction(ISD::SETULT, MVT::f64, Expand); - setCondCodeAction(ISD::SETUGT, MVT::f32, Expand); - setCondCodeAction(ISD::SETUGT, MVT::f64, Expand); - setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand); - setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand); - setCondCodeAction(ISD::SETOGE, MVT::f32, Expand); - setCondCodeAction(ISD::SETOGE, MVT::f64, Expand); - setCondCodeAction(ISD::SETOLE, MVT::f32, Expand); - setCondCodeAction(ISD::SETOLE, MVT::f64, Expand); - setCondCodeAction(ISD::SETONE, MVT::f32, Expand); - setCondCodeAction(ISD::SETONE, MVT::f64, Expand); + setCondCodeAction(ISD::SETULT, EVT::f32, Expand); + setCondCodeAction(ISD::SETULT, EVT::f64, Expand); + setCondCodeAction(ISD::SETUGT, EVT::f32, Expand); + setCondCodeAction(ISD::SETUGT, EVT::f64, Expand); + setCondCodeAction(ISD::SETUEQ, EVT::f32, Expand); + setCondCodeAction(ISD::SETUEQ, EVT::f64, Expand); + setCondCodeAction(ISD::SETOGE, EVT::f32, Expand); + setCondCodeAction(ISD::SETOGE, EVT::f64, Expand); + setCondCodeAction(ISD::SETOLE, EVT::f32, Expand); + setCondCodeAction(ISD::SETOLE, EVT::f64, Expand); + setCondCodeAction(ISD::SETONE, EVT::f32, Expand); + setCondCodeAction(ISD::SETONE, EVT::f64, Expand); if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) { // They also have instructions for converting between i64 and fp. - setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); - setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); - setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); + setOperationAction(ISD::FP_TO_SINT, EVT::i64, Custom); + setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand); + setOperationAction(ISD::SINT_TO_FP, EVT::i64, Custom); + setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand); // This is just the low 32 bits of a (signed) fp->i64 conversion. // We cannot do this with Promote because i64 is not a legal type. - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Custom); // FIXME: disable this lowered code. This generates 64-bit register values, // and we don't model the fact that the top part is clobbered by calls. We // need to flag these together so that the value isn't live across a call. - //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + //setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom); } else { // PowerPC does not have FP_TO_UINT on 32-bit implementations. - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand); } if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) { // 64-bit PowerPC implementations can support i64 types directly - addRegisterClass(MVT::i64, PPC::G8RCRegisterClass); + addRegisterClass(EVT::i64, PPC::G8RCRegisterClass); // BUILD_PAIR can't be handled natively, and should be expanded to shl/or - setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); + setOperationAction(ISD::BUILD_PAIR, EVT::i64, Expand); // 64-bit PowerPC wants to expand i128 shifts itself. - setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom); - setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom); - setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom); + setOperationAction(ISD::SHL_PARTS, EVT::i64, Custom); + setOperationAction(ISD::SRA_PARTS, EVT::i64, Custom); + setOperationAction(ISD::SRL_PARTS, EVT::i64, Custom); } else { // 32-bit PowerPC wants to expand i64 shifts itself. - setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom); + setOperationAction(ISD::SHL_PARTS, EVT::i32, Custom); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Custom); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Custom); } if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) { // First set operation action for all vector types to expand. Then we // will selectively turn on ones that can be effectively codegen'd. - for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { - MVT::SimpleValueType VT = (MVT::SimpleValueType)i; + for (unsigned i = (unsigned)EVT::FIRST_VECTOR_VALUETYPE; + i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) { + EVT::SimpleValueType VT = (EVT::SimpleValueType)i; // add/sub are legal for all supported vector VT's. setOperationAction(ISD::ADD , VT, Legal); @@ -291,21 +291,21 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) // We promote all shuffles to v16i8. setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote); - AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8); + AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, EVT::v16i8); // We promote all non-typed operations to v4i32. setOperationAction(ISD::AND , VT, Promote); - AddPromotedToType (ISD::AND , VT, MVT::v4i32); + AddPromotedToType (ISD::AND , VT, EVT::v4i32); setOperationAction(ISD::OR , VT, Promote); - AddPromotedToType (ISD::OR , VT, MVT::v4i32); + AddPromotedToType (ISD::OR , VT, EVT::v4i32); setOperationAction(ISD::XOR , VT, Promote); - AddPromotedToType (ISD::XOR , VT, MVT::v4i32); + AddPromotedToType (ISD::XOR , VT, EVT::v4i32); setOperationAction(ISD::LOAD , VT, Promote); - AddPromotedToType (ISD::LOAD , VT, MVT::v4i32); + AddPromotedToType (ISD::LOAD , VT, EVT::v4i32); setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v4i32); + AddPromotedToType (ISD::SELECT, VT, EVT::v4i32); setOperationAction(ISD::STORE, VT, Promote); - AddPromotedToType (ISD::STORE, VT, MVT::v4i32); + AddPromotedToType (ISD::STORE, VT, EVT::v4i32); // No other operations are legal. setOperationAction(ISD::MUL , VT, Expand); @@ -331,35 +331,35 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM) // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle // with merges, splats, etc. - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom); - - setOperationAction(ISD::AND , MVT::v4i32, Legal); - setOperationAction(ISD::OR , MVT::v4i32, Legal); - setOperationAction(ISD::XOR , MVT::v4i32, Legal); - setOperationAction(ISD::LOAD , MVT::v4i32, Legal); - setOperationAction(ISD::SELECT, MVT::v4i32, Expand); - setOperationAction(ISD::STORE , MVT::v4i32, Legal); - - addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass); - addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass); - addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass); - addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass); - - setOperationAction(ISD::MUL, MVT::v4f32, Legal); - setOperationAction(ISD::MUL, MVT::v4i32, Custom); - setOperationAction(ISD::MUL, MVT::v8i16, Custom); - setOperationAction(ISD::MUL, MVT::v16i8, Custom); - - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom); - - setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v16i8, Custom); + + setOperationAction(ISD::AND , EVT::v4i32, Legal); + setOperationAction(ISD::OR , EVT::v4i32, Legal); + setOperationAction(ISD::XOR , EVT::v4i32, Legal); + setOperationAction(ISD::LOAD , EVT::v4i32, Legal); + setOperationAction(ISD::SELECT, EVT::v4i32, Expand); + setOperationAction(ISD::STORE , EVT::v4i32, Legal); + + addRegisterClass(EVT::v4f32, PPC::VRRCRegisterClass); + addRegisterClass(EVT::v4i32, PPC::VRRCRegisterClass); + addRegisterClass(EVT::v8i16, PPC::VRRCRegisterClass); + addRegisterClass(EVT::v16i8, PPC::VRRCRegisterClass); + + setOperationAction(ISD::MUL, EVT::v4f32, Legal); + setOperationAction(ISD::MUL, EVT::v4i32, Custom); + setOperationAction(ISD::MUL, EVT::v8i16, Custom); + setOperationAction(ISD::MUL, EVT::v16i8, Custom); + + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4f32, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i32, Custom); + + setOperationAction(ISD::BUILD_VECTOR, EVT::v16i8, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v8i16, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v4i32, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom); } - setShiftAmountType(MVT::i32); + setShiftAmountType(EVT::i32); setBooleanContents(ZeroOrOneBooleanContent); if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { @@ -449,8 +449,8 @@ const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const { } } -MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(MVT VT) const { - return MVT::i32; +EVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const { + return EVT::i32; } /// getFunctionAlignment - Return the Log2 alignment of this function. @@ -523,7 +523,7 @@ bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) { /// static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize, unsigned LHSStart, unsigned RHSStart) { - assert(N->getValueType(0) == MVT::v16i8 && + assert(N->getValueType(0) == EVT::v16i8 && "PPC only supports shuffles by bytes!"); assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) && "Unsupported merge size!"); @@ -561,7 +561,7 @@ bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize, /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift /// amount, otherwise return -1. int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { - assert(N->getValueType(0) == MVT::v16i8 && + assert(N->getValueType(0) == EVT::v16i8 && "PPC only supports shuffles by bytes!"); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); @@ -597,7 +597,7 @@ int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) { /// specifies a splat of a single element that is suitable for input to /// VSPLTB/VSPLTH/VSPLTW. bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) { - assert(N->getValueType(0) == MVT::v16i8 && + assert(N->getValueType(0) == EVT::v16i8 && (EltSize == 1 || EltSize == 2 || EltSize == 4)); // This is a splat operation if each element of the permute is the same, and @@ -694,17 +694,17 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { // Finally, check the least significant entry. if (LeadingZero) { if (UniquedVals[Multiple-1].getNode() == 0) - return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef + return DAG.getTargetConstant(0, EVT::i32); // 0,0,0,undef int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue(); if (Val < 16) - return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4) + return DAG.getTargetConstant(Val, EVT::i32); // 0,0,0,4 -> vspltisw(4) } if (LeadingOnes) { if (UniquedVals[Multiple-1].getNode() == 0) - return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef + return DAG.getTargetConstant(~0U, EVT::i32); // -1,-1,-1,undef int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue(); if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2) - return DAG.getTargetConstant(Val, MVT::i32); + return DAG.getTargetConstant(Val, EVT::i32); } return SDValue(); @@ -726,7 +726,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) { Value = CN->getZExtValue(); } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) { - assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!"); + assert(CN->getValueType(0) == EVT::f32 && "Only one legal FP vector type!"); Value = FloatToBits(CN->getValueAPF().convertToFloat()); } @@ -756,7 +756,7 @@ SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) { // Finally, if this value fits in a 5 bit sext field, return it if (((MaskVal << (32-5)) >> (32-5)) == MaskVal) - return DAG.getTargetConstant(MaskVal, MVT::i32); + return DAG.getTargetConstant(MaskVal, EVT::i32); return SDValue(); } @@ -773,7 +773,7 @@ static bool isIntS16Immediate(SDNode *N, short &Imm) { return false; Imm = (short)cast<ConstantSDNode>(N)->getZExtValue(); - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue(); else return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue(); @@ -846,7 +846,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, if (N.getOpcode() == ISD::ADD) { short imm = 0; if (isIntS16Immediate(N.getOperand(1), imm)) { - Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); + Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32); if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); } else { @@ -880,7 +880,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, // If all of the bits are known zero on the LHS or RHS, the add won't // carry. Base = N.getOperand(0); - Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32); + Disp = DAG.getTargetConstant((int)imm & 0xFFFF, EVT::i32); return true; } } @@ -897,15 +897,15 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp, } // Handle 32-bit sext immediates with LIS + addr mode. - if (CN->getValueType(0) == MVT::i32 || + if (CN->getValueType(0) == EVT::i32 || (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { int Addr = (int)CN->getZExtValue(); // Otherwise, break this down into an LIS + disp. - Disp = DAG.getTargetConstant((short)Addr, MVT::i32); + Disp = DAG.getTargetConstant((short)Addr, EVT::i32); - Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32); - unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; + Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, EVT::i32); + unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8; Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0); return true; } @@ -960,7 +960,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, if (N.getOpcode() == ISD::ADD) { short imm = 0; if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) { - Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); + Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32); if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) { Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType()); } else { @@ -993,7 +993,7 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, // If all of the bits are known zero on the LHS or RHS, the add won't // carry. Base = N.getOperand(0); - Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32); + Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, EVT::i32); return true; } } @@ -1010,14 +1010,14 @@ bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp, } // Fold the low-part of 32-bit absolute addresses into addr mode. - if (CN->getValueType(0) == MVT::i32 || + if (CN->getValueType(0) == EVT::i32 || (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) { int Addr = (int)CN->getZExtValue(); // Otherwise, break this down into an LIS + disp. - Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32); - Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32); - unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8; + Disp = DAG.getTargetConstant((short)Addr >> 2, EVT::i32); + Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, EVT::i32); + unsigned Opc = CN->getValueType(0) == EVT::i32 ? PPC::LIS : PPC::LIS8; Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0); return true; } @@ -1044,7 +1044,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, if (!EnablePPCPreinc) return false; SDValue Ptr; - MVT VT; + EVT VT; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); VT = LD->getMemoryVT(); @@ -1063,7 +1063,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, // TODO: Check reg+reg first. // LDU/STU use reg+imm*4, others use reg+imm. - if (VT != MVT::i64) { + if (VT != EVT::i64) { // reg + imm if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) return false; @@ -1076,7 +1076,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of // sext i32 to i64 when addr mode is r+i. - if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 && + if (LD->getValueType(0) == EVT::i64 && LD->getMemoryVT() == EVT::i32 && LD->getExtensionType() == ISD::SEXTLOAD && isa<ConstantSDNode>(Offset)) return false; @@ -1092,7 +1092,7 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); Constant *C = CP->getConstVal(); SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment()); @@ -1126,7 +1126,7 @@ SDValue PPCTargetLowering::LowerConstantPool(SDValue Op, } SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); SDValue Zero = DAG.getConstant(0, PtrVT); @@ -1166,7 +1166,7 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op, SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset()); @@ -1214,17 +1214,17 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { // fold the new nodes. if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { if (C->isNullValue() && CC == ISD::SETEQ) { - MVT VT = Op.getOperand(0).getValueType(); + EVT VT = Op.getOperand(0).getValueType(); SDValue Zext = Op.getOperand(0); - if (VT.bitsLT(MVT::i32)) { - VT = MVT::i32; + if (VT.bitsLT(EVT::i32)) { + VT = EVT::i32; Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0)); } unsigned Log2b = Log2_32(VT.getSizeInBits()); SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext); SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz, - DAG.getConstant(Log2b, MVT::i32)); - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc); + DAG.getConstant(Log2b, EVT::i32)); + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Scc); } // Leave comparisons against 0 and -1 alone for now, since they're usually // optimized. FIXME: revisit this when we can custom lower all setcc @@ -1238,9 +1238,9 @@ SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { // condition register, reading it back out, and masking the correct bit. The // normal approach here uses sub to do this instead of xor. Using xor exposes // the result to other bit-twiddling opportunities. - MVT LHSVT = Op.getOperand(0).getValueType(); + EVT LHSVT = Op.getOperand(0).getValueType(); if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0), Op.getOperand(1)); return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC); @@ -1266,8 +1266,8 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { SDValue Nest = Op.getOperand(3); // 'nest' parameter value DebugLoc dl = Op.getDebugLoc(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - bool isPPC64 = (PtrVT == MVT::i64); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = (PtrVT == EVT::i64); const Type *IntPtrTy = DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(); @@ -1279,7 +1279,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { // TrampSize == (isPPC64 ? 48 : 40); Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, - isPPC64 ? MVT::i64 : MVT::i32); + isPPC64 ? EVT::i64 : EVT::i32); Args.push_back(Entry); Entry.Node = FPtr; Args.push_back(Entry); @@ -1287,7 +1287,7 @@ SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) { // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg) std::pair<SDValue, SDValue> CallResult = - LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), + LowerCallTo(Chain, Op.getValueType().getTypeForEVT(), false, false, false, false, 0, CallingConv::C, false, /*isReturnValueUsed=*/true, DAG.getExternalSymbol("__trampoline_setup", PtrVT), @@ -1310,7 +1310,7 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, if (Subtarget.isDarwinABI()) { // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0); @@ -1341,11 +1341,11 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, // } va_list[1]; - SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32); - SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32); + SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, EVT::i32); + SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, EVT::i32); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT); SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT); @@ -1363,14 +1363,14 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, // Store first byte : number of int regs SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR, - Op.getOperand(1), SV, 0, MVT::i8); + Op.getOperand(1), SV, 0, EVT::i8); uint64_t nextOffset = FPROffset; SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1), ConstFPROffset); // Store second byte : number of float regs SDValue secondStore = - DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8); + DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, EVT::i8); nextOffset += StackOffset; nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset); @@ -1387,15 +1387,15 @@ SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG, #include "PPCGenCallingConv.inc" -static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT, +static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { return true; } -static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, - MVT &LocVT, +static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT, + EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -1421,8 +1421,8 @@ static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT, return false; } -static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT, - MVT &LocVT, +static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT, + EVT &LocVT, CCValAssign::LocInfo &LocInfo, ISD::ArgFlagsTy &ArgFlags, CCState &State) { @@ -1469,7 +1469,7 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) { /// CalculateStackSlotSize - Calculates the size reserved for this argument on /// the stack. -static unsigned CalculateStackSlotSize(MVT ArgVT, ISD::ArgFlagsTy Flags, +static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags, unsigned PtrByteSize) { unsigned ArgSize = ArgVT.getSizeInBits()/8; if (Flags.isByVal()) @@ -1536,7 +1536,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4( MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Potential tail calls could cause overwriting of argument stack slots. bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast)); unsigned PtrByteSize = 4; @@ -1557,24 +1557,24 @@ PPCTargetLowering::LowerFormalArguments_SVR4( // Arguments stored in registers. if (VA.isRegLoc()) { TargetRegisterClass *RC; - MVT ValVT = VA.getValVT(); + EVT ValVT = VA.getValVT(); switch (ValVT.getSimpleVT()) { default: llvm_unreachable("ValVT not supported by formal arguments Lowering"); - case MVT::i32: + case EVT::i32: RC = PPC::GPRCRegisterClass; break; - case MVT::f32: + case EVT::f32: RC = PPC::F4RCRegisterClass; break; - case MVT::f64: + case EVT::f64: RC = PPC::F8RCRegisterClass; break; - case MVT::v16i8: - case MVT::v8i16: - case MVT::v4i32: - case MVT::v4f32: + case EVT::v16i8: + case EVT::v8i16: + case EVT::v4i32: + case EVT::v4f32: RC = PPC::VRRCRegisterClass; break; } @@ -1652,7 +1652,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4( // Make room for NumGPArgRegs and NumFPArgRegs. int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 + - NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8; + NumFPArgRegs * EVT(EVT::f64).getSizeInBits()/8; VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8, CCInfo.getNextStackOffset()); @@ -1693,11 +1693,11 @@ PPCTargetLowering::LowerFormalArguments_SVR4( // on the stack. unsigned FPRIndex = 0; for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) { - SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64); + SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], EVT::f64); SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, + SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } @@ -1705,11 +1705,11 @@ PPCTargetLowering::LowerFormalArguments_SVR4( for (; FPRIndex != NumFPArgRegs; ++FPRIndex) { unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::f64); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); // Increment the address by eight for the next argument to store - SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, + SDValue PtrOff = DAG.getConstant(EVT(EVT::f64).getSizeInBits()/8, PtrVT); FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff); } @@ -1717,7 +1717,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4( if (!MemOps.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, - MVT::Other, &MemOps[0], MemOps.size()); + EVT::Other, &MemOps[0], MemOps.size()); return Chain; } @@ -1736,8 +1736,8 @@ PPCTargetLowering::LowerFormalArguments_Darwin( MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - bool isPPC64 = PtrVT == MVT::i64; + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = PtrVT == EVT::i64; // Potential tail calls could cause overwriting of argument stack slots. bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast)); unsigned PtrByteSize = isPPC64 ? 8 : 4; @@ -1781,7 +1781,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin( if (!isVarArg && !isPPC64) { for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { - MVT ObjectVT = Ins[ArgNo].VT; + EVT ObjectVT = Ins[ArgNo].VT; unsigned ObjSize = ObjectVT.getSizeInBits()/8; ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; @@ -1796,18 +1796,18 @@ PPCTargetLowering::LowerFormalArguments_Darwin( switch(ObjectVT.getSimpleVT()) { default: llvm_unreachable("Unhandled argument type!"); - case MVT::i32: - case MVT::f32: + case EVT::i32: + case EVT::f32: VecArgOffset += isPPC64 ? 8 : 4; break; - case MVT::i64: // PPC64 - case MVT::f64: + case EVT::i64: // PPC64 + case EVT::f64: VecArgOffset += 8; break; - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v4f32: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: // Nothing to do, we're only looking at Nonvector args here. break; } @@ -1827,7 +1827,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin( for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) { SDValue ArgVal; bool needsLoad = false; - MVT ObjectVT = Ins[ArgNo].VT; + EVT ObjectVT = Ins[ArgNo].VT; unsigned ObjSize = ObjectVT.getSizeInBits()/8; unsigned ArgSize = ObjSize; ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags; @@ -1835,8 +1835,8 @@ PPCTargetLowering::LowerFormalArguments_Darwin( unsigned CurArgOffset = ArgOffset; // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary. - if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 || - ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) { + if (ObjectVT==EVT::v4f32 || ObjectVT==EVT::v4i32 || + ObjectVT==EVT::v8i16 || ObjectVT==EVT::v16i8) { if (isVarArg || isPPC64) { MinReservedArea = ((MinReservedArea+15)/16)*16; MinReservedArea += CalculateStackSlotSize(ObjectVT, @@ -1869,7 +1869,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin( unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT); SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, - NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); + NULL, 0, ObjSize==1 ? EVT::i8 : EVT::i16 ); MemOps.push_back(Store); ++GPR_idx; } @@ -1901,11 +1901,11 @@ PPCTargetLowering::LowerFormalArguments_Darwin( switch (ObjectVT.getSimpleVT()) { default: llvm_unreachable("Unhandled argument type!"); - case MVT::i32: + case EVT::i32: if (!isPPC64) { if (GPR_idx != Num_GPR_Regs) { unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); - ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); + ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32); ++GPR_idx; } else { needsLoad = true; @@ -1916,22 +1916,22 @@ PPCTargetLowering::LowerFormalArguments_Darwin( break; } // FALLTHROUGH - case MVT::i64: // PPC64 + case EVT::i64: // PPC64 if (GPR_idx != Num_GPR_Regs) { unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); - ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); + ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64); - if (ObjectVT == MVT::i32) { + if (ObjectVT == EVT::i32) { // PPC64 passes i8, i16, and i32 values in i64 registers. Promote - // value to MVT::i64 and then truncate to the correct register size. + // value to EVT::i64 and then truncate to the correct register size. if (Flags.isSExt()) - ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertSext, dl, EVT::i64, ArgVal, DAG.getValueType(ObjectVT)); else if (Flags.isZExt()) - ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal, + ArgVal = DAG.getNode(ISD::AssertZext, dl, EVT::i64, ArgVal, DAG.getValueType(ObjectVT)); - ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal); + ArgVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, ArgVal); } ++GPR_idx; @@ -1943,8 +1943,8 @@ PPCTargetLowering::LowerFormalArguments_Darwin( ArgOffset += 8; break; - case MVT::f32: - case MVT::f64: + case EVT::f32: + case EVT::f64: // Every 4 bytes of argument space consumes one of the GPRs available for // argument passing. if (GPR_idx != Num_GPR_Regs) { @@ -1955,7 +1955,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin( if (FPR_idx != Num_FPR_Regs) { unsigned VReg; - if (ObjectVT == MVT::f32) + if (ObjectVT == EVT::f32) VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); else VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); @@ -1969,10 +1969,10 @@ PPCTargetLowering::LowerFormalArguments_Darwin( // All FP arguments reserve stack space in the Darwin ABI. ArgOffset += isPPC64 ? 8 : ObjSize; break; - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v4f32: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: // Note that vector arguments in registers don't reserve stack space, // except in varargs functions. if (VR_idx != Num_VR_Regs) { @@ -2067,7 +2067,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin( if (!MemOps.empty()) Chain = DAG.getNode(ISD::TokenFactor, dl, - MVT::Other, &MemOps[0], MemOps.size()); + EVT::Other, &MemOps[0], MemOps.size()); return Chain; } @@ -2099,10 +2099,10 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG, for (unsigned i = 0; i != NumOps; ++i) { SDValue Arg = Outs[i].Val; ISD::ArgFlagsTy Flags = Outs[i].Flags; - MVT ArgVT = Arg.getValueType(); + EVT ArgVT = Arg.getValueType(); // Varargs Altivec parameters are padded to a 16 byte boundary. - if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 || - ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) { + if (ArgVT==EVT::v4f32 || ArgVT==EVT::v4i32 || + ArgVT==EVT::v8i16 || ArgVT==EVT::v16i8) { if (!isVarArg && !isPPC64) { // Non-varargs Altivec parameters go after all the non-Altivec // parameters; handle those later so we know how much padding we need. @@ -2256,7 +2256,7 @@ static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG, isDarwinABI); int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewRetAddrLoc); - MVT VT = isPPC64 ? MVT::i64 : MVT::i32; + EVT VT = isPPC64 ? EVT::i64 : EVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT); Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewRetAddr), 0); @@ -2284,7 +2284,7 @@ CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64, int Offset = ArgOffset + SPDiff; uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset); - MVT VT = isPPC64 ? MVT::i64 : MVT::i32; + EVT VT = isPPC64 ? EVT::i64 : EVT::i32; SDValue FIN = DAG.getFrameIndex(FI, VT); TailCallArgumentInfo Info; Info.Arg = Arg; @@ -2305,7 +2305,7 @@ SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG, DebugLoc dl) { if (SPDiff) { // Load the LR and FP stack slot for later adjusting. - MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32; + EVT VT = PPCSubTarget.isPPC64() ? EVT::i64 : EVT::i32; LROpOut = getReturnAddrFrameIndex(DAG); LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0); Chain = SDValue(LROpOut.getNode(), 1); @@ -2331,7 +2331,7 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, DebugLoc dl) { - SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), false, NULL, 0, NULL, 0); } @@ -2345,14 +2345,14 @@ LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain, bool isVector, SmallVector<SDValue, 8> &MemOpChains, SmallVector<TailCallArgumentInfo, 8>& TailCallArguments, DebugLoc dl) { - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); if (!isTailCall) { if (isVector) { SDValue StackPtr; if (isPPC64) - StackPtr = DAG.getRegister(PPC::X1, MVT::i64); + StackPtr = DAG.getRegister(PPC::X1, EVT::i64); else - StackPtr = DAG.getRegister(PPC::R1, MVT::i32); + StackPtr = DAG.getRegister(PPC::R1, EVT::i32); PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, DAG.getConstant(ArgOffset, PtrVT)); } @@ -2377,7 +2377,7 @@ void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain, StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments, MemOpChains2, dl); if (!MemOpChains2.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains2[0], MemOpChains2.size()); // Store the return address to the appropriate stack slot. @@ -2394,11 +2394,11 @@ static unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall, SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, - SmallVector<SDValue, 8> &Ops, std::vector<MVT> &NodeTys, + SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys, bool isSVR4ABI) { - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + NodeTys.push_back(EVT::Other); // Returns a chain + NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use. unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin; @@ -2421,8 +2421,8 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, InFlag = Chain.getValue(1); NodeTys.clear(); - NodeTys.push_back(MVT::Other); - NodeTys.push_back(MVT::Flag); + NodeTys.push_back(EVT::Other); + NodeTys.push_back(EVT::Flag); Ops.push_back(Chain); CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin; Callee.setNode(0); @@ -2438,7 +2438,7 @@ unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag, } // If this is a tail call add stack pointer delta. if (isTailCall) - Ops.push_back(DAG.getConstant(SPDiff, MVT::i32)); + Ops.push_back(DAG.getConstant(SPDiff, EVT::i32)); // Add argument registers to the end of the list so that they are known live // into the call. @@ -2464,7 +2464,7 @@ PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, // Copy all of the result registers out of their specified physreg. for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { CCValAssign &VA = RVLocs[i]; - MVT VT = VA.getValVT(); + EVT VT = VA.getValVT(); assert(VA.isRegLoc() && "Can only return in registers!"); Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VT, InFlag).getValue(1); @@ -2487,7 +2487,7 @@ PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall, const SmallVectorImpl<ISD::InputArg> &Ins, SmallVectorImpl<SDValue> &InVals) { - std::vector<MVT> NodeTys; + std::vector<EVT> NodeTys; SmallVector<SDValue, 8> Ops; unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff, isTailCall, RegsToPass, Ops, NodeTys, @@ -2522,7 +2522,7 @@ PPCTargetLowering::FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall, isa<ConstantSDNode>(Callee)) && "Expecting an global address, external symbol, absolute value or register"); - return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size()); + return DAG.getNode(PPCISD::TC_RETURN, dl, EVT::Other, &Ops[0], Ops.size()); } Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size()); @@ -2575,7 +2575,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, assert((CallConv == CallingConv::C || CallConv == CallingConv::Fast) && "Unknown calling convention!"); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); unsigned PtrByteSize = 4; MachineFunction &MF = DAG.getMachineFunction(); @@ -2607,7 +2607,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, unsigned NumArgs = Outs.size(); for (unsigned i = 0; i != NumArgs; ++i) { - MVT ArgVT = Outs[i].Val.getValueType(); + EVT ArgVT = Outs[i].Val.getValueType(); ISD::ArgFlagsTy ArgFlags = Outs[i].Flags; bool Result; @@ -2622,7 +2622,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, if (Result) { #ifndef NDEBUG cerr << "Call operand #" << i << " has unhandled type " - << ArgVT.getMVTString() << "\n"; + << ArgVT.getEVTString() << "\n"; #endif llvm_unreachable(0); } @@ -2665,7 +2665,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, // Set up a copy of the stack pointer for use loading and storing any // arguments that may not fit in the registers available for argument // passing. - SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32); + SDValue StackPtr = DAG.getRegister(PPC::R1, EVT::i32); SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; SmallVector<TailCallArgumentInfo, 8> TailCallArguments; @@ -2737,7 +2737,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain @@ -2751,7 +2751,7 @@ PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee, // Set CR6 to true if this is a vararg call. if (isVarArg) { - SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0); + SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, EVT::i32), 0); Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag); InFlag = Chain.getValue(1); } @@ -2777,8 +2777,8 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, unsigned NumOps = Outs.size(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - bool isPPC64 = PtrVT == MVT::i64; + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = PtrVT == EVT::i64; unsigned PtrByteSize = isPPC64 ? 8 : 4; MachineFunction &MF = DAG.getMachineFunction(); @@ -2826,9 +2826,9 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, // passing. SDValue StackPtr; if (isPPC64) - StackPtr = DAG.getRegister(PPC::X1, MVT::i64); + StackPtr = DAG.getRegister(PPC::X1, EVT::i64); else - StackPtr = DAG.getRegister(PPC::R1, MVT::i32); + StackPtr = DAG.getRegister(PPC::R1, EVT::i32); // Figure out which arguments are going to go in registers, and which in // memory. Also, if this is a vararg function, floating point operations @@ -2875,10 +2875,10 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff); // On PPC64, promote integers to 64-bit values. - if (isPPC64 && Arg.getValueType() == MVT::i32) { + if (isPPC64 && Arg.getValueType() == EVT::i32) { // FIXME: Should this use ANY_EXTEND if neither sext nor zext? unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; - Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg); + Arg = DAG.getNode(ExtOp, dl, EVT::i64, Arg); } // FIXME memcpy is used way more than necessary. Correctness first. @@ -2887,7 +2887,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, if (Size==1 || Size==2) { // Very small objects are passed right-justified. // Everything else is passed left-justified. - MVT VT = (Size==1) ? MVT::i8 : MVT::i16; + EVT VT = (Size==1) ? EVT::i8 : EVT::i16; if (GPR_idx != NumGPRs) { SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg, NULL, 0, VT); @@ -2941,8 +2941,8 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, switch (Arg.getValueType().getSimpleVT()) { default: llvm_unreachable("Unexpected ValueType for argument!"); - case MVT::i32: - case MVT::i64: + case EVT::i32: + case EVT::i64: if (GPR_idx != NumGPRs) { RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg)); } else { @@ -2953,8 +2953,8 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, } ArgOffset += PtrByteSize; break; - case MVT::f32: - case MVT::f64: + case EVT::f32: + case EVT::f64: if (FPR_idx != NumFPRs) { RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg)); @@ -2968,7 +2968,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load)); } - if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){ + if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 && !isPPC64){ SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType()); PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour); SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0); @@ -2981,7 +2981,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, // GPRs. if (GPR_idx != NumGPRs) ++GPR_idx; - if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && + if (GPR_idx != NumGPRs && Arg.getValueType() == EVT::f64 && !isPPC64) // PPC64 has 64-bit GPR's obviously :) ++GPR_idx; } @@ -2994,12 +2994,12 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, if (isPPC64) ArgOffset += 8; else - ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8; + ArgOffset += Arg.getValueType() == EVT::f32 ? 4 : 8; break; - case MVT::v4f32: - case MVT::v4i32: - case MVT::v8i16: - case MVT::v16i8: + case EVT::v4f32: + case EVT::v4i32: + case EVT::v8i16: + case EVT::v16i8: if (isVarArg) { // These go aligned on the stack, or in the corresponding R registers // when within range. The Darwin PPC ABI doc claims they also go in @@ -3018,7 +3018,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0); MemOpChains.push_back(Store); if (VR_idx != NumVRs) { - SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0); + SDValue Load = DAG.getLoad(EVT::v4f32, dl, Store, PtrOff, NULL, 0); MemOpChains.push_back(Load.getValue(1)); RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load)); } @@ -3062,9 +3062,9 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, ArgOffset += 12*16; for (unsigned i = 0; i != NumOps; ++i) { SDValue Arg = Outs[i].Val; - MVT ArgType = Arg.getValueType(); - if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 || - ArgType==MVT::v8i16 || ArgType==MVT::v16i8) { + EVT ArgType = Arg.getValueType(); + if (ArgType==EVT::v4f32 || ArgType==EVT::v4i32 || + ArgType==EVT::v8i16 || ArgType==EVT::v16i8) { if (++j > NumVRs) { SDValue PtrOff; // We are emitting Altivec params in order. @@ -3078,7 +3078,7 @@ PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee, } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain @@ -3130,9 +3130,9 @@ PPCTargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) - return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain, Flag); else - return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(PPCISD::RET_FLAG, dl, EVT::Other, Chain); } SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, @@ -3141,7 +3141,7 @@ SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG, DebugLoc dl = Op.getDebugLoc(); // Get the corect type for pointers. - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Construct the stack pointer operand. bool IsPPC64 = Subtarget.isPPC64(); @@ -3169,7 +3169,7 @@ PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); bool isDarwinABI = PPCSubTarget.isDarwinABI(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Get current frame pointer save index. The users of this index will be // primarily DYNALLOC instructions. @@ -3193,7 +3193,7 @@ PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const { MachineFunction &MF = DAG.getMachineFunction(); bool IsPPC64 = PPCSubTarget.isPPC64(); bool isDarwinABI = PPCSubTarget.isDarwinABI(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Get current frame pointer save index. The users of this index will be // primarily DYNALLOC instructions. @@ -3223,7 +3223,7 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, DebugLoc dl = Op.getDebugLoc(); // Get the corect type for pointers. - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); // Negate the size. SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT, DAG.getConstant(0, PtrVT), Size); @@ -3231,7 +3231,7 @@ SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue FPSIdx = getFramePointerFrameIndex(DAG); // Build a DYNALLOC node. SDValue Ops[3] = { Chain, NegSize, FPSIdx }; - SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other); + SDVTList VTs = DAG.getVTList(PtrVT, EVT::Other); return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3); } @@ -3248,8 +3248,8 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { // Cannot handle SETEQ/SETNE. if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; - MVT ResVT = Op.getValueType(); - MVT CmpVT = Op.getOperand(0).getValueType(); + EVT ResVT = Op.getValueType(); + EVT CmpVT = Op.getOperand(0).getValueType(); SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); SDValue TV = Op.getOperand(2), FV = Op.getOperand(3); DebugLoc dl = Op.getDebugLoc(); @@ -3264,18 +3264,18 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETOGE: case ISD::SETGE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits + LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV); case ISD::SETUGT: case ISD::SETGT: std::swap(TV, FV); // fsel is natively setge, swap operands for setlt case ISD::SETOLE: case ISD::SETLE: - if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits - LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS); + if (LHS.getValueType() == EVT::f32) // Comparison is always 64-bits + LHS = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, LHS); return DAG.getNode(PPCISD::FSEL, dl, ResVT, - DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV); + DAG.getNode(ISD::FNEG, dl, EVT::f64, LHS), TV, FV); } SDValue Cmp; @@ -3284,26 +3284,26 @@ SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { case ISD::SETULT: case ISD::SETLT: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOGE: case ISD::SETGE: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); case ISD::SETUGT: case ISD::SETGT: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV); case ISD::SETOLE: case ISD::SETLE: Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS); - if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits - Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp); + if (Cmp.getValueType() == EVT::f32) // Comparison is always 64-bits + Cmp = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Cmp); return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV); } return Op; @@ -3314,31 +3314,31 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) { assert(Op.getOperand(0).getValueType().isFloatingPoint()); SDValue Src = Op.getOperand(0); - if (Src.getValueType() == MVT::f32) - Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src); + if (Src.getValueType() == EVT::f32) + Src = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Src); SDValue Tmp; switch (Op.getValueType().getSimpleVT()) { default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!"); - case MVT::i32: + case EVT::i32: Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ : PPCISD::FCTIDZ, - dl, MVT::f64, Src); + dl, EVT::f64, Src); break; - case MVT::i64: - Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src); + case EVT::i64: + Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Src); break; } // Convert the FP value to an int value through memory. - SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64); + SDValue FIPtr = DAG.CreateStackTemporary(EVT::f64); // Emit a store to the stack slot. SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0); // Result is a load from the stack slot. If loading 4 bytes, make sure to // add in a bias. - if (Op.getValueType() == MVT::i32) + if (Op.getValueType() == EVT::i32) FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, DAG.getConstant(4, FIPtr.getValueType())); return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0); @@ -3347,20 +3347,20 @@ SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); // Don't handle ppc_fp128 here; let it be lowered to a libcall. - if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64) + if (Op.getValueType() != EVT::f32 && Op.getValueType() != EVT::f64) return SDValue(); - if (Op.getOperand(0).getValueType() == MVT::i64) { + if (Op.getOperand(0).getValueType() == EVT::i64) { SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::f64, Op.getOperand(0)); - SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits); - if (Op.getValueType() == MVT::f32) + EVT::f64, Op.getOperand(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Bits); + if (Op.getValueType() == EVT::f32) FP = DAG.getNode(ISD::FP_ROUND, dl, - MVT::f32, FP, DAG.getIntPtrConstant(0)); + EVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } - assert(Op.getOperand(0).getValueType() == MVT::i32 && + assert(Op.getOperand(0).getValueType() == EVT::i32 && "Unhandled SINT_TO_FP type in custom expander!"); // Since we only generate this in 64-bit mode, we can take advantage of // 64-bit registers. In particular, sign extend the input value into the @@ -3368,25 +3368,25 @@ SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { // then lfd it and fcfid it. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(8, 8); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); - SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32, + SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, EVT::i32, Op.getOperand(0)); // STD the extended value into the stack slot. MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx), MachineMemOperand::MOStore, 0, 8, 8); - SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other, + SDValue Store = DAG.getNode(PPCISD::STD_32, dl, EVT::Other, DAG.getEntryNode(), Ext64, FIdx, DAG.getMemOperand(MO)); // Load the value as a double. - SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0); + SDValue Ld = DAG.getLoad(EVT::f64, dl, Store, FIdx, NULL, 0); // FCFID it and return it. - SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld); - if (Op.getValueType() == MVT::f32) - FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0)); + SDValue FP = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Ld); + if (Op.getValueType() == EVT::f32) + FP = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, FP, DAG.getIntPtrConstant(0)); return FP; } @@ -3412,14 +3412,14 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { */ MachineFunction &MF = DAG.getMachineFunction(); - MVT VT = Op.getValueType(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - std::vector<MVT> NodeTys; + EVT VT = Op.getValueType(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + std::vector<EVT> NodeTys; SDValue MFFSreg, InFlag; // Save FP Control Word to register - NodeTys.push_back(MVT::f64); // return register - NodeTys.push_back(MVT::Flag); // unused in this context + NodeTys.push_back(EVT::f64); // return register + NodeTys.push_back(EVT::Flag); // unused in this context SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); // Save FP register to stack slot @@ -3431,29 +3431,29 @@ SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { // Load FP Control Word from low 32 bits of stack slot. SDValue Four = DAG.getConstant(4, PtrVT); SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four); - SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0); + SDValue CWD = DAG.getLoad(EVT::i32, dl, Store, Addr, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::AND, dl, MVT::i32, - CWD, DAG.getConstant(3, MVT::i32)); + DAG.getNode(ISD::AND, dl, EVT::i32, + CWD, DAG.getConstant(3, EVT::i32)); SDValue CWD2 = - DAG.getNode(ISD::SRL, dl, MVT::i32, - DAG.getNode(ISD::AND, dl, MVT::i32, - DAG.getNode(ISD::XOR, dl, MVT::i32, - CWD, DAG.getConstant(3, MVT::i32)), - DAG.getConstant(3, MVT::i32)), - DAG.getConstant(1, MVT::i32)); + DAG.getNode(ISD::SRL, dl, EVT::i32, + DAG.getNode(ISD::AND, dl, EVT::i32, + DAG.getNode(ISD::XOR, dl, EVT::i32, + CWD, DAG.getConstant(3, EVT::i32)), + DAG.getConstant(3, EVT::i32)), + DAG.getConstant(1, EVT::i32)); SDValue RetVal = - DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2); + DAG.getNode(ISD::XOR, dl, EVT::i32, CWD1, CWD2); return DAG.getNode((VT.getSizeInBits() < 16 ? ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal); } SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); DebugLoc dl = Op.getDebugLoc(); assert(Op.getNumOperands() == 3 && @@ -3465,7 +3465,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Lo = Op.getOperand(0); SDValue Hi = Op.getOperand(1); SDValue Amt = Op.getOperand(2); - MVT AmtVT = Amt.getValueType(); + EVT AmtVT = Amt.getValueType(); SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3482,7 +3482,7 @@ SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) { } SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && @@ -3494,7 +3494,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Lo = Op.getOperand(0); SDValue Hi = Op.getOperand(1); SDValue Amt = Op.getOperand(2); - MVT AmtVT = Amt.getValueType(); + EVT AmtVT = Amt.getValueType(); SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3512,7 +3512,7 @@ SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned BitWidth = VT.getSizeInBits(); assert(Op.getNumOperands() == 3 && VT == Op.getOperand(1).getValueType() && @@ -3522,7 +3522,7 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { SDValue Lo = Op.getOperand(0); SDValue Hi = Op.getOperand(1); SDValue Amt = Op.getOperand(2); - MVT AmtVT = Amt.getValueType(); + EVT AmtVT = Amt.getValueType(); SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, DAG.getConstant(BitWidth, AmtVT), Amt); @@ -3545,24 +3545,24 @@ SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) { /// BuildSplatI - Build a canonical splati of Val with an element size of /// SplatSize. Cast the result to VT. -static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, +static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(Val >= -16 && Val <= 15 && "vsplti is out of range!"); - static const MVT VTys[] = { // canonical VT to use for each size. - MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32 + static const EVT VTys[] = { // canonical VT to use for each size. + EVT::v16i8, EVT::v8i16, EVT::Other, EVT::v4i32 }; - MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1]; + EVT ReqVT = VT != EVT::Other ? VT : VTys[SplatSize-1]; // Force vspltis[hw] -1 to vspltisb -1 to canonicalize. if (Val == -1) SplatSize = 1; - MVT CanonicalVT = VTys[SplatSize-1]; + EVT CanonicalVT = VTys[SplatSize-1]; // Build a canonical splat for this value. - SDValue Elt = DAG.getConstant(Val, MVT::i32); + SDValue Elt = DAG.getConstant(Val, EVT::i32); SmallVector<SDValue, 8> Ops; Ops.assign(CanonicalVT.getVectorNumElements(), Elt); SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, @@ -3574,35 +3574,35 @@ static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT, /// specified intrinsic ID. static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS, SelectionDAG &DAG, DebugLoc dl, - MVT DestVT = MVT::Other) { - if (DestVT == MVT::Other) DestVT = LHS.getValueType(); + EVT DestVT = EVT::Other) { + if (DestVT == EVT::Other) DestVT = LHS.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, - DAG.getConstant(IID, MVT::i32), LHS, RHS); + DAG.getConstant(IID, EVT::i32), LHS, RHS); } /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the /// specified intrinsic ID. static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1, SDValue Op2, SelectionDAG &DAG, - DebugLoc dl, MVT DestVT = MVT::Other) { - if (DestVT == MVT::Other) DestVT = Op0.getValueType(); + DebugLoc dl, EVT DestVT = EVT::Other) { + if (DestVT == EVT::Other) DestVT = Op0.getValueType(); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, - DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2); + DAG.getConstant(IID, EVT::i32), Op0, Op1, Op2); } /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified /// amount. The result has the specified value type. static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt, - MVT VT, SelectionDAG &DAG, DebugLoc dl) { + EVT VT, SelectionDAG &DAG, DebugLoc dl) { // Force LHS/RHS to be the right type. - LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS); - RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS); + LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, LHS); + RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, RHS); int Ops[16]; for (unsigned i = 0; i != 16; ++i) Ops[i] = i + Amt; - SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops); + SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, LHS, RHS, Ops); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); } @@ -3633,9 +3633,9 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // All zeros? if (SplatBits == 0) { // Canonicalize all zero vectors to be v4i32. - if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) { - SDValue Z = DAG.getConstant(0, MVT::i32); - Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z); + if (Op.getValueType() != EVT::v4i32 || HasAnyUndefs) { + SDValue Z = DAG.getConstant(0, EVT::i32); + Z = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Z, Z, Z, Z); Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z); } return Op; @@ -3653,7 +3653,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // If this value is in the range [-32,30] and is even, use: // tmp = VSPLTI[bhw], result = add tmp, tmp if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) { - SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl); + SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, EVT::Other, DAG, dl); Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } @@ -3663,14 +3663,14 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // for fneg/fabs. if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) { // Make -1 and vspltisw -1: - SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl); + SDValue OnesV = BuildSplatI(-1, 4, EVT::v4i32, DAG, dl); // Make the VSLW intrinsic, computing 0x8000_0000. SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV, OnesV, DAG, dl); // xor by OnesV to invert it. - Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV); + Res = DAG.getNode(ISD::XOR, dl, EVT::v4i32, Res, OnesV); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res); } @@ -3691,7 +3691,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // vsplti + shl self. if (SextVal == (i << (int)TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); + SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0, Intrinsic::ppc_altivec_vslw @@ -3702,7 +3702,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // vsplti + srl self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); + SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0, Intrinsic::ppc_altivec_vsrw @@ -3713,7 +3713,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // vsplti + sra self. if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); + SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0, Intrinsic::ppc_altivec_vsraw @@ -3725,7 +3725,7 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // vsplti + rol self. if (SextVal == (int)(((unsigned)i << TypeShiftAmt) | ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) { - SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl); + SDValue Res = BuildSplatI(i, SplatSize, EVT::Other, DAG, dl); static const unsigned IIDs[] = { // Intrinsic to use for each size. Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0, Intrinsic::ppc_altivec_vrlw @@ -3736,17 +3736,17 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // t = vsplti c, result = vsldoi t, t, 1 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 2 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl); } // t = vsplti c, result = vsldoi t, t, 3 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) { - SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl); + SDValue T = BuildSplatI(i, SplatSize, EVT::v16i8, DAG, dl); return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl); } } @@ -3755,15 +3755,15 @@ SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // Odd, in range [17,31]: (vsplti C)-(vsplti -16). if (SextVal >= 0 && SextVal <= 31) { - SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl); - SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); + SDValue LHS = BuildSplatI(SextVal-16, SplatSize, EVT::Other, DAG, dl); + SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl); LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); } // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16). if (SextVal >= -31 && SextVal <= 0) { - SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl); - SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl); + SDValue LHS = BuildSplatI(SextVal+16, SplatSize, EVT::Other, DAG, dl); + SDValue RHS = BuildSplatI(-16, SplatSize, EVT::Other, DAG, dl); LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS); } @@ -3841,10 +3841,10 @@ static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS, case OP_VSLDOI12: return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl); } - MVT VT = OpLHS.getValueType(); - OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS); - OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS); - SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); + EVT VT = OpLHS.getValueType(); + OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpLHS); + OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OpRHS); + SDValue T = DAG.getVectorShuffle(EVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T); } @@ -3858,7 +3858,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); // Cases that are handled by instructions that take permute immediates // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be @@ -3955,7 +3955,7 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except // that it is in input element units, not in bytes. Convert now. - MVT EltVT = V1.getValueType().getVectorElementType(); + EVT EltVT = V1.getValueType().getVectorElementType(); unsigned BytesPerElement = EltVT.getSizeInBits()/8; SmallVector<SDValue, 16> ResultMask; @@ -3964,10 +3964,10 @@ SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, for (unsigned j = 0; j != BytesPerElement; ++j) ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j, - MVT::i32)); + EVT::i32)); } - SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8, + SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v16i8, &ResultMask[0], ResultMask.size()); return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask); } @@ -4032,7 +4032,7 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, if (!isDot) { SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(), Op.getOperand(1), Op.getOperand(2), - DAG.getConstant(CompareOpc, MVT::i32)); + DAG.getConstant(CompareOpc, EVT::i32)); return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp); } @@ -4040,17 +4040,17 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue Ops[] = { Op.getOperand(2), // LHS Op.getOperand(3), // RHS - DAG.getConstant(CompareOpc, MVT::i32) + DAG.getConstant(CompareOpc, EVT::i32) }; - std::vector<MVT> VTs; + std::vector<EVT> VTs; VTs.push_back(Op.getOperand(2).getValueType()); - VTs.push_back(MVT::Flag); + VTs.push_back(EVT::Flag); SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Now that we have the comparison, emit a copy from the CR to a GPR. // This is flagged to the above dot comparison. - SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32, - DAG.getRegister(PPC::CR6, MVT::i32), + SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, EVT::i32, + DAG.getRegister(PPC::CR6, EVT::i32), CompNode.getValue(1)); // Unpack the result based on how the target uses it. @@ -4073,16 +4073,16 @@ SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, } // Shift the bit into the low position. - Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags, - DAG.getConstant(8-(3-BitNo), MVT::i32)); + Flags = DAG.getNode(ISD::SRL, dl, EVT::i32, Flags, + DAG.getConstant(8-(3-BitNo), EVT::i32)); // Isolate the bit. - Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags, - DAG.getConstant(1, MVT::i32)); + Flags = DAG.getNode(ISD::AND, dl, EVT::i32, Flags, + DAG.getConstant(1, EVT::i32)); // If we are supposed to, toggle the bit. if (InvertBit) - Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags, - DAG.getConstant(1, MVT::i32)); + Flags = DAG.getNode(ISD::XOR, dl, EVT::i32, Flags, + DAG.getConstant(1, EVT::i32)); return Flags; } @@ -4092,7 +4092,7 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, // Create a stack slot that is 16-byte aligned. MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo(); int FrameIdx = FrameInfo->CreateStackObject(16, 16); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT); // Store the input value into Value#0 of the stack slot. @@ -4104,50 +4104,50 @@ SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); - if (Op.getValueType() == MVT::v4i32) { + if (Op.getValueType() == EVT::v4i32) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl); - SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt. + SDValue Zero = BuildSplatI( 0, 1, EVT::v4i32, DAG, dl); + SDValue Neg16 = BuildSplatI(-16, 4, EVT::v4i32, DAG, dl);//+16 as shift amt. SDValue RHSSwap = // = vrlw RHS, 16 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl); // Shrinkify inputs to v8i16. - LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS); - RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS); - RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap); + LHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, LHS); + RHS = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHS); + RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, RHSSwap); // Low parts multiplied together, generating 32-bit results (we ignore the // top parts). SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh, - LHS, RHS, DAG, dl, MVT::v4i32); + LHS, RHS, DAG, dl, EVT::v4i32); SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm, - LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32); + LHS, RHSSwap, Zero, DAG, dl, EVT::v4i32); // Shift the high parts up 16 bits. HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG, dl); - return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd); - } else if (Op.getValueType() == MVT::v8i16) { + return DAG.getNode(ISD::ADD, dl, EVT::v4i32, LoProd, HiProd); + } else if (Op.getValueType() == EVT::v8i16) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); - SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl); + SDValue Zero = BuildSplatI(0, 1, EVT::v8i16, DAG, dl); return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm, LHS, RHS, Zero, DAG, dl); - } else if (Op.getValueType() == MVT::v16i8) { + } else if (Op.getValueType() == EVT::v16i8) { SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1); // Multiply the even 8-bit parts, producing 16-bit sums. SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub, - LHS, RHS, DAG, dl, MVT::v8i16); - EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts); + LHS, RHS, DAG, dl, EVT::v8i16); + EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, EvenParts); // Multiply the odd 8-bit parts, producing 16-bit sums. SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub, - LHS, RHS, DAG, dl, MVT::v8i16); - OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts); + LHS, RHS, DAG, dl, EVT::v8i16); + OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, OddParts); // Merge the results together. int Ops[16]; @@ -4155,7 +4155,7 @@ SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) { Ops[i*2 ] = 2*i+1; Ops[i*2+1] = 2*i+1+16; } - return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops); + return DAG.getVectorShuffle(EVT::v16i8, dl, EvenParts, OddParts, Ops); } else { llvm_unreachable("Unknown mul to lower!"); } @@ -4219,44 +4219,44 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, assert(false && "Do not know how to custom type legalize this operation!"); return; case ISD::FP_ROUND_INREG: { - assert(N->getValueType(0) == MVT::ppcf128); - assert(N->getOperand(0).getValueType() == MVT::ppcf128); + assert(N->getValueType(0) == EVT::ppcf128); + assert(N->getOperand(0).getValueType() == EVT::ppcf128); SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, - MVT::f64, N->getOperand(0), + EVT::f64, N->getOperand(0), DAG.getIntPtrConstant(0)); SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, - MVT::f64, N->getOperand(0), + EVT::f64, N->getOperand(0), DAG.getIntPtrConstant(1)); // This sequence changes FPSCR to do round-to-zero, adds the two halves // of the long double, and puts FPSCR back the way it was. We do not // actually model FPSCR. - std::vector<MVT> NodeTys; + std::vector<EVT> NodeTys; SDValue Ops[4], Result, MFFSreg, InFlag, FPreg; - NodeTys.push_back(MVT::f64); // Return register - NodeTys.push_back(MVT::Flag); // Returns a flag for later insns + NodeTys.push_back(EVT::f64); // Return register + NodeTys.push_back(EVT::Flag); // Returns a flag for later insns Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0); MFFSreg = Result.getValue(0); InFlag = Result.getValue(1); NodeTys.clear(); - NodeTys.push_back(MVT::Flag); // Returns a flag - Ops[0] = DAG.getConstant(31, MVT::i32); + NodeTys.push_back(EVT::Flag); // Returns a flag + Ops[0] = DAG.getConstant(31, EVT::i32); Ops[1] = InFlag; Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); - NodeTys.push_back(MVT::Flag); // Returns a flag - Ops[0] = DAG.getConstant(30, MVT::i32); + NodeTys.push_back(EVT::Flag); // Returns a flag + Ops[0] = DAG.getConstant(30, EVT::i32); Ops[1] = InFlag; Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2); InFlag = Result.getValue(0); NodeTys.clear(); - NodeTys.push_back(MVT::f64); // result of add - NodeTys.push_back(MVT::Flag); // Returns a flag + NodeTys.push_back(EVT::f64); // result of add + NodeTys.push_back(EVT::Flag); // Returns a flag Ops[0] = Lo; Ops[1] = Hi; Ops[2] = InFlag; @@ -4265,8 +4265,8 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, InFlag = Result.getValue(1); NodeTys.clear(); - NodeTys.push_back(MVT::f64); - Ops[0] = DAG.getConstant(1, MVT::i32); + NodeTys.push_back(EVT::f64); + Ops[0] = DAG.getConstant(1, EVT::i32); Ops[1] = MFFSreg; Ops[2] = FPreg; Ops[3] = InFlag; @@ -4275,7 +4275,7 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, // We know the low half is about to be thrown away, so just use something // convenient. - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::ppcf128, FPreg, FPreg)); return; } @@ -4853,25 +4853,25 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores. // We allow the src/dst to be either f32/f64, but the intermediate // type must be i64. - if (N->getOperand(0).getValueType() == MVT::i64 && - N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) { + if (N->getOperand(0).getValueType() == EVT::i64 && + N->getOperand(0).getOperand(0).getValueType() != EVT::ppcf128) { SDValue Val = N->getOperand(0).getOperand(0); - if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); + if (Val.getValueType() == EVT::f32) { + Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIDZ, dl, EVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCFID, dl, EVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - if (N->getValueType(0) == MVT::f32) { - Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val, + if (N->getValueType(0) == EVT::f32) { + Val = DAG.getNode(ISD::FP_ROUND, dl, EVT::f32, Val, DAG.getIntPtrConstant(0)); DCI.AddToWorklist(Val.getNode()); } return Val; - } else if (N->getOperand(0).getValueType() == MVT::i32) { + } else if (N->getOperand(0).getValueType() == EVT::i32) { // If the intermediate type is i32, we can avoid the load/store here // too. } @@ -4883,17 +4883,17 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() && N->getOperand(1).getOpcode() == ISD::FP_TO_SINT && - N->getOperand(1).getValueType() == MVT::i32 && - N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) { + N->getOperand(1).getValueType() == EVT::i32 && + N->getOperand(1).getOperand(0).getValueType() != EVT::ppcf128) { SDValue Val = N->getOperand(1).getOperand(0); - if (Val.getValueType() == MVT::f32) { - Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val); + if (Val.getValueType() == EVT::f32) { + Val = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f64, Val); DCI.AddToWorklist(Val.getNode()); } - Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val); + Val = DAG.getNode(PPCISD::FCTIWZ, dl, EVT::f64, Val); DCI.AddToWorklist(Val.getNode()); - Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val, + Val = DAG.getNode(PPCISD::STFIWX, dl, EVT::Other, N->getOperand(0), Val, N->getOperand(2), N->getOperand(3)); DCI.AddToWorklist(Val.getNode()); return Val; @@ -4902,14 +4902,14 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // Turn STORE (BSWAP) -> sthbrx/stwbrx. if (N->getOperand(1).getOpcode() == ISD::BSWAP && N->getOperand(1).getNode()->hasOneUse() && - (N->getOperand(1).getValueType() == MVT::i32 || - N->getOperand(1).getValueType() == MVT::i16)) { + (N->getOperand(1).getValueType() == EVT::i32 || + N->getOperand(1).getValueType() == EVT::i16)) { SDValue BSwapOp = N->getOperand(1).getOperand(0); // Do an any-extend to 32-bits if this is a half-word input. - if (BSwapOp.getValueType() == MVT::i16) - BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp); + if (BSwapOp.getValueType() == EVT::i16) + BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, BSwapOp); - return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0), + return DAG.getNode(PPCISD::STBRX, dl, EVT::Other, N->getOperand(0), BSwapOp, N->getOperand(2), N->getOperand(3), DAG.getValueType(N->getOperand(1).getValueType())); } @@ -4918,13 +4918,13 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // Turn BSWAP (LOAD) -> lhbrx/lwbrx. if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) && N->getOperand(0).hasOneUse() && - (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) { + (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i16)) { SDValue Load = N->getOperand(0); LoadSDNode *LD = cast<LoadSDNode>(Load); // Create the byte-swapping load. - std::vector<MVT> VTs; - VTs.push_back(MVT::i32); - VTs.push_back(MVT::Other); + std::vector<EVT> VTs; + VTs.push_back(EVT::i32); + VTs.push_back(EVT::Other); SDValue MO = DAG.getMemOperand(LD->getMemOperand()); SDValue Ops[] = { LD->getChain(), // Chain @@ -4936,8 +4936,8 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, // If this is an i16 load, insert the truncate. SDValue ResVal = BSLoad; - if (N->getValueType(0) == MVT::i16) - ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad); + if (N->getValueType(0) == EVT::i16) + ResVal = DAG.getNode(ISD::TRUNCATE, dl, EVT::i16, BSLoad); // First, combine the bswap away. This makes the value produced by the // load dead. @@ -5025,21 +5025,21 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, if (CC == ISD::SETEQ) // Cond never true, remove branch. return N->getOperand(0); // Always !=, turn it into an unconditional branch. - return DAG.getNode(ISD::BR, dl, MVT::Other, + return DAG.getNode(ISD::BR, dl, EVT::Other, N->getOperand(0), N->getOperand(4)); } bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0); // Create the PPCISD altivec 'dot' comparison node. - std::vector<MVT> VTs; + std::vector<EVT> VTs; SDValue Ops[] = { LHS.getOperand(2), // LHS of compare LHS.getOperand(3), // RHS of compare - DAG.getConstant(CompareOpc, MVT::i32) + DAG.getConstant(CompareOpc, EVT::i32) }; VTs.push_back(LHS.getOperand(2).getValueType()); - VTs.push_back(MVT::Flag); + VTs.push_back(EVT::Flag); SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3); // Unpack the result based on how the target uses it. @@ -5060,9 +5060,9 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N, break; } - return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0), - DAG.getConstant(CompOpc, MVT::i32), - DAG.getRegister(PPC::CR6, MVT::i32), + return DAG.getNode(PPCISD::COND_BRANCH, dl, EVT::Other, N->getOperand(0), + DAG.getConstant(CompOpc, EVT::i32), + DAG.getRegister(PPC::CR6, EVT::i32), N->getOperand(4), CompNode.getValue(1)); } break; @@ -5087,7 +5087,7 @@ void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, default: break; case PPCISD::LBRX: { // lhbrx is known to have the top bits cleared out. - if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16) + if (cast<VTSDNode>(Op.getOperand(3))->getVT() == EVT::i16) KnownZero = 0xFFFF0000; break; } @@ -5135,19 +5135,19 @@ PPCTargetLowering::getConstraintType(const std::string &Constraint) const { std::pair<unsigned, const TargetRegisterClass*> PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() == 1) { // GCC RS6000 Constraint Letters switch (Constraint[0]) { case 'b': // R1-R31 case 'r': // R0-R31 - if (VT == MVT::i64 && PPCSubTarget.isPPC64()) + if (VT == EVT::i64 && PPCSubTarget.isPPC64()) return std::make_pair(0U, PPC::G8RCRegisterClass); return std::make_pair(0U, PPC::GPRCRegisterClass); case 'f': - if (VT == MVT::f32) + if (VT == EVT::f32) return std::make_pair(0U, PPC::F4RCRegisterClass); - else if (VT == MVT::f64) + else if (VT == EVT::f64) return std::make_pair(0U, PPC::F8RCRegisterClass); break; case 'v': @@ -5301,8 +5301,8 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0) return SDValue(); - MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - bool isPPC64 = PtrVT == MVT::i64; + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + bool isPPC64 = PtrVT == EVT::i64; MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -5311,10 +5311,10 @@ SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { if (isPPC64) return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1, - MVT::i64); + EVT::i64); else return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1, - MVT::i32); + EVT::i32); } bool @@ -5323,12 +5323,12 @@ PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { return false; } -MVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, +EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr, SelectionDAG &DAG) const { if (this->PPCSubTarget.isPPC64()) { - return MVT::i64; + return EVT::i64; } else { - return MVT::i32; + return EVT::i32; } } diff --git a/lib/Target/PowerPC/PPCISelLowering.h b/lib/Target/PowerPC/PPCISelLowering.h index e3f4b69a0e..9d8687bade 100644 --- a/lib/Target/PowerPC/PPCISelLowering.h +++ b/lib/Target/PowerPC/PPCISelLowering.h @@ -230,7 +230,7 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const; /// getPreIndexedAddressParts - returns true by value, base pointer and /// offset pointer and addressing mode by reference if the node's address @@ -295,7 +295,7 @@ namespace llvm { ConstraintType getConstraintType(const std::string &Constraint) const; std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate /// function arguments in the caller parameter area. This is the actual @@ -334,7 +334,7 @@ namespace llvm { virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; - virtual MVT getOptimalMemOpType(uint64_t Size, unsigned Align, + virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr, SelectionDAG &DAG) const; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 759cdf0a48..e0e84667c0 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -191,7 +191,7 @@ def ME : SDNodeXForm<imm, [{ def maskimm32 : PatLeaf<(imm), [{ // maskImm predicate - True if immediate is a run of ones. unsigned mb, me; - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return isRunOfOnes((unsigned)N->getZExtValue(), mb, me); else return false; @@ -200,7 +200,7 @@ def maskimm32 : PatLeaf<(imm), [{ def immSExt16 : PatLeaf<(imm), [{ // immSExt16 predicate - True if the immediate fits in a 16-bit sign extended // field. Used by instructions like 'addi'. - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return (int32_t)N->getZExtValue() == (short)N->getZExtValue(); else return (int64_t)N->getZExtValue() == (short)N->getZExtValue(); @@ -227,7 +227,7 @@ def imm16ShiftedSExt : PatLeaf<(imm), [{ // immediate are set. Used by instructions like 'addis'. Identical to // imm16ShiftedZExt in 32-bit mode. if (N->getZExtValue() & 0xFFFF) return false; - if (N->getValueType(0) == MVT::i32) + if (N->getValueType(0) == EVT::i32) return true; // For 64-bit, make sure it is sext right. return N->getZExtValue() == (uint64_t)(int)N->getZExtValue(); diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index e1b9b59b40..3aefa303aa 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -79,8 +79,8 @@ void SparcDAGToDAGISel::InstructionSelect() { bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Offset) { if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } if (Addr.getOpcode() == ISD::TargetExternalSymbol || @@ -93,11 +93,11 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr, if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { // Constant offset from frame ref. - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); } else { Base = Addr.getOperand(0); } - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), EVT::i32); return true; } } @@ -113,7 +113,7 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr, } } Base = Addr; - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } @@ -137,7 +137,7 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr, } R1 = Addr; - R2 = CurDAG->getRegister(SP::G0, MVT::i32); + R2 = CurDAG->getRegister(SP::G0, EVT::i32); return true; } @@ -158,17 +158,17 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { // Set the Y register to the high-part. SDValue TopPart; if (N->getOpcode() == ISD::SDIV) { - TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS, - CurDAG->getTargetConstant(31, MVT::i32)), 0); + TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, EVT::i32, DivLHS, + CurDAG->getTargetConstant(31, EVT::i32)), 0); } else { - TopPart = CurDAG->getRegister(SP::G0, MVT::i32); + TopPart = CurDAG->getRegister(SP::G0, EVT::i32); } - TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart, - CurDAG->getRegister(SP::G0, MVT::i32)), 0); + TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, EVT::Flag, TopPart, + CurDAG->getRegister(SP::G0, EVT::i32)), 0); // FIXME: Handle div by immediate. unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr; - return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, + return CurDAG->SelectNodeTo(N, Opcode, EVT::i32, DivLHS, DivRHS, TopPart); } case ISD::MULHU: @@ -177,10 +177,10 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) { SDValue MulLHS = N->getOperand(0); SDValue MulRHS = N->getOperand(1); unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr; - SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag, + SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, EVT::i32, EVT::Flag, MulLHS, MulRHS); // The high part is in the Y register. - return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1)); + return CurDAG->SelectNodeTo(N, SP::RDY, EVT::i32, SDValue(Mul, 1)); return NULL; } } diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp index b560b736d1..959d41ab8b 100644 --- a/lib/Target/Sparc/SparcISelLowering.cpp +++ b/lib/Target/Sparc/SparcISelLowering.cpp @@ -72,8 +72,8 @@ SparcTargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) - return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain, Flag); - return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain, Flag); + return DAG.getNode(SPISD::RET_FLAG, dl, EVT::Other, Chain); } /// LowerFormalArguments - V8 uses a very simple ABI, where all values are @@ -107,41 +107,41 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, CCValAssign &VA = ArgLocs[i]; // FIXME: We ignore the register assignments of AnalyzeFormalArguments // because it doesn't know how to split a double into two i32 registers. - MVT ObjectVT = VA.getValVT(); + EVT ObjectVT = VA.getValVT(); switch (ObjectVT.getSimpleVT()) { default: llvm_unreachable("Unhandled argument type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: + case EVT::i1: + case EVT::i8: + case EVT::i16: + case EVT::i32: if (!Ins[i].Used) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; InVals.push_back(DAG.getUNDEF(ObjectVT)); } else if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); - if (ObjectVT != MVT::i32) { + SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32); + if (ObjectVT != EVT::i32) { unsigned AssertOp = ISD::AssertSext; - Arg = DAG.getNode(AssertOp, dl, MVT::i32, Arg, + Arg = DAG.getNode(AssertOp, dl, EVT::i32, Arg, DAG.getValueType(ObjectVT)); Arg = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Arg); } InVals.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32); SDValue Load; - if (ObjectVT == MVT::i32) { - Load = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0); + if (ObjectVT == EVT::i32) { + Load = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0); } else { ISD::LoadExtType LoadOp = ISD::SEXTLOAD; // Sparc is big endian, so add an offset based on the ObjectVT. unsigned Offset = 4-std::max(1U, ObjectVT.getSizeInBits()/8); - FIPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIPtr, - DAG.getConstant(Offset, MVT::i32)); - Load = DAG.getExtLoad(LoadOp, dl, MVT::i32, Chain, FIPtr, + FIPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, FIPtr, + DAG.getConstant(Offset, EVT::i32)); + Load = DAG.getExtLoad(LoadOp, dl, EVT::i32, Chain, FIPtr, NULL, 0, ObjectVT); Load = DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, Load); } @@ -150,7 +150,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, ArgOffset += 4; break; - case MVT::f32: + case EVT::f32: if (!Ins[i].Used) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; InVals.push_back(DAG.getUNDEF(ObjectVT)); @@ -158,21 +158,21 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, // FP value is passed in an integer register. unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VReg); - SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32); - Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Arg); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Arg); InVals.push_back(Arg); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - SDValue Load = DAG.getLoad(MVT::f32, dl, Chain, FIPtr, NULL, 0); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32); + SDValue Load = DAG.getLoad(EVT::f32, dl, Chain, FIPtr, NULL, 0); InVals.push_back(Load); } ArgOffset += 4; break; - case MVT::i64: - case MVT::f64: + case EVT::i64: + case EVT::f64: if (!Ins[i].Used) { // Argument is dead. if (CurArgReg < ArgRegEnd) ++CurArgReg; if (CurArgReg < ArgRegEnd) ++CurArgReg; @@ -182,31 +182,31 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegHi = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegHi); - HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, MVT::i32); + HiVal = DAG.getCopyFromReg(Chain, dl, VRegHi, EVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - HiVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32); + HiVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0); } SDValue LoVal; if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR unsigned VRegLo = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg++, VRegLo); - LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, MVT::i32); + LoVal = DAG.getCopyFromReg(Chain, dl, VRegLo, EVT::i32); } else { int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4); - SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); - LoVal = DAG.getLoad(MVT::i32, dl, Chain, FIPtr, NULL, 0); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32); + LoVal = DAG.getLoad(EVT::i32, dl, Chain, FIPtr, NULL, 0); } // Compose the two halves together into an i64 unit. SDValue WholeValue = - DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); + DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, LoVal, HiVal); // If we want a double, do a bit convert. - if (ObjectVT == MVT::f64) - WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, WholeValue); + if (ObjectVT == EVT::f64) + WholeValue = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, WholeValue); InVals.push_back(WholeValue); } @@ -225,10 +225,10 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, for (; CurArgReg != ArgRegEnd; ++CurArgReg) { unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); MF.getRegInfo().addLiveIn(*CurArgReg, VReg); - SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32); + SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, EVT::i32); int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset); - SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32); + SDValue FIPtr = DAG.getFrameIndex(FrameIdx, EVT::i32); OutChains.push_back(DAG.getStore(DAG.getRoot(), dl, Arg, FIPtr, NULL, 0)); ArgOffset += 4; @@ -236,7 +236,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain, if (!OutChains.empty()) { OutChains.push_back(Chain); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &OutChains[0], OutChains.size()); } } @@ -270,15 +270,15 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, for (unsigned i = 0, e = Outs.size(); i != e; ++i) { switch (Outs[i].Val.getValueType().getSimpleVT()) { default: llvm_unreachable("Unknown value type!"); - case MVT::i1: - case MVT::i8: - case MVT::i16: - case MVT::i32: - case MVT::f32: + case EVT::i1: + case EVT::i8: + case EVT::i16: + case EVT::i32: + case EVT::f32: ArgsSize += 4; break; - case MVT::i64: - case MVT::f64: + case EVT::i64: + case EVT::f64: ArgsSize += 8; break; } @@ -328,10 +328,10 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, assert(VA.isMemLoc()); // Create a store off the stack pointer for this argument. - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); + SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32); // FIXME: VERIFY THAT 68 IS RIGHT. SDValue PtrOff = DAG.getIntPtrConstant(VA.getLocMemOffset()+68); - PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff); + PtrOff = DAG.getNode(ISD::ADD, EVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0)); } @@ -343,12 +343,12 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, for (unsigned i = 0, e = Outs.size(); i != e; ++i) { SDValue Val = Outs[i].Val; - MVT ObjectVT = Val.getValueType(); + EVT ObjectVT = Val.getValueType(); SDValue ValToStore(0, 0); unsigned ObjSize; switch (ObjectVT.getSimpleVT()) { default: llvm_unreachable("Unhandled argument type!"); - case MVT::i32: + case EVT::i32: ObjSize = 4; if (RegsToPass.size() >= 6) { @@ -357,17 +357,17 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; - case MVT::f32: + case EVT::f32: ObjSize = 4; if (RegsToPass.size() >= 6) { ValToStore = Val; } else { // Convert this to a FP value in an int reg. - Val = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Val); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Val)); } break; - case MVT::f64: { + case EVT::f64: { ObjSize = 8; if (RegsToPass.size() >= 6) { ValToStore = Val; // Whole thing is passed in memory. @@ -376,16 +376,16 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Break into top and bottom parts by storing to the stack and loading // out the parts as integers. Top part goes in a reg. - SDValue StackPtr = DAG.CreateStackTemporary(MVT::f64, MVT::i32); + SDValue StackPtr = DAG.CreateStackTemporary(EVT::f64, EVT::i32); SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Val, StackPtr, NULL, 0); // Sparc is big-endian, so the high part comes first. - SDValue Hi = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); + SDValue Hi = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0); // Increment the pointer to the other half. StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, DAG.getIntPtrConstant(4)); // Load the low part. - SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, NULL, 0, 0); + SDValue Lo = DAG.getLoad(EVT::i32, dl, Store, StackPtr, NULL, 0, 0); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); @@ -398,7 +398,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } break; } - case MVT::i64: { + case EVT::i64: { ObjSize = 8; if (RegsToPass.size() >= 6) { ValToStore = Val; // Whole thing is passed in memory. @@ -406,10 +406,10 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } // Split the value into top and bottom part. Top part goes in a reg. - SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, - DAG.getConstant(1, MVT::i32)); - SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Val, - DAG.getConstant(0, MVT::i32)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val, + DAG.getConstant(1, EVT::i32)); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Val, + DAG.getConstant(0, EVT::i32)); RegsToPass.push_back(std::make_pair(ArgRegs[RegsToPass.size()], Hi)); if (RegsToPass.size() >= 6) { @@ -424,9 +424,9 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, } if (ValToStore.getNode()) { - SDValue StackPtr = DAG.getRegister(SP::O6, MVT::i32); - SDValue PtrOff = DAG.getConstant(ArgOffset, MVT::i32); - PtrOff = DAG.getNode(ISD::ADD, dl, MVT::i32, StackPtr, PtrOff); + SDValue StackPtr = DAG.getRegister(SP::O6, EVT::i32); + SDValue PtrOff = DAG.getConstant(ArgOffset, EVT::i32); + PtrOff = DAG.getNode(ISD::ADD, dl, EVT::i32, StackPtr, PtrOff); MemOpChains.push_back(DAG.getStore(Chain, dl, ValToStore, PtrOff, NULL, 0)); } @@ -436,7 +436,7 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Emit all stores, make sure the occur before any copies into physregs. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -458,13 +458,13 @@ SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) - Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32); - std::vector<MVT> NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use. + std::vector<EVT> NodeTys; + NodeTys.push_back(EVT::Other); // Returns a chain + NodeTys.push_back(EVT::Flag); // Returns a flag for retval copy to use. SDValue Ops[] = { Chain, Callee, InFlag }; Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); InFlag = Chain.getValue(1); @@ -553,120 +553,120 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM) : TargetLowering(TM, new TargetLoweringObjectFileELF()) { // Set up the register classes. - addRegisterClass(MVT::i32, SP::IntRegsRegisterClass); - addRegisterClass(MVT::f32, SP::FPRegsRegisterClass); - addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass); + addRegisterClass(EVT::i32, SP::IntRegsRegisterClass); + addRegisterClass(EVT::f32, SP::FPRegsRegisterClass); + addRegisterClass(EVT::f64, SP::DFPRegsRegisterClass); // Turn FP extload into load/fextend - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); // Sparc doesn't have i1 sign extending load - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); // Turn FP truncstore into trunc + store. - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); // Custom legalize GlobalAddress nodes into LO/HI parts. - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool , MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom); + setOperationAction(ISD::ConstantPool , EVT::i32, Custom); // Sparc doesn't have sext_inreg, replace them with shl/sra - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Expand); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand); // Sparc has no REM or DIVREM operations. - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::SDIVREM, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::SDIVREM, EVT::i32, Expand); + setOperationAction(ISD::UDIVREM, EVT::i32, Expand); // Custom expand fp<->sint - setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::i32, Custom); + setOperationAction(ISD::SINT_TO_FP, EVT::i32, Custom); // Expand fp<->uint - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand); // Sparc has no select or setcc: expand to SELECT_CC. - setOperationAction(ISD::SELECT, MVT::i32, Expand); - setOperationAction(ISD::SELECT, MVT::f32, Expand); - setOperationAction(ISD::SELECT, MVT::f64, Expand); - setOperationAction(ISD::SETCC, MVT::i32, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Expand); - setOperationAction(ISD::SETCC, MVT::f64, Expand); + setOperationAction(ISD::SELECT, EVT::i32, Expand); + setOperationAction(ISD::SELECT, EVT::f32, Expand); + setOperationAction(ISD::SELECT, EVT::f64, Expand); + setOperationAction(ISD::SETCC, EVT::i32, Expand); + setOperationAction(ISD::SETCC, EVT::f32, Expand); + setOperationAction(ISD::SETCC, EVT::f64, Expand); // Sparc doesn't have BRCOND either, it has BR_CC. - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BRIND, MVT::Other, Expand); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::i32, Custom); - setOperationAction(ISD::BR_CC, MVT::f32, Custom); - setOperationAction(ISD::BR_CC, MVT::f64, Custom); + setOperationAction(ISD::BRCOND, EVT::Other, Expand); + setOperationAction(ISD::BRIND, EVT::Other, Expand); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::i32, Custom); + setOperationAction(ISD::BR_CC, EVT::f32, Custom); + setOperationAction(ISD::BR_CC, EVT::f64, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f64, Custom); // SPARC has no intrinsics for these particular operations. - setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand); - - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FREM , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); - setOperationAction(ISD::FREM , MVT::f32, Expand); - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTTZ , MVT::i32, Expand); - setOperationAction(ISD::CTLZ , MVT::i32, Expand); - setOperationAction(ISD::ROTL , MVT::i32, Expand); - setOperationAction(ISD::ROTR , MVT::i32, Expand); - setOperationAction(ISD::BSWAP, MVT::i32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); - setOperationAction(ISD::FPOW , MVT::f64, Expand); - setOperationAction(ISD::FPOW , MVT::f32, Expand); - - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::MEMBARRIER, EVT::Other, Expand); + + setOperationAction(ISD::FSIN , EVT::f64, Expand); + setOperationAction(ISD::FCOS , EVT::f64, Expand); + setOperationAction(ISD::FREM , EVT::f64, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); + setOperationAction(ISD::FREM , EVT::f32, Expand); + setOperationAction(ISD::CTPOP, EVT::i32, Expand); + setOperationAction(ISD::CTTZ , EVT::i32, Expand); + setOperationAction(ISD::CTLZ , EVT::i32, Expand); + setOperationAction(ISD::ROTL , EVT::i32, Expand); + setOperationAction(ISD::ROTR , EVT::i32, Expand); + setOperationAction(ISD::BSWAP, EVT::i32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand); + setOperationAction(ISD::FPOW , EVT::f64, Expand); + setOperationAction(ISD::FPOW , EVT::f32, Expand); + + setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand); // FIXME: Sparc provides these multiplies, but we don't have them yet. - setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::UMUL_LOHI, EVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); // We don't have line number support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); // VASTART needs to be custom lowered to use the VarArgsFrameIndex. - setOperationAction(ISD::VASTART , MVT::Other, Custom); + setOperationAction(ISD::VASTART , EVT::Other, Custom); // VAARG needs to be lowered to not do unaligned accesses for doubles. - setOperationAction(ISD::VAARG , MVT::Other, Custom); + setOperationAction(ISD::VAARG , EVT::Other, Custom); // Use the default implementation. - setOperationAction(ISD::VACOPY , MVT::Other, Expand); - setOperationAction(ISD::VAEND , MVT::Other, Expand); - setOperationAction(ISD::STACKSAVE , MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom); + setOperationAction(ISD::VACOPY , EVT::Other, Expand); + setOperationAction(ISD::VAEND , EVT::Other, Expand); + setOperationAction(ISD::STACKSAVE , EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE , EVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32 , Custom); // No debug info support yet. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); - setOperationAction(ISD::DECLARE, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); + setOperationAction(ISD::DECLARE, EVT::Other, Expand); setStackPointerRegisterToSaveRestore(SP::O6); if (TM.getSubtarget<SparcSubtarget>().isV9()) - setOperationAction(ISD::CTPOP, MVT::i32, Legal); + setOperationAction(ISD::CTPOP, EVT::i32, Legal); computeRegisterProperties(); } @@ -745,10 +745,10 @@ static SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); // FIXME there isn't really any debug info here DebugLoc dl = Op.getDebugLoc(); - SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); - SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, GA); - SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, GA); - return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); + SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32); + SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, GA); + SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, GA); + return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi); } static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { @@ -756,24 +756,24 @@ static SDValue LowerCONSTANTPOOL(SDValue Op, SelectionDAG &DAG) { // FIXME there isn't really any debug info here DebugLoc dl = Op.getDebugLoc(); Constant *C = N->getConstVal(); - SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment()); - SDValue Hi = DAG.getNode(SPISD::Hi, dl, MVT::i32, CP); - SDValue Lo = DAG.getNode(SPISD::Lo, dl, MVT::i32, CP); - return DAG.getNode(ISD::ADD, dl, MVT::i32, Lo, Hi); + SDValue CP = DAG.getTargetConstantPool(C, EVT::i32, N->getAlignment()); + SDValue Hi = DAG.getNode(SPISD::Hi, dl, EVT::i32, CP); + SDValue Lo = DAG.getNode(SPISD::Lo, dl, EVT::i32, CP); + return DAG.getNode(ISD::ADD, dl, EVT::i32, Lo, Hi); } static SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); // Convert the fp value to integer in an FP register. - assert(Op.getValueType() == MVT::i32); - Op = DAG.getNode(SPISD::FTOI, dl, MVT::f32, Op.getOperand(0)); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op); + assert(Op.getValueType() == EVT::i32); + Op = DAG.getNode(SPISD::FTOI, dl, EVT::f32, Op.getOperand(0)); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op); } static SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); - assert(Op.getOperand(0).getValueType() == MVT::i32); - SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Op.getOperand(0)); + assert(Op.getOperand(0).getValueType() == EVT::i32); + SDValue Tmp = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Op.getOperand(0)); // Convert the int value to FP in an FP register. return DAG.getNode(SPISD::ITOF, dl, Op.getValueType(), Tmp); } @@ -793,21 +793,21 @@ static SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) { // Get the condition flag. SDValue CompareFlag; - if (LHS.getValueType() == MVT::i32) { - std::vector<MVT> VTs; - VTs.push_back(MVT::i32); - VTs.push_back(MVT::Flag); + if (LHS.getValueType() == EVT::i32) { + std::vector<EVT> VTs; + VTs.push_back(EVT::i32); + VTs.push_back(EVT::Flag); SDValue Ops[2] = { LHS, RHS }; CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); Opc = SPISD::BRICC; } else { - CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); + CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS); if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); Opc = SPISD::BRFCC; } - return DAG.getNode(Opc, dl, MVT::Other, Chain, Dest, - DAG.getConstant(SPCC, MVT::i32), CompareFlag); + return DAG.getNode(Opc, dl, EVT::Other, Chain, Dest, + DAG.getConstant(SPCC, EVT::i32), CompareFlag); } static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { @@ -824,21 +824,21 @@ static SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { LookThroughSetCC(LHS, RHS, CC, SPCC); SDValue CompareFlag; - if (LHS.getValueType() == MVT::i32) { - std::vector<MVT> VTs; + if (LHS.getValueType() == EVT::i32) { + std::vector<EVT> VTs; VTs.push_back(LHS.getValueType()); // subcc returns a value - VTs.push_back(MVT::Flag); + VTs.push_back(EVT::Flag); SDValue Ops[2] = { LHS, RHS }; CompareFlag = DAG.getNode(SPISD::CMPICC, dl, VTs, Ops, 2).getValue(1); Opc = SPISD::SELECT_ICC; if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC); } else { - CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, MVT::Flag, LHS, RHS); + CompareFlag = DAG.getNode(SPISD::CMPFCC, dl, EVT::Flag, LHS, RHS); Opc = SPISD::SELECT_FCC; if (SPCC == ~0U) SPCC = FPCondCCodeToFCC(CC); } return DAG.getNode(Opc, dl, TrueVal.getValueType(), TrueVal, FalseVal, - DAG.getConstant(SPCC, MVT::i32), CompareFlag); + DAG.getConstant(SPCC, EVT::i32), CompareFlag); } static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, @@ -846,40 +846,40 @@ static SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG, // vastart just stores the address of the VarArgsFrameIndex slot into the // memory location argument. DebugLoc dl = Op.getDebugLoc(); - SDValue Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, - DAG.getRegister(SP::I6, MVT::i32), + SDValue Offset = DAG.getNode(ISD::ADD, dl, EVT::i32, + DAG.getRegister(SP::I6, EVT::i32), DAG.getConstant(TLI.getVarArgsFrameOffset(), - MVT::i32)); + EVT::i32)); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), dl, Offset, Op.getOperand(1), SV, 0); } static SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.getNode(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDValue InChain = Node->getOperand(0); SDValue VAListPtr = Node->getOperand(1); const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); DebugLoc dl = Node->getDebugLoc(); - SDValue VAList = DAG.getLoad(MVT::i32, dl, InChain, VAListPtr, SV, 0); + SDValue VAList = DAG.getLoad(EVT::i32, dl, InChain, VAListPtr, SV, 0); // Increment the pointer, VAList, to the next vaarg - SDValue NextPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, VAList, + SDValue NextPtr = DAG.getNode(ISD::ADD, dl, EVT::i32, VAList, DAG.getConstant(VT.getSizeInBits()/8, - MVT::i32)); + EVT::i32)); // Store the incremented VAList to the legalized pointer InChain = DAG.getStore(VAList.getValue(1), dl, NextPtr, VAListPtr, SV, 0); // Load the actual argument out of the pointer VAList, unless this is an // f64 load. - if (VT != MVT::f64) + if (VT != EVT::f64) return DAG.getLoad(VT, dl, InChain, VAList, NULL, 0); // Otherwise, load it as i64, then do a bitconvert. - SDValue V = DAG.getLoad(MVT::i64, dl, InChain, VAList, NULL, 0); + SDValue V = DAG.getLoad(EVT::i64, dl, InChain, VAList, NULL, 0); // Bit-Convert the value to f64. SDValue Ops[2] = { - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f64, V), + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f64, V), V.getValue(1) }; return DAG.getMergeValues(Ops, 2, dl); @@ -891,14 +891,14 @@ static SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); unsigned SPReg = SP::O6; - SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, MVT::i32); - SDValue NewSP = DAG.getNode(ISD::SUB, dl, MVT::i32, SP, Size); // Value + SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, EVT::i32); + SDValue NewSP = DAG.getNode(ISD::SUB, dl, EVT::i32, SP, Size); // Value Chain = DAG.getCopyToReg(SP.getValue(1), dl, SPReg, NewSP); // Output chain // The resultant pointer is actually 16 words from the bottom of the stack, // to provide a register spill area. - SDValue NewVal = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP, - DAG.getConstant(96, MVT::i32)); + SDValue NewVal = DAG.getNode(ISD::ADD, dl, EVT::i32, NewSP, + DAG.getConstant(96, EVT::i32)); SDValue Ops[2] = { NewVal, Chain }; return DAG.getMergeValues(Ops, 2, dl); } @@ -1016,7 +1016,7 @@ SparcTargetLowering::getConstraintType(const std::string &Constraint) const { std::pair<unsigned, const TargetRegisterClass*> SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': @@ -1029,7 +1029,7 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, std::vector<unsigned> SparcTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() != 1) return std::vector<unsigned>(); diff --git a/lib/Target/Sparc/SparcISelLowering.h b/lib/Target/Sparc/SparcISelLowering.h index dab4cc6b94..912f2ba6a4 100644 --- a/lib/Target/Sparc/SparcISelLowering.h +++ b/lib/Target/Sparc/SparcISelLowering.h @@ -64,10 +64,10 @@ namespace llvm { ConstraintType getConstraintType(const std::string &Constraint) const; std::pair<unsigned, const TargetRegisterClass*> - getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const; + getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td index 8ecc5889c7..3f61cb3560 100644 --- a/lib/Target/Sparc/SparcInstrInfo.td +++ b/lib/Target/Sparc/SparcInstrInfo.td @@ -57,12 +57,12 @@ def simm13 : PatLeaf<(imm), [{ def LO10 : SDNodeXForm<imm, [{ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, - MVT::i32); + EVT::i32); }]>; def HI22 : SDNodeXForm<imm, [{ // Transformation function: shift the immediate value down into the low bits. - return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32); + return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, EVT::i32); }]>; def SETHIimm : PatLeaf<(imm), [{ diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index 482d93448b..a8357a1353 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -107,19 +107,19 @@ namespace { /// getI8Imm - Return a target constant with the specified value, of type /// i8. inline SDValue getI8Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i8); + return CurDAG->getTargetConstant(Imm, EVT::i8); } /// getI16Imm - Return a target constant with the specified value, of type /// i16. inline SDValue getI16Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i16); + return CurDAG->getTargetConstant(Imm, EVT::i16); } /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(uint64_t Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } // Include the pieces autogenerated from the target description. @@ -353,7 +353,7 @@ void SystemZDAGToDAGISel::getAddressOperandsRI(const SystemZRRIAddressMode &AM, Base = AM.Base.Reg; else Base = CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, TLI.getPointerTy()); - Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i64); + Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i64); } void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, @@ -405,7 +405,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue Op, SDValue& Addr, DOUT << "MatchAddress (final): "; DEBUG(AM12.dump()); - MVT VT = Addr.getValueType(); + EVT VT = Addr.getValueType(); if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { if (!AM12.Base.Reg.getNode()) AM12.Base.Reg = CurDAG->getRegister(0, VT); @@ -448,7 +448,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDValue Op, SDValue& Addr, DOUT << "MatchAddress (final): "; DEBUG(AM.dump()); - MVT VT = Addr.getValueType(); + EVT VT = Addr.getValueType(); if (AM.BaseType == SystemZRRIAddressMode::RegBase) { if (!AM.Base.Reg.getNode()) AM.Base.Reg = CurDAG->getRegister(0, VT); @@ -496,7 +496,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Op, SDValue Addr, DOUT << "MatchAddress (final): "; DEBUG(AM12.dump()); - MVT VT = Addr.getValueType(); + EVT VT = Addr.getValueType(); if (AM12.BaseType == SystemZRRIAddressMode::RegBase) { if (!AM12.Base.Reg.getNode()) AM12.Base.Reg = CurDAG->getRegister(0, VT); @@ -540,7 +540,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Op, SDValue Addr, DOUT << "MatchAddress (final): "; DEBUG(AM.dump()); - MVT VT = Addr.getValueType(); + EVT VT = Addr.getValueType(); if (AM.BaseType == SystemZRRIAddressMode::RegBase) { if (!AM.Base.Reg.getNode()) AM.Base.Reg = CurDAG->getRegister(0, VT); @@ -563,7 +563,7 @@ bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Op, SDValue Addr, if (MatchAddress(Addr, AM, false)) return false; - MVT VT = Addr.getValueType(); + EVT VT = Addr.getValueType(); unsigned Complexity = 0; if (AM.BaseType == SystemZRRIAddressMode::RegBase) if (AM.Base.Reg.getNode()) @@ -618,7 +618,7 @@ void SystemZDAGToDAGISel::InstructionSelect() { SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDNode *Node = Op.getNode(); - MVT NVT = Node->getValueType(0); + EVT NVT = Node->getValueType(0); DebugLoc dl = Op.getDebugLoc(); unsigned Opcode = Node->getOpcode(); @@ -648,18 +648,18 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { SDValue N0 = Node->getOperand(0); SDValue N1 = Node->getOperand(1); - MVT ResVT; + EVT ResVT; bool is32Bit = false; switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); - case MVT::i32: + case EVT::i32: Opc = SystemZ::SDIVREM32r; MOpc = SystemZ::SDIVREM32m; - ResVT = MVT::v2i64; + ResVT = EVT::v2i64; is32Bit = true; break; - case MVT::i64: + case EVT::i64: Opc = SystemZ::SDIVREM64r; MOpc = SystemZ::SDIVREM64m; - ResVT = MVT::v2i64; + ResVT = EVT::v2i64; break; } @@ -669,7 +669,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { // Prepare the dividend SDNode *Dividend; if (is32Bit) - Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, MVT::i64, N0); + Dividend = CurDAG->getTargetNode(SystemZ::MOVSX64rr32, dl, EVT::i64, N0); else Dividend = N0.getNode(); @@ -679,7 +679,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { Dividend = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(subreg_odd, MVT::i32)); + CurDAG->getTargetConstant(subreg_odd, EVT::i32)); SDNode *Result; SDValue DivVal = SDValue(Dividend, 0); @@ -699,7 +699,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + EVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); #ifndef NDEBUG @@ -716,7 +716,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + EVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); #ifndef NDEBUG @@ -736,21 +736,21 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { unsigned Opc, MOpc, ClrOpc; SDValue N0 = Node->getOperand(0); SDValue N1 = Node->getOperand(1); - MVT ResVT; + EVT ResVT; bool is32Bit = false; switch (NVT.getSimpleVT()) { default: assert(0 && "Unsupported VT!"); - case MVT::i32: + case EVT::i32: Opc = SystemZ::UDIVREM32r; MOpc = SystemZ::UDIVREM32m; ClrOpc = SystemZ::MOV64Pr0_even; - ResVT = MVT::v2i32; + ResVT = EVT::v2i32; is32Bit = true; break; - case MVT::i64: + case EVT::i64: Opc = SystemZ::UDIVREM64r; MOpc = SystemZ::UDIVREM64m; ClrOpc = SystemZ::MOV128r0_even; - ResVT = MVT::v2i64; + ResVT = EVT::v2i64; break; } @@ -768,7 +768,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { Dividend = CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, ResVT, SDValue(Tmp, 0), SDValue(Dividend, 0), - CurDAG->getTargetConstant(SubRegIdx, MVT::i32)); + CurDAG->getTargetConstant(SubRegIdx, EVT::i32)); } // Zero out even subreg @@ -793,7 +793,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + EVT::i32)); ReplaceUses(Op.getValue(0), SDValue(Div, 0)); #ifndef NDEBUG DOUT << std::string(Indent-2, ' ') << "=> "; @@ -809,7 +809,7 @@ SDNode *SystemZDAGToDAGISel::Select(SDValue Op) { dl, NVT, SDValue(Result, 0), CurDAG->getTargetConstant(SubRegIdx, - MVT::i32)); + EVT::i32)); ReplaceUses(Op.getValue(1), SDValue(Rem, 0)); #ifndef NDEBUG DOUT << std::string(Indent-2, ' ') << "=> "; diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 6265a13edb..6ffb434bbf 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -44,14 +44,14 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : RegInfo = TM.getRegisterInfo(); // Set up the register classes. - addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass); - addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass); - addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass); - addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass); + addRegisterClass(EVT::i32, SystemZ::GR32RegisterClass); + addRegisterClass(EVT::i64, SystemZ::GR64RegisterClass); + addRegisterClass(EVT::v2i32,SystemZ::GR64PRegisterClass); + addRegisterClass(EVT::v2i64,SystemZ::GR128RegisterClass); if (!UseSoftFloat) { - addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass); - addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass); + addRegisterClass(EVT::f32, SystemZ::FP32RegisterClass); + addRegisterClass(EVT::f64, SystemZ::FP64RegisterClass); addLegalFPImmediate(APFloat(+0.0)); // lzer addLegalFPImmediate(APFloat(+0.0f)); // lzdr @@ -63,92 +63,92 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) : computeRegisterProperties(); // Set shifts properties - setShiftAmountType(MVT::i64); + setShiftAmountType(EVT::i64); // Provide all sorts of operation actions - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand); - setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::f32, Expand); + setLoadExtAction(ISD::ZEXTLOAD, EVT::f32, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f32, Expand); - setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand); - setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::f64, Expand); + setLoadExtAction(ISD::ZEXTLOAD, EVT::f64, Expand); + setLoadExtAction(ISD::EXTLOAD, EVT::f64, Expand); setStackPointerRegisterToSaveRestore(SystemZ::R15D); setSchedulingPreference(SchedulingForLatency); setBooleanContents(ZeroOrOneBooleanContent); - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::BRCOND, MVT::Other, Expand); - setOperationAction(ISD::BR_CC, MVT::i32, Custom); - setOperationAction(ISD::BR_CC, MVT::i64, Custom); - setOperationAction(ISD::BR_CC, MVT::f32, Custom); - setOperationAction(ISD::BR_CC, MVT::f64, Custom); - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); - setOperationAction(ISD::JumpTable, MVT::i64, Custom); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - - setOperationAction(ISD::SDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::SDIV, MVT::i64, Expand); - setOperationAction(ISD::UDIV, MVT::i64, Expand); - setOperationAction(ISD::SREM, MVT::i32, Expand); - setOperationAction(ISD::UREM, MVT::i32, Expand); - setOperationAction(ISD::SREM, MVT::i64, Expand); - setOperationAction(ISD::UREM, MVT::i64, Expand); - - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); - - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::CTPOP, MVT::i64, Expand); - setOperationAction(ISD::CTTZ, MVT::i32, Expand); - setOperationAction(ISD::CTTZ, MVT::i64, Expand); - setOperationAction(ISD::CTLZ, MVT::i32, Promote); - setOperationAction(ISD::CTLZ, MVT::i64, Legal); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::BRCOND, EVT::Other, Expand); + setOperationAction(ISD::BR_CC, EVT::i32, Custom); + setOperationAction(ISD::BR_CC, EVT::i64, Custom); + setOperationAction(ISD::BR_CC, EVT::f32, Custom); + setOperationAction(ISD::BR_CC, EVT::f64, Custom); + setOperationAction(ISD::ConstantPool, EVT::i32, Custom); + setOperationAction(ISD::ConstantPool, EVT::i64, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i64, Custom); + setOperationAction(ISD::JumpTable, EVT::i64, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand); + + setOperationAction(ISD::SDIV, EVT::i32, Expand); + setOperationAction(ISD::UDIV, EVT::i32, Expand); + setOperationAction(ISD::SDIV, EVT::i64, Expand); + setOperationAction(ISD::UDIV, EVT::i64, Expand); + setOperationAction(ISD::SREM, EVT::i32, Expand); + setOperationAction(ISD::UREM, EVT::i32, Expand); + setOperationAction(ISD::SREM, EVT::i64, Expand); + setOperationAction(ISD::UREM, EVT::i64, Expand); + + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1, Expand); + + setOperationAction(ISD::CTPOP, EVT::i32, Expand); + setOperationAction(ISD::CTPOP, EVT::i64, Expand); + setOperationAction(ISD::CTTZ, EVT::i32, Expand); + setOperationAction(ISD::CTTZ, EVT::i64, Expand); + setOperationAction(ISD::CTLZ, EVT::i32, Promote); + setOperationAction(ISD::CTLZ, EVT::i64, Legal); // FIXME: Can we lower these 2 efficiently? - setOperationAction(ISD::SETCC, MVT::i32, Expand); - setOperationAction(ISD::SETCC, MVT::i64, Expand); - setOperationAction(ISD::SETCC, MVT::f32, Expand); - setOperationAction(ISD::SETCC, MVT::f64, Expand); - setOperationAction(ISD::SELECT, MVT::i32, Expand); - setOperationAction(ISD::SELECT, MVT::i64, Expand); - setOperationAction(ISD::SELECT, MVT::f32, Expand); - setOperationAction(ISD::SELECT, MVT::f64, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i64, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::f64, Custom); + setOperationAction(ISD::SETCC, EVT::i32, Expand); + setOperationAction(ISD::SETCC, EVT::i64, Expand); + setOperationAction(ISD::SETCC, EVT::f32, Expand); + setOperationAction(ISD::SETCC, EVT::f64, Expand); + setOperationAction(ISD::SELECT, EVT::i32, Expand); + setOperationAction(ISD::SELECT, EVT::i64, Expand); + setOperationAction(ISD::SELECT, EVT::f32, Expand); + setOperationAction(ISD::SELECT, EVT::f64, Expand); + setOperationAction(ISD::SELECT_CC, EVT::i32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::i64, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f32, Custom); + setOperationAction(ISD::SELECT_CC, EVT::f64, Custom); // Funny enough: we don't have 64-bit signed versions of these stuff, but have // unsigned. - setOperationAction(ISD::MULHS, MVT::i64, Expand); - setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand); + setOperationAction(ISD::MULHS, EVT::i64, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i64, Expand); // Lower some FP stuff - setOperationAction(ISD::FSIN, MVT::f32, Expand); - setOperationAction(ISD::FSIN, MVT::f64, Expand); - setOperationAction(ISD::FCOS, MVT::f32, Expand); - setOperationAction(ISD::FCOS, MVT::f64, Expand); - setOperationAction(ISD::FREM, MVT::f32, Expand); - setOperationAction(ISD::FREM, MVT::f64, Expand); + setOperationAction(ISD::FSIN, EVT::f32, Expand); + setOperationAction(ISD::FSIN, EVT::f64, Expand); + setOperationAction(ISD::FCOS, EVT::f32, Expand); + setOperationAction(ISD::FCOS, EVT::f64, Expand); + setOperationAction(ISD::FREM, EVT::f32, Expand); + setOperationAction(ISD::FREM, EVT::f64, Expand); // We have only 64-bit bitconverts - setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand); - setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::f32, Expand); + setOperationAction(ISD::BIT_CONVERT, EVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); - setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); - setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand); + setOperationAction(ISD::UINT_TO_FP, EVT::i32, Expand); + setOperationAction(ISD::UINT_TO_FP, EVT::i64, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, EVT::i64, Expand); - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); } SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { @@ -238,7 +238,7 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain, for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { SDValue ArgValue; CCValAssign &VA = ArgLocs[i]; - MVT LocVT = VA.getLocVT(); + EVT LocVT = VA.getLocVT(); if (VA.isRegLoc()) { // Arguments passed in registers TargetRegisterClass *RC; @@ -250,13 +250,13 @@ SystemZTargetLowering::LowerCCCArguments(SDValue Chain, << "\n"; #endif llvm_unreachable(0); - case MVT::i64: + case EVT::i64: RC = SystemZ::GR64RegisterClass; break; - case MVT::f32: + case EVT::f32: RC = SystemZ::FP32RegisterClass; break; - case MVT::f64: + case EVT::f64: RC = SystemZ::FP64RegisterClass; break; } @@ -382,7 +382,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, // Transform all store nodes into one single node because all store nodes are // independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain and @@ -404,7 +404,7 @@ SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy()); // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -530,10 +530,10 @@ SystemZTargetLowering::LowerReturn(SDValue Chain, } if (Flag.getNode()) - return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag); + return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain, Flag); // Return Void - return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain); + return DAG.getNode(SystemZISD::RET_FLAG, dl, EVT::Other, Chain); } SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, @@ -608,11 +608,11 @@ SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS, break; } - SystemZCC = DAG.getConstant(TCC, MVT::i32); + SystemZCC = DAG.getConstant(TCC, EVT::i32); DebugLoc dl = LHS.getDebugLoc(); return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP), - dl, MVT::Flag, LHS, RHS); + dl, EVT::Flag, LHS, RHS); } @@ -641,7 +641,7 @@ SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { SDValue SystemZCC; SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG); - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); + SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag); SmallVector<SDValue, 4> Ops; Ops.push_back(TrueV); Ops.push_back(FalseV); diff --git a/lib/Target/SystemZ/SystemZOperands.td b/lib/Target/SystemZ/SystemZOperands.td index 156cace9c3..0ee48c3eba 100644 --- a/lib/Target/SystemZ/SystemZOperands.td +++ b/lib/Target/SystemZ/SystemZOperands.td @@ -134,10 +134,10 @@ def i64hh16c : PatLeaf<(i64 imm), [{ def immSExt16 : PatLeaf<(imm), [{ // immSExt16 predicate - true if the immediate fits in a 16-bit sign extended // field. - if (N->getValueType(0) == MVT::i64) { + if (N->getValueType(0) == EVT::i64) { uint64_t val = N->getZExtValue(); return ((int64_t)val == (int16_t)val); - } else if (N->getValueType(0) == MVT::i32) { + } else if (N->getValueType(0) == EVT::i32) { uint32_t val = N->getZExtValue(); return ((int32_t)val == (int16_t)val); } diff --git a/lib/Target/TargetRegisterInfo.cpp b/lib/Target/TargetRegisterInfo.cpp index a84fdaa4a8..b649fca67d 100644 --- a/lib/Target/TargetRegisterInfo.cpp +++ b/lib/Target/TargetRegisterInfo.cpp @@ -40,10 +40,10 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR, TargetRegisterInfo::~TargetRegisterInfo() {} /// getPhysicalRegisterRegClass - Returns the Register Class of a physical -/// register of the given type. If type is MVT::Other, then just return any +/// register of the given type. If type is EVT::Other, then just return any /// register class the register belongs to. const TargetRegisterClass * -TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { +TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, EVT VT) const { assert(isPhysicalRegister(reg) && "reg must be a physical register"); // Pick the most super register class of the right type that contains @@ -51,7 +51,7 @@ TargetRegisterInfo::getPhysicalRegisterRegClass(unsigned reg, MVT VT) const { const TargetRegisterClass* BestRC = 0; for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ const TargetRegisterClass* RC = *I; - if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && + if ((VT == EVT::Other || RC->hasType(VT)) && RC->contains(reg) && (!BestRC || BestRC->hasSuperClass(RC))) BestRC = RC; } diff --git a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp index 58959ed3b6..1d8d7a7295 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp @@ -425,9 +425,9 @@ void X86ATTAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo, O << '%'; unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { - MVT VT = (strcmp(Modifier+6,"64") == 0) ? - MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 : - ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8)); + EVT VT = (strcmp(Modifier+6,"64") == 0) ? + EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 : + ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8)); Reg = getX86SubSuperRegister(Reg, VT); } O << TRI->getAsmName(Reg); @@ -573,19 +573,19 @@ bool X86ATTAsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode) { switch (Mode) { default: return true; // Unknown mode. case 'b': // Print QImode register - Reg = getX86SubSuperRegister(Reg, MVT::i8); + Reg = getX86SubSuperRegister(Reg, EVT::i8); break; case 'h': // Print QImode high register - Reg = getX86SubSuperRegister(Reg, MVT::i8, true); + Reg = getX86SubSuperRegister(Reg, EVT::i8, true); break; case 'w': // Print HImode register - Reg = getX86SubSuperRegister(Reg, MVT::i16); + Reg = getX86SubSuperRegister(Reg, EVT::i16); break; case 'k': // Print SImode register - Reg = getX86SubSuperRegister(Reg, MVT::i32); + Reg = getX86SubSuperRegister(Reg, EVT::i32); break; case 'q': // Print DImode register - Reg = getX86SubSuperRegister(Reg, MVT::i64); + Reg = getX86SubSuperRegister(Reg, EVT::i64); break; } @@ -685,7 +685,7 @@ static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) { unsigned Reg = MI->getOperand(i).getReg(); if (Reg == 0) continue; - MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); + MI->getOperand(i).setReg(getX86SubSuperRegister(Reg, EVT::i64)); } } diff --git a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp index 23244792d1..34908dae29 100644 --- a/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp @@ -75,9 +75,9 @@ void X86ATTAsmPrinter::printOperand(const MCInst *MI, unsigned OpNo, unsigned Reg = Op.getReg(); #if 0 if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { - MVT VT = (strcmp(Modifier+6,"64") == 0) ? - MVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? MVT::i32 : - ((strcmp(Modifier+6,"16") == 0) ? MVT::i16 : MVT::i8)); + EVT VT = (strcmp(Modifier+6,"64") == 0) ? + EVT::i64 : ((strcmp(Modifier+6, "32") == 0) ? EVT::i32 : + ((strcmp(Modifier+6,"16") == 0) ? EVT::i16 : EVT::i8)); Reg = getX86SubSuperRegister(Reg, VT); } #endif diff --git a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp index c9a761d395..08f5aa45fe 100644 --- a/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp +++ b/lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp @@ -209,9 +209,9 @@ void X86IntelAsmPrinter::printOp(const MachineOperand &MO, if (TargetRegisterInfo::isPhysicalRegister(MO.getReg())) { unsigned Reg = MO.getReg(); if (Modifier && strncmp(Modifier, "subreg", strlen("subreg")) == 0) { - MVT VT = (strcmp(Modifier,"subreg64") == 0) ? - MVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? MVT::i32 : - ((strcmp(Modifier,"subreg16") == 0) ? MVT::i16 :MVT::i8)); + EVT VT = (strcmp(Modifier,"subreg64") == 0) ? + EVT::i64 : ((strcmp(Modifier, "subreg32") == 0) ? EVT::i32 : + ((strcmp(Modifier,"subreg16") == 0) ? EVT::i16 :EVT::i8)); Reg = getX86SubSuperRegister(Reg, VT); } O << TRI->getName(Reg); @@ -376,16 +376,16 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO, switch (Mode) { default: return true; // Unknown mode. case 'b': // Print QImode register - Reg = getX86SubSuperRegister(Reg, MVT::i8); + Reg = getX86SubSuperRegister(Reg, EVT::i8); break; case 'h': // Print QImode high register - Reg = getX86SubSuperRegister(Reg, MVT::i8, true); + Reg = getX86SubSuperRegister(Reg, EVT::i8, true); break; case 'w': // Print HImode register - Reg = getX86SubSuperRegister(Reg, MVT::i16); + Reg = getX86SubSuperRegister(Reg, EVT::i16); break; case 'k': // Print SImode register - Reg = getX86SubSuperRegister(Reg, MVT::i32); + Reg = getX86SubSuperRegister(Reg, EVT::i32); break; } diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index a4bb1be799..30466817c7 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -79,16 +79,16 @@ public: #include "X86GenFastISel.inc" private: - bool X86FastEmitCompare(Value *LHS, Value *RHS, MVT VT); + bool X86FastEmitCompare(Value *LHS, Value *RHS, EVT VT); - bool X86FastEmitLoad(MVT VT, const X86AddressMode &AM, unsigned &RR); + bool X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &RR); - bool X86FastEmitStore(MVT VT, Value *Val, + bool X86FastEmitStore(EVT VT, Value *Val, const X86AddressMode &AM); - bool X86FastEmitStore(MVT VT, unsigned Val, + bool X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM); - bool X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, unsigned Src, MVT SrcVT, + bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, unsigned &ResultReg); bool X86SelectAddress(Value *V, X86AddressMode &AM); @@ -133,36 +133,36 @@ private: /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is /// computed in an SSE register, not on the X87 floating point stack. - bool isScalarFPTypeInSSEReg(MVT VT) const { - return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 - (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 + bool isScalarFPTypeInSSEReg(EVT VT) const { + return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 + (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 } - bool isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1 = false); + bool isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1 = false); }; } // end anonymous namespace. -bool X86FastISel::isTypeLegal(const Type *Ty, MVT &VT, bool AllowI1) { +bool X86FastISel::isTypeLegal(const Type *Ty, EVT &VT, bool AllowI1) { VT = TLI.getValueType(Ty, /*HandleUnknown=*/true); - if (VT == MVT::Other || !VT.isSimple()) + if (VT == EVT::Other || !VT.isSimple()) // Unhandled type. Halt "fast" selection and bail. return false; // For now, require SSE/SSE2 for performing floating-point operations, // since x87 requires additional work. - if (VT == MVT::f64 && !X86ScalarSSEf64) + if (VT == EVT::f64 && !X86ScalarSSEf64) return false; - if (VT == MVT::f32 && !X86ScalarSSEf32) + if (VT == EVT::f32 && !X86ScalarSSEf32) return false; // Similarly, no f80 support yet. - if (VT == MVT::f80) + if (VT == EVT::f80) return false; // We only handle legal types. For example, on x86-32 the instruction // selector contains all of the 64-bit instructions from x86-64, // under the assumption that i64 won't be used if the target doesn't // support it. - return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); + return (AllowI1 && VT == EVT::i1) || TLI.isTypeLegal(VT); } #include "X86GenCallingConv.inc" @@ -188,31 +188,31 @@ CCAssignFn *X86FastISel::CCAssignFnForCall(unsigned CC, bool isTaillCall) { /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. /// Return true and the result register by reference if it is possible. -bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, +bool X86FastISel::X86FastEmitLoad(EVT VT, const X86AddressMode &AM, unsigned &ResultReg) { // Get opcode and regclass of the output for the given load instruction. unsigned Opc = 0; const TargetRegisterClass *RC = NULL; switch (VT.getSimpleVT()) { default: return false; - case MVT::i8: + case EVT::i8: Opc = X86::MOV8rm; RC = X86::GR8RegisterClass; break; - case MVT::i16: + case EVT::i16: Opc = X86::MOV16rm; RC = X86::GR16RegisterClass; break; - case MVT::i32: + case EVT::i32: Opc = X86::MOV32rm; RC = X86::GR32RegisterClass; break; - case MVT::i64: + case EVT::i64: // Must be in x86-64 mode. Opc = X86::MOV64rm; RC = X86::GR64RegisterClass; break; - case MVT::f32: + case EVT::f32: if (Subtarget->hasSSE1()) { Opc = X86::MOVSSrm; RC = X86::FR32RegisterClass; @@ -221,7 +221,7 @@ bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, RC = X86::RFP32RegisterClass; } break; - case MVT::f64: + case EVT::f64: if (Subtarget->hasSSE2()) { Opc = X86::MOVSDrm; RC = X86::FR64RegisterClass; @@ -230,7 +230,7 @@ bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, RC = X86::RFP64RegisterClass; } break; - case MVT::f80: + case EVT::f80: // No f80 support yet. return false; } @@ -245,21 +245,21 @@ bool X86FastISel::X86FastEmitLoad(MVT VT, const X86AddressMode &AM, /// and a displacement offset, or a GlobalAddress, /// i.e. V. Return true if it is possible. bool -X86FastISel::X86FastEmitStore(MVT VT, unsigned Val, +X86FastISel::X86FastEmitStore(EVT VT, unsigned Val, const X86AddressMode &AM) { // Get opcode and regclass of the output for the given store instruction. unsigned Opc = 0; switch (VT.getSimpleVT()) { - case MVT::f80: // No f80 support yet. + case EVT::f80: // No f80 support yet. default: return false; - case MVT::i8: Opc = X86::MOV8mr; break; - case MVT::i16: Opc = X86::MOV16mr; break; - case MVT::i32: Opc = X86::MOV32mr; break; - case MVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. - case MVT::f32: + case EVT::i8: Opc = X86::MOV8mr; break; + case EVT::i16: Opc = X86::MOV16mr; break; + case EVT::i32: Opc = X86::MOV32mr; break; + case EVT::i64: Opc = X86::MOV64mr; break; // Must be in x86-64 mode. + case EVT::f32: Opc = Subtarget->hasSSE1() ? X86::MOVSSmr : X86::ST_Fp32m; break; - case MVT::f64: + case EVT::f64: Opc = Subtarget->hasSSE2() ? X86::MOVSDmr : X86::ST_Fp64m; break; } @@ -268,7 +268,7 @@ X86FastISel::X86FastEmitStore(MVT VT, unsigned Val, return true; } -bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val, +bool X86FastISel::X86FastEmitStore(EVT VT, Value *Val, const X86AddressMode &AM) { // Handle 'null' like i32/i64 0. if (isa<ConstantPointerNull>(Val)) @@ -279,10 +279,10 @@ bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val, unsigned Opc = 0; switch (VT.getSimpleVT()) { default: break; - case MVT::i8: Opc = X86::MOV8mi; break; - case MVT::i16: Opc = X86::MOV16mi; break; - case MVT::i32: Opc = X86::MOV32mi; break; - case MVT::i64: + case EVT::i8: Opc = X86::MOV8mi; break; + case EVT::i16: Opc = X86::MOV16mi; break; + case EVT::i32: Opc = X86::MOV32mi; break; + case EVT::i64: // Must be a 32-bit sign extended value. if ((int)CI->getSExtValue() == CI->getSExtValue()) Opc = X86::MOV64mi32; @@ -306,8 +306,8 @@ bool X86FastISel::X86FastEmitStore(MVT VT, Value *Val, /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. /// ISD::SIGN_EXTEND). -bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, MVT DstVT, - unsigned Src, MVT SrcVT, +bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, + unsigned Src, EVT SrcVT, unsigned &ResultReg) { unsigned RR = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); @@ -478,7 +478,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { StubAM.GV = GV; StubAM.GVOpFlags = GVFlags; - if (TLI.getPointerTy() == MVT::i64) { + if (TLI.getPointerTy() == EVT::i64) { Opc = X86::MOV64rm; RC = X86::GR64RegisterClass; @@ -605,7 +605,7 @@ bool X86FastISel::X86SelectCallAddress(Value *V, X86AddressMode &AM) { /// X86SelectStore - Select and emit code to implement store instructions. bool X86FastISel::X86SelectStore(Instruction* I) { - MVT VT; + EVT VT; if (!isTypeLegal(I->getOperand(0)->getType(), VT)) return false; @@ -619,7 +619,7 @@ bool X86FastISel::X86SelectStore(Instruction* I) { /// X86SelectLoad - Select and emit code to implement load instructions. /// bool X86FastISel::X86SelectLoad(Instruction *I) { - MVT VT; + EVT VT; if (!isTypeLegal(I->getType(), VT)) return false; @@ -635,29 +635,29 @@ bool X86FastISel::X86SelectLoad(Instruction *I) { return false; } -static unsigned X86ChooseCmpOpcode(MVT VT) { +static unsigned X86ChooseCmpOpcode(EVT VT) { switch (VT.getSimpleVT()) { default: return 0; - case MVT::i8: return X86::CMP8rr; - case MVT::i16: return X86::CMP16rr; - case MVT::i32: return X86::CMP32rr; - case MVT::i64: return X86::CMP64rr; - case MVT::f32: return X86::UCOMISSrr; - case MVT::f64: return X86::UCOMISDrr; + case EVT::i8: return X86::CMP8rr; + case EVT::i16: return X86::CMP16rr; + case EVT::i32: return X86::CMP32rr; + case EVT::i64: return X86::CMP64rr; + case EVT::f32: return X86::UCOMISSrr; + case EVT::f64: return X86::UCOMISDrr; } } /// X86ChooseCmpImmediateOpcode - If we have a comparison with RHS as the RHS /// of the comparison, return an opcode that works for the compare (e.g. /// CMP32ri) otherwise return 0. -static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) { +static unsigned X86ChooseCmpImmediateOpcode(EVT VT, ConstantInt *RHSC) { switch (VT.getSimpleVT()) { // Otherwise, we can't fold the immediate into this comparison. default: return 0; - case MVT::i8: return X86::CMP8ri; - case MVT::i16: return X86::CMP16ri; - case MVT::i32: return X86::CMP32ri; - case MVT::i64: + case EVT::i8: return X86::CMP8ri; + case EVT::i16: return X86::CMP16ri; + case EVT::i32: return X86::CMP32ri; + case EVT::i64: // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext // field. if ((int)RHSC->getSExtValue() == RHSC->getSExtValue()) @@ -666,7 +666,7 @@ static unsigned X86ChooseCmpImmediateOpcode(MVT VT, ConstantInt *RHSC) { } } -bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) { +bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, EVT VT) { unsigned Op0Reg = getRegForValue(Op0); if (Op0Reg == 0) return false; @@ -698,7 +698,7 @@ bool X86FastISel::X86FastEmitCompare(Value *Op0, Value *Op1, MVT VT) { bool X86FastISel::X86SelectCmp(Instruction *I) { CmpInst *CI = cast<CmpInst>(I); - MVT VT; + EVT VT; if (!isTypeLegal(I->getOperand(0)->getType(), VT)) return false; @@ -778,7 +778,7 @@ bool X86FastISel::X86SelectZExt(Instruction *I) { unsigned ResultReg = getRegForValue(I->getOperand(0)); if (ResultReg == 0) return false; // Set the high bits to zero. - ResultReg = FastEmitZExtFromI1(MVT::i8, ResultReg); + ResultReg = FastEmitZExtFromI1(EVT::i8, ResultReg); if (ResultReg == 0) return false; UpdateValueMap(I, ResultReg); return true; @@ -798,7 +798,7 @@ bool X86FastISel::X86SelectBranch(Instruction *I) { // Fold the common case of a conditional branch with a comparison. if (CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { if (CI->hasOneUse()) { - MVT VT = TLI.getValueType(CI->getOperand(0)->getType()); + EVT VT = TLI.getValueType(CI->getOperand(0)->getType()); // Try to take advantage of fallthrough opportunities. CmpInst::Predicate Predicate = CI->getPredicate(); @@ -975,8 +975,8 @@ bool X86FastISel::X86SelectShift(Instruction *I) { return false; } - MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) + EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); + if (VT == EVT::Other || !isTypeLegal(I->getType(), VT)) return false; unsigned Op0Reg = getRegForValue(I->getOperand(0)); @@ -1009,19 +1009,19 @@ bool X86FastISel::X86SelectShift(Instruction *I) { } bool X86FastISel::X86SelectSelect(Instruction *I) { - MVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); - if (VT == MVT::Other || !isTypeLegal(I->getType(), VT)) + EVT VT = TLI.getValueType(I->getType(), /*HandleUnknown=*/true); + if (VT == EVT::Other || !isTypeLegal(I->getType(), VT)) return false; unsigned Opc = 0; const TargetRegisterClass *RC = NULL; - if (VT.getSimpleVT() == MVT::i16) { + if (VT.getSimpleVT() == EVT::i16) { Opc = X86::CMOVE16rr; RC = &X86::GR16RegClass; - } else if (VT.getSimpleVT() == MVT::i32) { + } else if (VT.getSimpleVT() == EVT::i32) { Opc = X86::CMOVE32rr; RC = &X86::GR32RegClass; - } else if (VT.getSimpleVT() == MVT::i64) { + } else if (VT.getSimpleVT() == EVT::i64) { Opc = X86::CMOVE64rr; RC = &X86::GR64RegClass; } else { @@ -1081,14 +1081,14 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) { if (Subtarget->is64Bit()) // All other cases should be handled by the tblgen generated code. return false; - MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(I->getType()); + EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(I->getType()); // This code only handles truncation to byte right now. - if (DstVT != MVT::i8 && DstVT != MVT::i1) + if (DstVT != EVT::i8 && DstVT != EVT::i1) // All other cases should be handled by the tblgen generated code. return false; - if (SrcVT != MVT::i16 && SrcVT != MVT::i32) + if (SrcVT != EVT::i16 && SrcVT != EVT::i32) // All other cases should be handled by the tblgen generated code. return false; @@ -1098,14 +1098,14 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) { return false; // First issue a copy to GR16_ABCD or GR32_ABCD. - unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr; - const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16) + unsigned CopyOpc = (SrcVT == EVT::i16) ? X86::MOV16rr : X86::MOV32rr; + const TargetRegisterClass *CopyRC = (SrcVT == EVT::i16) ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass; unsigned CopyReg = createResultReg(CopyRC); BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg); // Then issue an extract_subreg. - unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8, + unsigned ResultReg = FastEmitInst_extractsubreg(EVT::i8, CopyReg, X86::SUBREG_8BIT); if (!ResultReg) return false; @@ -1150,7 +1150,7 @@ bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { const Type *RetTy = cast<StructType>(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); - MVT VT; + EVT VT; if (!isTypeLegal(RetTy, VT)) return false; @@ -1164,9 +1164,9 @@ bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { return false; unsigned OpC = 0; - if (VT == MVT::i32) + if (VT == EVT::i32) OpC = X86::ADD32rr; - else if (VT == MVT::i64) + else if (VT == EVT::i64) OpC = X86::ADD64rr; else return false; @@ -1185,7 +1185,7 @@ bool X86FastISel::X86VisitIntrinsicCall(IntrinsicInst &I) { if (DestReg1 != ResultReg) ResultReg = DestReg1+1; else - ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); + ResultReg = createResultReg(TLI.getRegClassFor(EVT::i8)); unsigned Opc = X86::SETBr; if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) @@ -1229,9 +1229,9 @@ bool X86FastISel::X86SelectCall(Instruction *I) { // Handle *simple* calls for now. const Type *RetTy = CS.getType(); - MVT RetVT; + EVT RetVT; if (RetTy == Type::VoidTy) - RetVT = MVT::isVoid; + RetVT = EVT::isVoid; else if (!isTypeLegal(RetTy, RetVT, true)) return false; @@ -1251,15 +1251,15 @@ bool X86FastISel::X86SelectCall(Instruction *I) { // Allow calls which produce i1 results. bool AndToI1 = false; - if (RetVT == MVT::i1) { - RetVT = MVT::i8; + if (RetVT == EVT::i1) { + RetVT = EVT::i8; AndToI1 = true; } // Deal with call operands first. SmallVector<Value*, 8> ArgVals; SmallVector<unsigned, 8> Args; - SmallVector<MVT, 8> ArgVTs; + SmallVector<EVT, 8> ArgVTs; SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; Args.reserve(CS.arg_size()); ArgVals.reserve(CS.arg_size()); @@ -1285,7 +1285,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { return false; const Type *ArgTy = (*i)->getType(); - MVT ArgVT; + EVT ArgVT; if (!isTypeLegal(ArgTy, ArgVT)) return false; unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); @@ -1315,7 +1315,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; unsigned Arg = Args[VA.getValNo()]; - MVT ArgVT = ArgVTs[VA.getValNo()]; + EVT ArgVT = ArgVTs[VA.getValNo()]; // Promote the value if needed. switch (VA.getLocInfo()) { @@ -1445,14 +1445,14 @@ bool X86FastISel::X86SelectCall(Instruction *I) { BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0); // Now handle call return value (if any). - if (RetVT.getSimpleVT() != MVT::isVoid) { + if (RetVT.getSimpleVT() != EVT::isVoid) { SmallVector<CCValAssign, 16> RVLocs; CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); // Copy all of the result registers out of their specified physreg. assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); - MVT CopyVT = RVLocs[0].getValVT(); + EVT CopyVT = RVLocs[0].getValVT(); TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); TargetRegisterClass *SrcRC = DstRC; @@ -1462,7 +1462,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) { if ((RVLocs[0].getLocReg() == X86::ST0 || RVLocs[0].getLocReg() == X86::ST1) && isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { - CopyVT = MVT::f80; + CopyVT = EVT::f80; SrcRC = X86::RSTRegisterClass; DstRC = X86::RFP80RegisterClass; } @@ -1476,14 +1476,14 @@ bool X86FastISel::X86SelectCall(Instruction *I) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and // then loading it back. Ewww... - MVT ResVT = RVLocs[0].getValVT(); - unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; + EVT ResVT = RVLocs[0].getValVT(); + unsigned Opc = ResVT == EVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; unsigned MemSize = ResVT.getSizeInBits()/8; int FI = MFI.CreateStackObject(MemSize, MemSize); addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg); - DstRC = ResVT == MVT::f32 + DstRC = ResVT == EVT::f32 ? X86::FR32RegisterClass : X86::FR64RegisterClass; - Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; + Opc = ResVT == EVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; ResultReg = createResultReg(DstRC); addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI); } @@ -1536,8 +1536,8 @@ X86FastISel::TargetSelectInstruction(Instruction *I) { return X86SelectExtractValue(I); case Instruction::IntToPtr: // Deliberate fall-through. case Instruction::PtrToInt: { - MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(I->getType()); + EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(I->getType()); if (DstVT.bitsGT(SrcVT)) return X86SelectZExt(I); if (DstVT.bitsLT(SrcVT)) @@ -1553,7 +1553,7 @@ X86FastISel::TargetSelectInstruction(Instruction *I) { } unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { - MVT VT; + EVT VT; if (!isTypeLegal(C->getType(), VT)) return false; @@ -1562,24 +1562,24 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { const TargetRegisterClass *RC = NULL; switch (VT.getSimpleVT()) { default: return false; - case MVT::i8: + case EVT::i8: Opc = X86::MOV8rm; RC = X86::GR8RegisterClass; break; - case MVT::i16: + case EVT::i16: Opc = X86::MOV16rm; RC = X86::GR16RegisterClass; break; - case MVT::i32: + case EVT::i32: Opc = X86::MOV32rm; RC = X86::GR32RegisterClass; break; - case MVT::i64: + case EVT::i64: // Must be in x86-64 mode. Opc = X86::MOV64rm; RC = X86::GR64RegisterClass; break; - case MVT::f32: + case EVT::f32: if (Subtarget->hasSSE1()) { Opc = X86::MOVSSrm; RC = X86::FR32RegisterClass; @@ -1588,7 +1588,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { RC = X86::RFP32RegisterClass; } break; - case MVT::f64: + case EVT::f64: if (Subtarget->hasSSE2()) { Opc = X86::MOVSDrm; RC = X86::FR64RegisterClass; @@ -1597,7 +1597,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { RC = X86::RFP64RegisterClass; } break; - case MVT::f80: + case EVT::f80: // No f80 support yet. return false; } @@ -1606,7 +1606,7 @@ unsigned X86FastISel::TargetMaterializeConstant(Constant *C) { if (isa<GlobalValue>(C)) { X86AddressMode AM; if (X86SelectAddress(C, AM)) { - if (TLI.getPointerTy() == MVT::i32) + if (TLI.getPointerTy() == EVT::i32) Opc = X86::LEA32r; else Opc = X86::LEA64r; diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp index 1a99b08c96..4aee4930fc 100644 --- a/lib/Target/X86/X86ISelDAGToDAG.cpp +++ b/lib/Target/X86/X86ISelDAGToDAG.cpp @@ -186,7 +186,7 @@ namespace { private: SDNode *Select(SDValue N); SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); - SDNode *SelectAtomicLoadAdd(SDNode *Node, MVT NVT); + SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT); bool MatchSegmentBaseAddress(SDValue N, X86ISelAddressMode &AM); bool MatchLoad(SDValue N, X86ISelAddressMode &AM); @@ -233,40 +233,40 @@ namespace { // These are 32-bit even in 64-bit mode since RIP relative offset // is 32-bit. if (AM.GV) - Disp = CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp, + Disp = CurDAG->getTargetGlobalAddress(AM.GV, EVT::i32, AM.Disp, AM.SymbolFlags); else if (AM.CP) - Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, + Disp = CurDAG->getTargetConstantPool(AM.CP, EVT::i32, AM.Align, AM.Disp, AM.SymbolFlags); else if (AM.ES) - Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags); + Disp = CurDAG->getTargetExternalSymbol(AM.ES, EVT::i32, AM.SymbolFlags); else if (AM.JT != -1) - Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); + Disp = CurDAG->getTargetJumpTable(AM.JT, EVT::i32, AM.SymbolFlags); else - Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); + Disp = CurDAG->getTargetConstant(AM.Disp, EVT::i32); if (AM.Segment.getNode()) Segment = AM.Segment; else - Segment = CurDAG->getRegister(0, MVT::i32); + Segment = CurDAG->getRegister(0, EVT::i32); } /// getI8Imm - Return a target constant with the specified value, of type /// i8. inline SDValue getI8Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i8); + return CurDAG->getTargetConstant(Imm, EVT::i8); } /// getI16Imm - Return a target constant with the specified value, of type /// i16. inline SDValue getI16Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i16); + return CurDAG->getTargetConstant(Imm, EVT::i16); } /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } /// getGlobalBaseReg - Return an SDNode that returns the value of @@ -408,7 +408,7 @@ static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load, Ops.push_back(Chain.getOperand(i)); SDValue NewChain = CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), - MVT::Other, &Ops[0], Ops.size()); + EVT::Other, &Ops[0], Ops.size()); Ops.clear(); Ops.push_back(NewChain); } @@ -599,8 +599,8 @@ void X86DAGToDAGISel::PreprocessForFPConvert() { // If the source and destination are SSE registers, then this is a legal // conversion that should not be lowered. - MVT SrcVT = N->getOperand(0).getValueType(); - MVT DstVT = N->getValueType(0); + EVT SrcVT = N->getOperand(0).getValueType(); + EVT DstVT = N->getValueType(0); bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); if (SrcIsSSE && DstIsSSE) @@ -618,7 +618,7 @@ void X86DAGToDAGISel::PreprocessForFPConvert() { // Here we could have an FP stack truncation or an FPStack <-> SSE convert. // FPStack has extload and truncstore. SSE can fold direct loads into other // operations. Based on this, decide what we want to do. - MVT MemVT; + EVT MemVT; if (N->getOpcode() == ISD::FP_ROUND) MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. else @@ -764,7 +764,7 @@ bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { } if (N.getOpcode() == X86ISD::WrapperRIP) - AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); + AM.setBaseReg(CurDAG->getRegister(X86::RIP, EVT::i64)); return false; } @@ -1001,7 +1001,7 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, RHS.getNode()->getOpcode() == ISD::TRUNCATE || RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && - RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) + RHS.getNode()->getOperand(0).getValueType() == EVT::i32)) ++Cost; // If the base is a register with multiple uses, this // transformation may save a mov. @@ -1111,13 +1111,13 @@ bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, unsigned ScaleLog = 8 - C1->getZExtValue(); if (ScaleLog > 0 && ScaleLog < 4 && C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) { - SDValue Eight = CurDAG->getConstant(8, MVT::i8); + SDValue Eight = CurDAG->getConstant(8, EVT::i8); SDValue Mask = CurDAG->getConstant(0xff, N.getValueType()); SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), X, Eight); SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(), Srl, Mask); - SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8); + SDValue ShlCount = CurDAG->getConstant(ScaleLog, EVT::i8); SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), And, ShlCount); @@ -1267,7 +1267,7 @@ bool X86DAGToDAGISel::SelectAddr(SDValue Op, SDValue N, SDValue &Base, if (!Done && MatchAddress(N, AM)) return false; - MVT VT = N.getValueType(); + EVT VT = N.getValueType(); if (AM.BaseType == X86ISelAddressMode::RegBase) { if (!AM.Base.Reg.getNode()) AM.Base.Reg = CurDAG->getRegister(0, VT); @@ -1333,14 +1333,14 @@ bool X86DAGToDAGISel::SelectLEAAddr(SDValue Op, SDValue N, // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support // segments. SDValue Copy = AM.Segment; - SDValue T = CurDAG->getRegister(0, MVT::i32); + SDValue T = CurDAG->getRegister(0, EVT::i32); AM.Segment = T; if (MatchAddress(N, AM)) return false; assert (T == AM.Segment); AM.Segment = Copy; - MVT VT = N.getValueType(); + EVT VT = N.getValueType(); unsigned Complexity = 0; if (AM.BaseType == X86ISelAddressMode::RegBase) if (AM.Base.Reg.getNode()) @@ -1400,11 +1400,11 @@ bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue Op, SDValue N, SDValue &Base, AM.Base.Reg = CurDAG->getRegister(0, N.getValueType()); AM.SymbolFlags = GA->getTargetFlags(); - if (N.getValueType() == MVT::i32) { + if (N.getValueType() == EVT::i32) { AM.Scale = 1; - AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); + AM.IndexReg = CurDAG->getRegister(X86::EBX, EVT::i32); } else { - AM.IndexReg = CurDAG->getRegister(0, MVT::i64); + AM.IndexReg = CurDAG->getRegister(0, EVT::i64); } SDValue Segment; @@ -1435,7 +1435,7 @@ SDNode *X86DAGToDAGISel::getGlobalBaseReg() { static SDNode *FindCallStartFromCall(SDNode *Node) { if (Node->getOpcode() == ISD::CALLSEQ_START) return Node; - assert(Node->getOperand(0).getValueType() == MVT::Other && + assert(Node->getOperand(0).getValueType() == EVT::Other && "Node doesn't have a token chain argument!"); return FindCallStartFromCall(Node->getOperand(0).getNode()); } @@ -1451,11 +1451,11 @@ SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { SDValue LSI = Node->getOperand(4); // MemOperand const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, LSI, Chain}; return CurDAG->getTargetNode(Opc, Node->getDebugLoc(), - MVT::i32, MVT::i32, MVT::Other, Ops, + EVT::i32, EVT::i32, EVT::Other, Ops, array_lengthof(Ops)); } -SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { +SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { if (Node->hasAnyUseOfValue(0)) return 0; @@ -1497,7 +1497,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { unsigned Opc = 0; switch (NVT.getSimpleVT()) { default: return 0; - case MVT::i8: + case EVT::i8: if (isInc) Opc = X86::LOCK_INC8m; else if (isDec) @@ -1514,7 +1514,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { Opc = X86::LOCK_ADD8mr; } break; - case MVT::i16: + case EVT::i16: if (isInc) Opc = X86::LOCK_INC16m; else if (isDec) @@ -1537,7 +1537,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { Opc = X86::LOCK_ADD16mr; } break; - case MVT::i32: + case EVT::i32: if (isInc) Opc = X86::LOCK_INC32m; else if (isDec) @@ -1560,7 +1560,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { Opc = X86::LOCK_ADD32mr; } break; - case MVT::i64: + case EVT::i64: if (isInc) Opc = X86::LOCK_INC64m; else if (isDec) @@ -1591,12 +1591,12 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { SDValue MemOp = CurDAG->getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); if (isInc || isDec) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, MemOp, Chain }; - SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7), 0); + SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 7), 0); SDValue RetVals[] = { Undef, Ret }; return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); } else { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, MemOp, Chain }; - SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8), 0); + SDValue Ret = SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Other, Ops, 8), 0); SDValue RetVals[] = { Undef, Ret }; return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); } @@ -1604,7 +1604,7 @@ SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, MVT NVT) { SDNode *X86DAGToDAGISel::Select(SDValue N) { SDNode *Node = N.getNode(); - MVT NVT = Node->getValueType(0); + EVT NVT = Node->getValueType(0); unsigned Opc, MOpc; unsigned Opcode = Node->getOpcode(); DebugLoc dl = Node->getDebugLoc(); @@ -1666,28 +1666,28 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { if (!isSigned) { switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; - case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; - case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; - case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; + case EVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; + case EVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; + case EVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; + case EVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; } } else { switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; - case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; - case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; - case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; + case EVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; + case EVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; + case EVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; + case EVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; } } unsigned LoReg, HiReg; switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; - case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; - case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; - case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; + case EVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; + case EVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; + case EVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; + case EVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; } SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; @@ -1706,14 +1706,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, + CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops, array_lengthof(Ops)); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0); } // Copy the low half of the result, if it is needed. @@ -1737,15 +1737,15 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - X86::AX, MVT::i16, InFlag); + X86::AX, EVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16, Result, - CurDAG->getTargetConstant(8, MVT::i8)), 0); + CurDAG->getTargetConstant(8, EVT::i8)), 0); // Then truncate it down to i8. - SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32); + SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32); Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, - MVT::i8, Result, SRIdx), 0); + EVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, InFlag); @@ -1777,18 +1777,18 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { if (!isSigned) { switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; - case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; - case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; - case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; + case EVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; + case EVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; + case EVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; + case EVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; } } else { switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; - case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; - case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; - case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; + case EVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; + case EVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; + case EVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; + case EVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; } } @@ -1796,22 +1796,22 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { unsigned ClrOpcode, SExtOpcode; switch (NVT.getSimpleVT()) { default: llvm_unreachable("Unsupported VT!"); - case MVT::i8: + case EVT::i8: LoReg = X86::AL; HiReg = X86::AH; ClrOpcode = 0; SExtOpcode = X86::CBW; break; - case MVT::i16: + case EVT::i16: LoReg = X86::AX; HiReg = X86::DX; ClrOpcode = X86::MOV16r0; SExtOpcode = X86::CWD; break; - case MVT::i32: + case EVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; ClrOpcode = X86::MOV32r0; SExtOpcode = X86::CDQ; break; - case MVT::i64: + case EVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; ClrOpcode = ~0U; // NOT USED. SExtOpcode = X86::CQO; @@ -1823,21 +1823,21 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { bool signBitIsZero = CurDAG->SignBitIsZero(N0); SDValue InFlag; - if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { + if (NVT == EVT::i8 && (!isSigned || signBitIsZero)) { // Special case for div8, just use a move with zero extension to AX to // clear the upper 8 bits (AH). SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; if (TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, MVT::i16, - MVT::Other, Ops, + SDValue(CurDAG->getTargetNode(X86::MOVZX16rm8, dl, EVT::i16, + EVT::Other, Ops, array_lengthof(Ops)), 0); Chain = Move.getValue(1); ReplaceUses(N0.getValue(1), Chain); } else { Move = - SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, MVT::i16, N0),0); + SDValue(CurDAG->getTargetNode(X86::MOVZX16rr8, dl, EVT::i16, N0),0); Chain = CurDAG->getEntryNode(); } Chain = CurDAG->getCopyToReg(Chain, dl, X86::AX, Move, SDValue()); @@ -1849,24 +1849,24 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { if (isSigned && !signBitIsZero) { // Sign extend the low part into the high part. InFlag = - SDValue(CurDAG->getTargetNode(SExtOpcode, dl, MVT::Flag, InFlag),0); + SDValue(CurDAG->getTargetNode(SExtOpcode, dl, EVT::Flag, InFlag),0); } else { // Zero out the high part, effectively zero extending the input. SDValue ClrNode; - if (NVT.getSimpleVT() == MVT::i64) { - ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, MVT::i32), + if (NVT.getSimpleVT() == EVT::i64) { + ClrNode = SDValue(CurDAG->getTargetNode(X86::MOV32r0, dl, EVT::i32), 0); // We just did a 32-bit clear, insert it into a 64-bit register to // clear the whole 64-bit reg. SDValue Undef = SDValue(CurDAG->getTargetNode(TargetInstrInfo::IMPLICIT_DEF, - dl, MVT::i64), 0); + dl, EVT::i64), 0); SDValue SubRegNo = - CurDAG->getTargetConstant(X86::SUBREG_32BIT, MVT::i32); + CurDAG->getTargetConstant(X86::SUBREG_32BIT, EVT::i32); ClrNode = SDValue(CurDAG->getTargetNode(TargetInstrInfo::INSERT_SUBREG, dl, - MVT::i64, Undef, ClrNode, SubRegNo), + EVT::i64, Undef, ClrNode, SubRegNo), 0); } else { ClrNode = SDValue(CurDAG->getTargetNode(ClrOpcode, dl, NVT), 0); @@ -1881,14 +1881,14 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), InFlag }; SDNode *CNode = - CurDAG->getTargetNode(MOpc, dl, MVT::Other, MVT::Flag, Ops, + CurDAG->getTargetNode(MOpc, dl, EVT::Other, EVT::Flag, Ops, array_lengthof(Ops)); InFlag = SDValue(CNode, 1); // Update the chain. ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); } else { InFlag = - SDValue(CurDAG->getTargetNode(Opc, dl, MVT::Flag, N1, InFlag), 0); + SDValue(CurDAG->getTargetNode(Opc, dl, EVT::Flag, N1, InFlag), 0); } // Copy the division (low) result, if it is needed. @@ -1912,16 +1912,16 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { // Prevent use of AH in a REX instruction by referencing AX instead. // Shift it down 8 bits. Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, - X86::AX, MVT::i16, InFlag); + X86::AX, EVT::i16, InFlag); InFlag = Result.getValue(2); - Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, MVT::i16, + Result = SDValue(CurDAG->getTargetNode(X86::SHR16ri, dl, EVT::i16, Result, - CurDAG->getTargetConstant(8, MVT::i8)), + CurDAG->getTargetConstant(8, EVT::i8)), 0); // Then truncate it down to i8. - SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, MVT::i32); + SDValue SRIdx = CurDAG->getTargetConstant(X86::SUBREG_8BIT, EVT::i32); Result = SDValue(CurDAG->getTargetNode(X86::EXTRACT_SUBREG, dl, - MVT::i8, Result, SRIdx), 0); + EVT::i8, Result, SRIdx), 0); } else { Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, HiReg, NVT, InFlag); @@ -1981,7 +1981,7 @@ SDNode *X86DAGToDAGISel::Select(SDValue N) { TLI.getPointerTy()); SDValue Ops[] = { Tmp1, Tmp2, Chain }; return CurDAG->getTargetNode(TargetInstrInfo::DECLARE, dl, - MVT::Other, Ops, + EVT::Other, Ops, array_lengthof(Ops)); } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3fbb846aec..855167360f 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -48,7 +48,7 @@ static cl::opt<bool> DisableMMX("disable-mmx", cl::Hidden, cl::desc("Disable use of MMX")); // Forward declarations. -static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, +static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2); static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { @@ -79,7 +79,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // Set up the TargetLowering object. // X86 is weird, it always uses i8 for shift amounts and setcc results. - setShiftAmountType(MVT::i8); + setShiftAmountType(EVT::i8); setBooleanContents(ZeroOrOneBooleanContent); setSchedulingPreference(SchedulingForRegPressure); setStackPointerRegisterToSaveRestore(X86StackPtr); @@ -98,113 +98,113 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } // Set up the register classes. - addRegisterClass(MVT::i8, X86::GR8RegisterClass); - addRegisterClass(MVT::i16, X86::GR16RegisterClass); - addRegisterClass(MVT::i32, X86::GR32RegisterClass); + addRegisterClass(EVT::i8, X86::GR8RegisterClass); + addRegisterClass(EVT::i16, X86::GR16RegisterClass); + addRegisterClass(EVT::i32, X86::GR32RegisterClass); if (Subtarget->is64Bit()) - addRegisterClass(MVT::i64, X86::GR64RegisterClass); + addRegisterClass(EVT::i64, X86::GR64RegisterClass); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); // We don't accept any truncstore of integer registers. - setTruncStoreAction(MVT::i64, MVT::i32, Expand); - setTruncStoreAction(MVT::i64, MVT::i16, Expand); - setTruncStoreAction(MVT::i64, MVT::i8 , Expand); - setTruncStoreAction(MVT::i32, MVT::i16, Expand); - setTruncStoreAction(MVT::i32, MVT::i8 , Expand); - setTruncStoreAction(MVT::i16, MVT::i8, Expand); + setTruncStoreAction(EVT::i64, EVT::i32, Expand); + setTruncStoreAction(EVT::i64, EVT::i16, Expand); + setTruncStoreAction(EVT::i64, EVT::i8 , Expand); + setTruncStoreAction(EVT::i32, EVT::i16, Expand); + setTruncStoreAction(EVT::i32, EVT::i8 , Expand); + setTruncStoreAction(EVT::i16, EVT::i8, Expand); // SETOEQ and SETUNE require checking two conditions. - setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); - setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); - setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); - setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); - setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); - setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); + setCondCodeAction(ISD::SETOEQ, EVT::f32, Expand); + setCondCodeAction(ISD::SETOEQ, EVT::f64, Expand); + setCondCodeAction(ISD::SETOEQ, EVT::f80, Expand); + setCondCodeAction(ISD::SETUNE, EVT::f32, Expand); + setCondCodeAction(ISD::SETUNE, EVT::f64, Expand); + setCondCodeAction(ISD::SETUNE, EVT::f80, Expand); // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this // operation. - setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); + setOperationAction(ISD::UINT_TO_FP , EVT::i1 , Promote); + setOperationAction(ISD::UINT_TO_FP , EVT::i8 , Promote); + setOperationAction(ISD::UINT_TO_FP , EVT::i16 , Promote); if (Subtarget->is64Bit()) { - setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); - setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); + setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Promote); + setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Expand); } else if (!UseSoftFloat) { if (X86ScalarSSEf64) { // We have an impenetrably clever algorithm for ui64->double only. - setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); + setOperationAction(ISD::UINT_TO_FP , EVT::i64 , Custom); } // We have an algorithm for SSE2, and we turn this into a 64-bit // FILD for other targets. - setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); + setOperationAction(ISD::UINT_TO_FP , EVT::i32 , Custom); } // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have // this operation. - setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); - setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); + setOperationAction(ISD::SINT_TO_FP , EVT::i1 , Promote); + setOperationAction(ISD::SINT_TO_FP , EVT::i8 , Promote); if (!UseSoftFloat) { // SSE has no i16 to fp conversion, only i32 if (X86ScalarSSEf32) { - setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); + setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote); // f32 and f64 cases are Legal, f80 case is not - setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); + setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom); } else { - setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); - setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); + setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Custom); + setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Custom); } } else { - setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); - setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); + setOperationAction(ISD::SINT_TO_FP , EVT::i16 , Promote); + setOperationAction(ISD::SINT_TO_FP , EVT::i32 , Promote); } // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 // are Legal, f80 is custom lowered. - setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); - setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); + setOperationAction(ISD::FP_TO_SINT , EVT::i64 , Custom); + setOperationAction(ISD::SINT_TO_FP , EVT::i64 , Custom); // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have // this operation. - setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); - setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); + setOperationAction(ISD::FP_TO_SINT , EVT::i1 , Promote); + setOperationAction(ISD::FP_TO_SINT , EVT::i8 , Promote); if (X86ScalarSSEf32) { - setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); + setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Promote); // f32 and f64 cases are Legal, f80 case is not - setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); + setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom); } else { - setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); - setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); + setOperationAction(ISD::FP_TO_SINT , EVT::i16 , Custom); + setOperationAction(ISD::FP_TO_SINT , EVT::i32 , Custom); } // Handle FP_TO_UINT by promoting the destination to a larger signed // conversion. - setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); - setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); - setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); + setOperationAction(ISD::FP_TO_UINT , EVT::i1 , Promote); + setOperationAction(ISD::FP_TO_UINT , EVT::i8 , Promote); + setOperationAction(ISD::FP_TO_UINT , EVT::i16 , Promote); if (Subtarget->is64Bit()) { - setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); - setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); + setOperationAction(ISD::FP_TO_UINT , EVT::i64 , Expand); + setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Promote); } else if (!UseSoftFloat) { if (X86ScalarSSEf32 && !Subtarget->hasSSE3()) // Expand FP_TO_UINT into a select. // FIXME: We would like to use a Custom expander here eventually to do // the optimal thing for SSE vs. the default expansion in the legalizer. - setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); + setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Expand); else // With SSE3 we can use fisttpll to convert to a signed i64; without // SSE, we're stuck with a fistpll. - setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); + setOperationAction(ISD::FP_TO_UINT , EVT::i32 , Custom); } // TODO: when we have SSE, these could be more efficient, by using movd/movq. if (!X86ScalarSSEf64) { - setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand); - setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand); + setOperationAction(ISD::BIT_CONVERT , EVT::f32 , Expand); + setOperationAction(ISD::BIT_CONVERT , EVT::i32 , Expand); } // Scalar integer divide and remainder are lowered to use operations that @@ -217,150 +217,150 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // (low) operations are left as Legal, as there are single-result // instructions for this in x86. Using the two-result multiply instructions // when both high and low results are needed must be arranged by dagcombine. - setOperationAction(ISD::MULHS , MVT::i8 , Expand); - setOperationAction(ISD::MULHU , MVT::i8 , Expand); - setOperationAction(ISD::SDIV , MVT::i8 , Expand); - setOperationAction(ISD::UDIV , MVT::i8 , Expand); - setOperationAction(ISD::SREM , MVT::i8 , Expand); - setOperationAction(ISD::UREM , MVT::i8 , Expand); - setOperationAction(ISD::MULHS , MVT::i16 , Expand); - setOperationAction(ISD::MULHU , MVT::i16 , Expand); - setOperationAction(ISD::SDIV , MVT::i16 , Expand); - setOperationAction(ISD::UDIV , MVT::i16 , Expand); - setOperationAction(ISD::SREM , MVT::i16 , Expand); - setOperationAction(ISD::UREM , MVT::i16 , Expand); - setOperationAction(ISD::MULHS , MVT::i32 , Expand); - setOperationAction(ISD::MULHU , MVT::i32 , Expand); - setOperationAction(ISD::SDIV , MVT::i32 , Expand); - setOperationAction(ISD::UDIV , MVT::i32 , Expand); - setOperationAction(ISD::SREM , MVT::i32 , Expand); - setOperationAction(ISD::UREM , MVT::i32 , Expand); - setOperationAction(ISD::MULHS , MVT::i64 , Expand); - setOperationAction(ISD::MULHU , MVT::i64 , Expand); - setOperationAction(ISD::SDIV , MVT::i64 , Expand); - setOperationAction(ISD::UDIV , MVT::i64 , Expand); - setOperationAction(ISD::SREM , MVT::i64 , Expand); - setOperationAction(ISD::UREM , MVT::i64 , Expand); - - setOperationAction(ISD::BR_JT , MVT::Other, Expand); - setOperationAction(ISD::BRCOND , MVT::Other, Custom); - setOperationAction(ISD::BR_CC , MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); + setOperationAction(ISD::MULHS , EVT::i8 , Expand); + setOperationAction(ISD::MULHU , EVT::i8 , Expand); + setOperationAction(ISD::SDIV , EVT::i8 , Expand); + setOperationAction(ISD::UDIV , EVT::i8 , Expand); + setOperationAction(ISD::SREM , EVT::i8 , Expand); + setOperationAction(ISD::UREM , EVT::i8 , Expand); + setOperationAction(ISD::MULHS , EVT::i16 , Expand); + setOperationAction(ISD::MULHU , EVT::i16 , Expand); + setOperationAction(ISD::SDIV , EVT::i16 , Expand); + setOperationAction(ISD::UDIV , EVT::i16 , Expand); + setOperationAction(ISD::SREM , EVT::i16 , Expand); + setOperationAction(ISD::UREM , EVT::i16 , Expand); + setOperationAction(ISD::MULHS , EVT::i32 , Expand); + setOperationAction(ISD::MULHU , EVT::i32 , Expand); + setOperationAction(ISD::SDIV , EVT::i32 , Expand); + setOperationAction(ISD::UDIV , EVT::i32 , Expand); + setOperationAction(ISD::SREM , EVT::i32 , Expand); + setOperationAction(ISD::UREM , EVT::i32 , Expand); + setOperationAction(ISD::MULHS , EVT::i64 , Expand); + setOperationAction(ISD::MULHU , EVT::i64 , Expand); + setOperationAction(ISD::SDIV , EVT::i64 , Expand); + setOperationAction(ISD::UDIV , EVT::i64 , Expand); + setOperationAction(ISD::SREM , EVT::i64 , Expand); + setOperationAction(ISD::UREM , EVT::i64 , Expand); + + setOperationAction(ISD::BR_JT , EVT::Other, Expand); + setOperationAction(ISD::BRCOND , EVT::Other, Custom); + setOperationAction(ISD::BR_CC , EVT::Other, Expand); + setOperationAction(ISD::SELECT_CC , EVT::Other, Expand); if (Subtarget->is64Bit()) - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); - setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); - setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); - setOperationAction(ISD::FREM , MVT::f32 , Expand); - setOperationAction(ISD::FREM , MVT::f64 , Expand); - setOperationAction(ISD::FREM , MVT::f80 , Expand); - setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); - - setOperationAction(ISD::CTPOP , MVT::i8 , Expand); - setOperationAction(ISD::CTTZ , MVT::i8 , Custom); - setOperationAction(ISD::CTLZ , MVT::i8 , Custom); - setOperationAction(ISD::CTPOP , MVT::i16 , Expand); - setOperationAction(ISD::CTTZ , MVT::i16 , Custom); - setOperationAction(ISD::CTLZ , MVT::i16 , Custom); - setOperationAction(ISD::CTPOP , MVT::i32 , Expand); - setOperationAction(ISD::CTTZ , MVT::i32 , Custom); - setOperationAction(ISD::CTLZ , MVT::i32 , Custom); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i32, Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i16 , Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i8 , Legal); + setOperationAction(ISD::SIGN_EXTEND_INREG, EVT::i1 , Expand); + setOperationAction(ISD::FP_ROUND_INREG , EVT::f32 , Expand); + setOperationAction(ISD::FREM , EVT::f32 , Expand); + setOperationAction(ISD::FREM , EVT::f64 , Expand); + setOperationAction(ISD::FREM , EVT::f80 , Expand); + setOperationAction(ISD::FLT_ROUNDS_ , EVT::i32 , Custom); + + setOperationAction(ISD::CTPOP , EVT::i8 , Expand); + setOperationAction(ISD::CTTZ , EVT::i8 , Custom); + setOperationAction(ISD::CTLZ , EVT::i8 , Custom); + setOperationAction(ISD::CTPOP , EVT::i16 , Expand); + setOperationAction(ISD::CTTZ , EVT::i16 , Custom); + setOperationAction(ISD::CTLZ , EVT::i16 , Custom); + setOperationAction(ISD::CTPOP , EVT::i32 , Expand); + setOperationAction(ISD::CTTZ , EVT::i32 , Custom); + setOperationAction(ISD::CTLZ , EVT::i32 , Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::CTPOP , MVT::i64 , Expand); - setOperationAction(ISD::CTTZ , MVT::i64 , Custom); - setOperationAction(ISD::CTLZ , MVT::i64 , Custom); + setOperationAction(ISD::CTPOP , EVT::i64 , Expand); + setOperationAction(ISD::CTTZ , EVT::i64 , Custom); + setOperationAction(ISD::CTLZ , EVT::i64 , Custom); } - setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); - setOperationAction(ISD::BSWAP , MVT::i16 , Expand); + setOperationAction(ISD::READCYCLECOUNTER , EVT::i64 , Custom); + setOperationAction(ISD::BSWAP , EVT::i16 , Expand); // These should be promoted to a larger select which is supported. - setOperationAction(ISD::SELECT , MVT::i1 , Promote); - setOperationAction(ISD::SELECT , MVT::i8 , Promote); + setOperationAction(ISD::SELECT , EVT::i1 , Promote); + setOperationAction(ISD::SELECT , EVT::i8 , Promote); // X86 wants to expand cmov itself. - setOperationAction(ISD::SELECT , MVT::i16 , Custom); - setOperationAction(ISD::SELECT , MVT::i32 , Custom); - setOperationAction(ISD::SELECT , MVT::f32 , Custom); - setOperationAction(ISD::SELECT , MVT::f64 , Custom); - setOperationAction(ISD::SELECT , MVT::f80 , Custom); - setOperationAction(ISD::SETCC , MVT::i8 , Custom); - setOperationAction(ISD::SETCC , MVT::i16 , Custom); - setOperationAction(ISD::SETCC , MVT::i32 , Custom); - setOperationAction(ISD::SETCC , MVT::f32 , Custom); - setOperationAction(ISD::SETCC , MVT::f64 , Custom); - setOperationAction(ISD::SETCC , MVT::f80 , Custom); + setOperationAction(ISD::SELECT , EVT::i16 , Custom); + setOperationAction(ISD::SELECT , EVT::i32 , Custom); + setOperationAction(ISD::SELECT , EVT::f32 , Custom); + setOperationAction(ISD::SELECT , EVT::f64 , Custom); + setOperationAction(ISD::SELECT , EVT::f80 , Custom); + setOperationAction(ISD::SETCC , EVT::i8 , Custom); + setOperationAction(ISD::SETCC , EVT::i16 , Custom); + setOperationAction(ISD::SETCC , EVT::i32 , Custom); + setOperationAction(ISD::SETCC , EVT::f32 , Custom); + setOperationAction(ISD::SETCC , EVT::f64 , Custom); + setOperationAction(ISD::SETCC , EVT::f80 , Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::SELECT , MVT::i64 , Custom); - setOperationAction(ISD::SETCC , MVT::i64 , Custom); + setOperationAction(ISD::SELECT , EVT::i64 , Custom); + setOperationAction(ISD::SETCC , EVT::i64 , Custom); } - setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); + setOperationAction(ISD::EH_RETURN , EVT::Other, Custom); // Darwin ABI issue. - setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); - setOperationAction(ISD::JumpTable , MVT::i32 , Custom); - setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); - setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); + setOperationAction(ISD::ConstantPool , EVT::i32 , Custom); + setOperationAction(ISD::JumpTable , EVT::i32 , Custom); + setOperationAction(ISD::GlobalAddress , EVT::i32 , Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32 , Custom); if (Subtarget->is64Bit()) - setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); - setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i64, Custom); + setOperationAction(ISD::ExternalSymbol , EVT::i32 , Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); - setOperationAction(ISD::JumpTable , MVT::i64 , Custom); - setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); - setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); + setOperationAction(ISD::ConstantPool , EVT::i64 , Custom); + setOperationAction(ISD::JumpTable , EVT::i64 , Custom); + setOperationAction(ISD::GlobalAddress , EVT::i64 , Custom); + setOperationAction(ISD::ExternalSymbol, EVT::i64 , Custom); } // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) - setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); - setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); - setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); + setOperationAction(ISD::SHL_PARTS , EVT::i32 , Custom); + setOperationAction(ISD::SRA_PARTS , EVT::i32 , Custom); + setOperationAction(ISD::SRL_PARTS , EVT::i32 , Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); - setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); - setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); + setOperationAction(ISD::SHL_PARTS , EVT::i64 , Custom); + setOperationAction(ISD::SRA_PARTS , EVT::i64 , Custom); + setOperationAction(ISD::SRL_PARTS , EVT::i64 , Custom); } if (Subtarget->hasSSE1()) - setOperationAction(ISD::PREFETCH , MVT::Other, Legal); + setOperationAction(ISD::PREFETCH , EVT::Other, Legal); if (!Subtarget->hasSSE2()) - setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand); + setOperationAction(ISD::MEMBARRIER , EVT::Other, Expand); // Expand certain atomics - setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom); - setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i16, Custom); - setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom); - setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i8, Custom); + setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i16, Custom); + setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i32, Custom); + setOperationAction(ISD::ATOMIC_CMP_SWAP, EVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i8, Custom); - setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i16, Custom); - setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom); - setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i8, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i16, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i32, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom); if (!Subtarget->is64Bit()) { - setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); - setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_ADD, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_SUB, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_AND, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_OR, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_XOR, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_LOAD_NAND, EVT::i64, Custom); + setOperationAction(ISD::ATOMIC_SWAP, EVT::i64, Custom); } // Use the default ISD::DBG_STOPPOINT, ISD::DECLARE expansion. - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); // FIXME - use subtarget debug flags if (!Subtarget->isTargetDarwin() && !Subtarget->isTargetELF() && !Subtarget->isTargetCygMing()) { - setOperationAction(ISD::DBG_LABEL, MVT::Other, Expand); - setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); + setOperationAction(ISD::DBG_LABEL, EVT::Other, Expand); + setOperationAction(ISD::EH_LABEL, EVT::Other, Expand); } - setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); - setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); - setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); - setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); + setOperationAction(ISD::EXCEPTIONADDR, EVT::i64, Expand); + setOperationAction(ISD::EHSELECTION, EVT::i64, Expand); + setOperationAction(ISD::EXCEPTIONADDR, EVT::i32, Expand); + setOperationAction(ISD::EHSELECTION, EVT::i32, Expand); if (Subtarget->is64Bit()) { setExceptionPointerRegister(X86::RAX); setExceptionSelectorRegister(X86::RDX); @@ -368,56 +368,56 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setExceptionPointerRegister(X86::EAX); setExceptionSelectorRegister(X86::EDX); } - setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); - setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); + setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i32, Custom); + setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, EVT::i64, Custom); - setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom); + setOperationAction(ISD::TRAMPOLINE, EVT::Other, Custom); - setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::TRAP, EVT::Other, Legal); // VASTART needs to be custom lowered to use the VarArgsFrameIndex - setOperationAction(ISD::VASTART , MVT::Other, Custom); - setOperationAction(ISD::VAEND , MVT::Other, Expand); + setOperationAction(ISD::VASTART , EVT::Other, Custom); + setOperationAction(ISD::VAEND , EVT::Other, Expand); if (Subtarget->is64Bit()) { - setOperationAction(ISD::VAARG , MVT::Other, Custom); - setOperationAction(ISD::VACOPY , MVT::Other, Custom); + setOperationAction(ISD::VAARG , EVT::Other, Custom); + setOperationAction(ISD::VACOPY , EVT::Other, Custom); } else { - setOperationAction(ISD::VAARG , MVT::Other, Expand); - setOperationAction(ISD::VACOPY , MVT::Other, Expand); + setOperationAction(ISD::VAARG , EVT::Other, Expand); + setOperationAction(ISD::VACOPY , EVT::Other, Expand); } - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); if (Subtarget->is64Bit()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i64, Expand); if (Subtarget->isTargetCygMing()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Custom); else - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand); if (!UseSoftFloat && X86ScalarSSEf64) { // f32 and f64 use SSE. // Set up the FP register classes. - addRegisterClass(MVT::f32, X86::FR32RegisterClass); - addRegisterClass(MVT::f64, X86::FR64RegisterClass); + addRegisterClass(EVT::f32, X86::FR32RegisterClass); + addRegisterClass(EVT::f64, X86::FR64RegisterClass); // Use ANDPD to simulate FABS. - setOperationAction(ISD::FABS , MVT::f64, Custom); - setOperationAction(ISD::FABS , MVT::f32, Custom); + setOperationAction(ISD::FABS , EVT::f64, Custom); + setOperationAction(ISD::FABS , EVT::f32, Custom); // Use XORP to simulate FNEG. - setOperationAction(ISD::FNEG , MVT::f64, Custom); - setOperationAction(ISD::FNEG , MVT::f32, Custom); + setOperationAction(ISD::FNEG , EVT::f64, Custom); + setOperationAction(ISD::FNEG , EVT::f32, Custom); // Use ANDPD and ORPD to simulate FCOPYSIGN. - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Custom); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom); // We don't support sin/cos/fmod - setOperationAction(ISD::FSIN , MVT::f64, Expand); - setOperationAction(ISD::FCOS , MVT::f64, Expand); - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSIN , EVT::f64, Expand); + setOperationAction(ISD::FCOS , EVT::f64, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); // Expand FP immediates into loads from the stack, except for the special // cases we handle. @@ -426,24 +426,24 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } else if (!UseSoftFloat && X86ScalarSSEf32) { // Use SSE for f32, x87 for f64. // Set up the FP register classes. - addRegisterClass(MVT::f32, X86::FR32RegisterClass); - addRegisterClass(MVT::f64, X86::RFP64RegisterClass); + addRegisterClass(EVT::f32, X86::FR32RegisterClass); + addRegisterClass(EVT::f64, X86::RFP64RegisterClass); // Use ANDPS to simulate FABS. - setOperationAction(ISD::FABS , MVT::f32, Custom); + setOperationAction(ISD::FABS , EVT::f32, Custom); // Use XORP to simulate FNEG. - setOperationAction(ISD::FNEG , MVT::f32, Custom); + setOperationAction(ISD::FNEG , EVT::f32, Custom); - setOperationAction(ISD::UNDEF, MVT::f64, Expand); + setOperationAction(ISD::UNDEF, EVT::f64, Expand); // Use ANDPS and ORPS to simulate FCOPYSIGN. - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Custom); // We don't support sin/cos/fmod - setOperationAction(ISD::FSIN , MVT::f32, Expand); - setOperationAction(ISD::FCOS , MVT::f32, Expand); + setOperationAction(ISD::FSIN , EVT::f32, Expand); + setOperationAction(ISD::FCOS , EVT::f32, Expand); // Special cases we handle for FP constants. addLegalFPImmediate(APFloat(+0.0f)); // xorps @@ -453,23 +453,23 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS if (!UnsafeFPMath) { - setOperationAction(ISD::FSIN , MVT::f64 , Expand); - setOperationAction(ISD::FCOS , MVT::f64 , Expand); + setOperationAction(ISD::FSIN , EVT::f64 , Expand); + setOperationAction(ISD::FCOS , EVT::f64 , Expand); } } else if (!UseSoftFloat) { // f32 and f64 in x87. // Set up the FP register classes. - addRegisterClass(MVT::f64, X86::RFP64RegisterClass); - addRegisterClass(MVT::f32, X86::RFP32RegisterClass); + addRegisterClass(EVT::f64, X86::RFP64RegisterClass); + addRegisterClass(EVT::f32, X86::RFP32RegisterClass); - setOperationAction(ISD::UNDEF, MVT::f64, Expand); - setOperationAction(ISD::UNDEF, MVT::f32, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); + setOperationAction(ISD::UNDEF, EVT::f64, Expand); + setOperationAction(ISD::UNDEF, EVT::f32, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f64, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f32, Expand); if (!UnsafeFPMath) { - setOperationAction(ISD::FSIN , MVT::f64 , Expand); - setOperationAction(ISD::FCOS , MVT::f64 , Expand); + setOperationAction(ISD::FSIN , EVT::f64 , Expand); + setOperationAction(ISD::FCOS , EVT::f64 , Expand); } addLegalFPImmediate(APFloat(+0.0)); // FLD0 addLegalFPImmediate(APFloat(+1.0)); // FLD1 @@ -483,9 +483,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // Long double always uses X87. if (!UseSoftFloat) { - addRegisterClass(MVT::f80, X86::RFP80RegisterClass); - setOperationAction(ISD::UNDEF, MVT::f80, Expand); - setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); + addRegisterClass(EVT::f80, X86::RFP80RegisterClass); + setOperationAction(ISD::UNDEF, EVT::f80, Expand); + setOperationAction(ISD::FCOPYSIGN, EVT::f80, Expand); { bool ignored; APFloat TmpFlt(+0.0); @@ -503,220 +503,220 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } if (!UnsafeFPMath) { - setOperationAction(ISD::FSIN , MVT::f80 , Expand); - setOperationAction(ISD::FCOS , MVT::f80 , Expand); + setOperationAction(ISD::FSIN , EVT::f80 , Expand); + setOperationAction(ISD::FCOS , EVT::f80 , Expand); } } // Always use a library call for pow. - setOperationAction(ISD::FPOW , MVT::f32 , Expand); - setOperationAction(ISD::FPOW , MVT::f64 , Expand); - setOperationAction(ISD::FPOW , MVT::f80 , Expand); + setOperationAction(ISD::FPOW , EVT::f32 , Expand); + setOperationAction(ISD::FPOW , EVT::f64 , Expand); + setOperationAction(ISD::FPOW , EVT::f80 , Expand); - setOperationAction(ISD::FLOG, MVT::f80, Expand); - setOperationAction(ISD::FLOG2, MVT::f80, Expand); - setOperationAction(ISD::FLOG10, MVT::f80, Expand); - setOperationAction(ISD::FEXP, MVT::f80, Expand); - setOperationAction(ISD::FEXP2, MVT::f80, Expand); + setOperationAction(ISD::FLOG, EVT::f80, Expand); + setOperationAction(ISD::FLOG2, EVT::f80, Expand); + setOperationAction(ISD::FLOG10, EVT::f80, Expand); + setOperationAction(ISD::FEXP, EVT::f80, Expand); + setOperationAction(ISD::FEXP2, EVT::f80, Expand); // First set operation action for all vector types to either promote // (for widening) or expand (for scalarization). Then we will selectively // turn on ones that can be effectively codegen'd. - for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; - VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { - setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); - setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); - setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::VSETCC, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); - setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); + for (unsigned VT = (unsigned)EVT::FIRST_VECTOR_VALUETYPE; + VT <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++VT) { + setOperationAction(ISD::ADD , (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SUB , (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FADD, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FNEG, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSUB, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::MUL , (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FMUL, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SDIV, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UDIV, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FDIV, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SREM, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UREM, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::LOAD, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::VECTOR_SHUFFLE, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::EXTRACT_VECTOR_ELT,(EVT::SimpleValueType)VT,Expand); + setOperationAction(ISD::EXTRACT_SUBVECTOR,(EVT::SimpleValueType)VT,Expand); + setOperationAction(ISD::INSERT_VECTOR_ELT,(EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FABS, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSIN, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FCOS, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FREM, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FPOWI, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FSQRT, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FCOPYSIGN, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SMUL_LOHI, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UMUL_LOHI, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SDIVREM, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UDIVREM, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FPOW, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTPOP, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTTZ, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::CTLZ, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SHL, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SRA, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SRL, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::ROTL, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::ROTR, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::BSWAP, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::VSETCC, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FLOG, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FLOG2, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FLOG10, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FEXP, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FEXP2, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FP_TO_UINT, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::FP_TO_SINT, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::UINT_TO_FP, (EVT::SimpleValueType)VT, Expand); + setOperationAction(ISD::SINT_TO_FP, (EVT::SimpleValueType)VT, Expand); } // FIXME: In order to prevent SSE instructions being expanded to MMX ones // with -msoft-float, disable use of MMX as well. if (!UseSoftFloat && !DisableMMX && Subtarget->hasMMX()) { - addRegisterClass(MVT::v8i8, X86::VR64RegisterClass); - addRegisterClass(MVT::v4i16, X86::VR64RegisterClass); - addRegisterClass(MVT::v2i32, X86::VR64RegisterClass); - addRegisterClass(MVT::v2f32, X86::VR64RegisterClass); - addRegisterClass(MVT::v1i64, X86::VR64RegisterClass); - - setOperationAction(ISD::ADD, MVT::v8i8, Legal); - setOperationAction(ISD::ADD, MVT::v4i16, Legal); - setOperationAction(ISD::ADD, MVT::v2i32, Legal); - setOperationAction(ISD::ADD, MVT::v1i64, Legal); - - setOperationAction(ISD::SUB, MVT::v8i8, Legal); - setOperationAction(ISD::SUB, MVT::v4i16, Legal); - setOperationAction(ISD::SUB, MVT::v2i32, Legal); - setOperationAction(ISD::SUB, MVT::v1i64, Legal); - - setOperationAction(ISD::MULHS, MVT::v4i16, Legal); - setOperationAction(ISD::MUL, MVT::v4i16, Legal); - - setOperationAction(ISD::AND, MVT::v8i8, Promote); - AddPromotedToType (ISD::AND, MVT::v8i8, MVT::v1i64); - setOperationAction(ISD::AND, MVT::v4i16, Promote); - AddPromotedToType (ISD::AND, MVT::v4i16, MVT::v1i64); - setOperationAction(ISD::AND, MVT::v2i32, Promote); - AddPromotedToType (ISD::AND, MVT::v2i32, MVT::v1i64); - setOperationAction(ISD::AND, MVT::v1i64, Legal); - - setOperationAction(ISD::OR, MVT::v8i8, Promote); - AddPromotedToType (ISD::OR, MVT::v8i8, MVT::v1i64); - setOperationAction(ISD::OR, MVT::v4i16, Promote); - AddPromotedToType (ISD::OR, MVT::v4i16, MVT::v1i64); - setOperationAction(ISD::OR, MVT::v2i32, Promote); - AddPromotedToType (ISD::OR, MVT::v2i32, MVT::v1i64); - setOperationAction(ISD::OR, MVT::v1i64, Legal); - - setOperationAction(ISD::XOR, MVT::v8i8, Promote); - AddPromotedToType (ISD::XOR, MVT::v8i8, MVT::v1i64); - setOperationAction(ISD::XOR, MVT::v4i16, Promote); - AddPromotedToType (ISD::XOR, MVT::v4i16, MVT::v1i64); - setOperationAction(ISD::XOR, MVT::v2i32, Promote); - AddPromotedToType (ISD::XOR, MVT::v2i32, MVT::v1i64); - setOperationAction(ISD::XOR, MVT::v1i64, Legal); - - setOperationAction(ISD::LOAD, MVT::v8i8, Promote); - AddPromotedToType (ISD::LOAD, MVT::v8i8, MVT::v1i64); - setOperationAction(ISD::LOAD, MVT::v4i16, Promote); - AddPromotedToType (ISD::LOAD, MVT::v4i16, MVT::v1i64); - setOperationAction(ISD::LOAD, MVT::v2i32, Promote); - AddPromotedToType (ISD::LOAD, MVT::v2i32, MVT::v1i64); - setOperationAction(ISD::LOAD, MVT::v2f32, Promote); - AddPromotedToType (ISD::LOAD, MVT::v2f32, MVT::v1i64); - setOperationAction(ISD::LOAD, MVT::v1i64, Legal); - - setOperationAction(ISD::BUILD_VECTOR, MVT::v8i8, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2i32, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2f32, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v1i64, Custom); - - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i8, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i32, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v1i64, Custom); - - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f32, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Custom); - - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); - - setTruncStoreAction(MVT::v8i16, MVT::v8i8, Expand); - setOperationAction(ISD::TRUNCATE, MVT::v8i8, Expand); - setOperationAction(ISD::SELECT, MVT::v8i8, Promote); - setOperationAction(ISD::SELECT, MVT::v4i16, Promote); - setOperationAction(ISD::SELECT, MVT::v2i32, Promote); - setOperationAction(ISD::SELECT, MVT::v1i64, Custom); - setOperationAction(ISD::VSETCC, MVT::v8i8, Custom); - setOperationAction(ISD::VSETCC, MVT::v4i16, Custom); - setOperationAction(ISD::VSETCC, MVT::v2i32, Custom); + addRegisterClass(EVT::v8i8, X86::VR64RegisterClass); + addRegisterClass(EVT::v4i16, X86::VR64RegisterClass); + addRegisterClass(EVT::v2i32, X86::VR64RegisterClass); + addRegisterClass(EVT::v2f32, X86::VR64RegisterClass); + addRegisterClass(EVT::v1i64, X86::VR64RegisterClass); + + setOperationAction(ISD::ADD, EVT::v8i8, Legal); + setOperationAction(ISD::ADD, EVT::v4i16, Legal); + setOperationAction(ISD::ADD, EVT::v2i32, Legal); + setOperationAction(ISD::ADD, EVT::v1i64, Legal); + + setOperationAction(ISD::SUB, EVT::v8i8, Legal); + setOperationAction(ISD::SUB, EVT::v4i16, Legal); + setOperationAction(ISD::SUB, EVT::v2i32, Legal); + setOperationAction(ISD::SUB, EVT::v1i64, Legal); + + setOperationAction(ISD::MULHS, EVT::v4i16, Legal); + setOperationAction(ISD::MUL, EVT::v4i16, Legal); + + setOperationAction(ISD::AND, EVT::v8i8, Promote); + AddPromotedToType (ISD::AND, EVT::v8i8, EVT::v1i64); + setOperationAction(ISD::AND, EVT::v4i16, Promote); + AddPromotedToType (ISD::AND, EVT::v4i16, EVT::v1i64); + setOperationAction(ISD::AND, EVT::v2i32, Promote); + AddPromotedToType (ISD::AND, EVT::v2i32, EVT::v1i64); + setOperationAction(ISD::AND, EVT::v1i64, Legal); + + setOperationAction(ISD::OR, EVT::v8i8, Promote); + AddPromotedToType (ISD::OR, EVT::v8i8, EVT::v1i64); + setOperationAction(ISD::OR, EVT::v4i16, Promote); + AddPromotedToType (ISD::OR, EVT::v4i16, EVT::v1i64); + setOperationAction(ISD::OR, EVT::v2i32, Promote); + AddPromotedToType (ISD::OR, EVT::v2i32, EVT::v1i64); + setOperationAction(ISD::OR, EVT::v1i64, Legal); + + setOperationAction(ISD::XOR, EVT::v8i8, Promote); + AddPromotedToType (ISD::XOR, EVT::v8i8, EVT::v1i64); + setOperationAction(ISD::XOR, EVT::v4i16, Promote); + AddPromotedToType (ISD::XOR, EVT::v4i16, EVT::v1i64); + setOperationAction(ISD::XOR, EVT::v2i32, Promote); + AddPromotedToType (ISD::XOR, EVT::v2i32, EVT::v1i64); + setOperationAction(ISD::XOR, EVT::v1i64, Legal); + + setOperationAction(ISD::LOAD, EVT::v8i8, Promote); + AddPromotedToType (ISD::LOAD, EVT::v8i8, EVT::v1i64); + setOperationAction(ISD::LOAD, EVT::v4i16, Promote); + AddPromotedToType (ISD::LOAD, EVT::v4i16, EVT::v1i64); + setOperationAction(ISD::LOAD, EVT::v2i32, Promote); + AddPromotedToType (ISD::LOAD, EVT::v2i32, EVT::v1i64); + setOperationAction(ISD::LOAD, EVT::v2f32, Promote); + AddPromotedToType (ISD::LOAD, EVT::v2f32, EVT::v1i64); + setOperationAction(ISD::LOAD, EVT::v1i64, Legal); + + setOperationAction(ISD::BUILD_VECTOR, EVT::v8i8, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v4i16, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v2i32, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v2f32, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v1i64, Custom); + + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8i8, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i16, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i32, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v1i64, Custom); + + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v2f32, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i8, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v4i16, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v1i64, Custom); + + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i16, Custom); + + setTruncStoreAction(EVT::v8i16, EVT::v8i8, Expand); + setOperationAction(ISD::TRUNCATE, EVT::v8i8, Expand); + setOperationAction(ISD::SELECT, EVT::v8i8, Promote); + setOperationAction(ISD::SELECT, EVT::v4i16, Promote); + setOperationAction(ISD::SELECT, EVT::v2i32, Promote); + setOperationAction(ISD::SELECT, EVT::v1i64, Custom); + setOperationAction(ISD::VSETCC, EVT::v8i8, Custom); + setOperationAction(ISD::VSETCC, EVT::v4i16, Custom); + setOperationAction(ISD::VSETCC, EVT::v2i32, Custom); } if (!UseSoftFloat && Subtarget->hasSSE1()) { - addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); - - setOperationAction(ISD::FADD, MVT::v4f32, Legal); - setOperationAction(ISD::FSUB, MVT::v4f32, Legal); - setOperationAction(ISD::FMUL, MVT::v4f32, Legal); - setOperationAction(ISD::FDIV, MVT::v4f32, Legal); - setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); - setOperationAction(ISD::FNEG, MVT::v4f32, Custom); - setOperationAction(ISD::LOAD, MVT::v4f32, Legal); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); - setOperationAction(ISD::SELECT, MVT::v4f32, Custom); - setOperationAction(ISD::VSETCC, MVT::v4f32, Custom); + addRegisterClass(EVT::v4f32, X86::VR128RegisterClass); + + setOperationAction(ISD::FADD, EVT::v4f32, Legal); + setOperationAction(ISD::FSUB, EVT::v4f32, Legal); + setOperationAction(ISD::FMUL, EVT::v4f32, Legal); + setOperationAction(ISD::FDIV, EVT::v4f32, Legal); + setOperationAction(ISD::FSQRT, EVT::v4f32, Legal); + setOperationAction(ISD::FNEG, EVT::v4f32, Custom); + setOperationAction(ISD::LOAD, EVT::v4f32, Legal); + setOperationAction(ISD::BUILD_VECTOR, EVT::v4f32, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f32, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom); + setOperationAction(ISD::SELECT, EVT::v4f32, Custom); + setOperationAction(ISD::VSETCC, EVT::v4f32, Custom); } if (!UseSoftFloat && Subtarget->hasSSE2()) { - addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); + addRegisterClass(EVT::v2f64, X86::VR128RegisterClass); // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM // registers cannot be used even for integer operations. - addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); - addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); - addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); - addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); - - setOperationAction(ISD::ADD, MVT::v16i8, Legal); - setOperationAction(ISD::ADD, MVT::v8i16, Legal); - setOperationAction(ISD::ADD, MVT::v4i32, Legal); - setOperationAction(ISD::ADD, MVT::v2i64, Legal); - setOperationAction(ISD::MUL, MVT::v2i64, Custom); - setOperationAction(ISD::SUB, MVT::v16i8, Legal); - setOperationAction(ISD::SUB, MVT::v8i16, Legal); - setOperationAction(ISD::SUB, MVT::v4i32, Legal); - setOperationAction(ISD::SUB, MVT::v2i64, Legal); - setOperationAction(ISD::MUL, MVT::v8i16, Legal); - setOperationAction(ISD::FADD, MVT::v2f64, Legal); - setOperationAction(ISD::FSUB, MVT::v2f64, Legal); - setOperationAction(ISD::FMUL, MVT::v2f64, Legal); - setOperationAction(ISD::FDIV, MVT::v2f64, Legal); - setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); - setOperationAction(ISD::FNEG, MVT::v2f64, Custom); - - setOperationAction(ISD::VSETCC, MVT::v2f64, Custom); - setOperationAction(ISD::VSETCC, MVT::v16i8, Custom); - setOperationAction(ISD::VSETCC, MVT::v8i16, Custom); - setOperationAction(ISD::VSETCC, MVT::v4i32, Custom); - - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); + addRegisterClass(EVT::v16i8, X86::VR128RegisterClass); + addRegisterClass(EVT::v8i16, X86::VR128RegisterClass); + addRegisterClass(EVT::v4i32, X86::VR128RegisterClass); + addRegisterClass(EVT::v2i64, X86::VR128RegisterClass); + + setOperationAction(ISD::ADD, EVT::v16i8, Legal); + setOperationAction(ISD::ADD, EVT::v8i16, Legal); + setOperationAction(ISD::ADD, EVT::v4i32, Legal); + setOperationAction(ISD::ADD, EVT::v2i64, Legal); + setOperationAction(ISD::MUL, EVT::v2i64, Custom); + setOperationAction(ISD::SUB, EVT::v16i8, Legal); + setOperationAction(ISD::SUB, EVT::v8i16, Legal); + setOperationAction(ISD::SUB, EVT::v4i32, Legal); + setOperationAction(ISD::SUB, EVT::v2i64, Legal); + setOperationAction(ISD::MUL, EVT::v8i16, Legal); + setOperationAction(ISD::FADD, EVT::v2f64, Legal); + setOperationAction(ISD::FSUB, EVT::v2f64, Legal); + setOperationAction(ISD::FMUL, EVT::v2f64, Legal); + setOperationAction(ISD::FDIV, EVT::v2f64, Legal); + setOperationAction(ISD::FSQRT, EVT::v2f64, Legal); + setOperationAction(ISD::FNEG, EVT::v2f64, Custom); + + setOperationAction(ISD::VSETCC, EVT::v2f64, Custom); + setOperationAction(ISD::VSETCC, EVT::v16i8, Custom); + setOperationAction(ISD::VSETCC, EVT::v8i16, Custom); + setOperationAction(ISD::VSETCC, EVT::v4i32, Custom); + + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i8, Custom); + setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v8i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom); // Custom lower build_vector, vector_shuffle, and extract_vector_elt. - for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { - MVT VT = (MVT::SimpleValueType)i; + for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; ++i) { + EVT VT = (EVT::SimpleValueType)i; // Do not attempt to custom lower non-power-of-2 vectors if (!isPowerOf2_32(VT.getVectorNumElements())) continue; @@ -728,138 +728,138 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT.getSimpleVT(), Custom); } - setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v2f64, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v2i64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2f64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v2i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2f64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2f64, Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Custom); } // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. - for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { - MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; - MVT VT = SVT; + for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v2i64; i++) { + EVT::SimpleValueType SVT = (EVT::SimpleValueType)i; + EVT VT = SVT; // Do not attempt to promote non-128-bit vectors if (!VT.is128BitVector()) { continue; } setOperationAction(ISD::AND, SVT, Promote); - AddPromotedToType (ISD::AND, SVT, MVT::v2i64); + AddPromotedToType (ISD::AND, SVT, EVT::v2i64); setOperationAction(ISD::OR, SVT, Promote); - AddPromotedToType (ISD::OR, SVT, MVT::v2i64); + AddPromotedToType (ISD::OR, SVT, EVT::v2i64); setOperationAction(ISD::XOR, SVT, Promote); - AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); + AddPromotedToType (ISD::XOR, SVT, EVT::v2i64); setOperationAction(ISD::LOAD, SVT, Promote); - AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); + AddPromotedToType (ISD::LOAD, SVT, EVT::v2i64); setOperationAction(ISD::SELECT, SVT, Promote); - AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); + AddPromotedToType (ISD::SELECT, SVT, EVT::v2i64); } - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); // Custom lower v2i64 and v2f64 selects. - setOperationAction(ISD::LOAD, MVT::v2f64, Legal); - setOperationAction(ISD::LOAD, MVT::v2i64, Legal); - setOperationAction(ISD::SELECT, MVT::v2f64, Custom); - setOperationAction(ISD::SELECT, MVT::v2i64, Custom); + setOperationAction(ISD::LOAD, EVT::v2f64, Legal); + setOperationAction(ISD::LOAD, EVT::v2i64, Legal); + setOperationAction(ISD::SELECT, EVT::v2f64, Custom); + setOperationAction(ISD::SELECT, EVT::v2i64, Custom); - setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); - setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); + setOperationAction(ISD::FP_TO_SINT, EVT::v4i32, Legal); + setOperationAction(ISD::SINT_TO_FP, EVT::v4i32, Legal); if (!DisableMMX && Subtarget->hasMMX()) { - setOperationAction(ISD::FP_TO_SINT, MVT::v2i32, Custom); - setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); + setOperationAction(ISD::FP_TO_SINT, EVT::v2i32, Custom); + setOperationAction(ISD::SINT_TO_FP, EVT::v2i32, Custom); } } if (Subtarget->hasSSE41()) { // FIXME: Do we need to handle scalar-to-vector here? - setOperationAction(ISD::MUL, MVT::v4i32, Legal); + setOperationAction(ISD::MUL, EVT::v4i32, Legal); // i8 and i16 vectors are custom , because the source register and source // source memory operand types are not the same width. f32 vectors are // custom since the immediate controlling the insert encodes additional // information. - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i8, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i32, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f32, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v16i8, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8i16, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i32, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f32, Custom); if (Subtarget->is64Bit()) { - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v2i64, Legal); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v2i64, Legal); } } if (Subtarget->hasSSE42()) { - setOperationAction(ISD::VSETCC, MVT::v2i64, Custom); + setOperationAction(ISD::VSETCC, EVT::v2i64, Custom); } if (!UseSoftFloat && Subtarget->hasAVX()) { - addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); - addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); - addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); - addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); - - setOperationAction(ISD::LOAD, MVT::v8f32, Legal); - setOperationAction(ISD::LOAD, MVT::v8i32, Legal); - setOperationAction(ISD::LOAD, MVT::v4f64, Legal); - setOperationAction(ISD::LOAD, MVT::v4i64, Legal); - setOperationAction(ISD::FADD, MVT::v8f32, Legal); - setOperationAction(ISD::FSUB, MVT::v8f32, Legal); - setOperationAction(ISD::FMUL, MVT::v8f32, Legal); - setOperationAction(ISD::FDIV, MVT::v8f32, Legal); - setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); - setOperationAction(ISD::FNEG, MVT::v8f32, Custom); - //setOperationAction(ISD::BUILD_VECTOR, MVT::v8f32, Custom); - //setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Custom); - //setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8f32, Custom); - //setOperationAction(ISD::SELECT, MVT::v8f32, Custom); - //setOperationAction(ISD::VSETCC, MVT::v8f32, Custom); + addRegisterClass(EVT::v8f32, X86::VR256RegisterClass); + addRegisterClass(EVT::v4f64, X86::VR256RegisterClass); + addRegisterClass(EVT::v8i32, X86::VR256RegisterClass); + addRegisterClass(EVT::v4i64, X86::VR256RegisterClass); + + setOperationAction(ISD::LOAD, EVT::v8f32, Legal); + setOperationAction(ISD::LOAD, EVT::v8i32, Legal); + setOperationAction(ISD::LOAD, EVT::v4f64, Legal); + setOperationAction(ISD::LOAD, EVT::v4i64, Legal); + setOperationAction(ISD::FADD, EVT::v8f32, Legal); + setOperationAction(ISD::FSUB, EVT::v8f32, Legal); + setOperationAction(ISD::FMUL, EVT::v8f32, Legal); + setOperationAction(ISD::FDIV, EVT::v8f32, Legal); + setOperationAction(ISD::FSQRT, EVT::v8f32, Legal); + setOperationAction(ISD::FNEG, EVT::v8f32, Custom); + //setOperationAction(ISD::BUILD_VECTOR, EVT::v8f32, Custom); + //setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v8f32, Custom); + //setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v8f32, Custom); + //setOperationAction(ISD::SELECT, EVT::v8f32, Custom); + //setOperationAction(ISD::VSETCC, EVT::v8f32, Custom); // Operations to consider commented out -v16i16 v32i8 - //setOperationAction(ISD::ADD, MVT::v16i16, Legal); - setOperationAction(ISD::ADD, MVT::v8i32, Custom); - setOperationAction(ISD::ADD, MVT::v4i64, Custom); - //setOperationAction(ISD::SUB, MVT::v32i8, Legal); - //setOperationAction(ISD::SUB, MVT::v16i16, Legal); - setOperationAction(ISD::SUB, MVT::v8i32, Custom); - setOperationAction(ISD::SUB, MVT::v4i64, Custom); - //setOperationAction(ISD::MUL, MVT::v16i16, Legal); - setOperationAction(ISD::FADD, MVT::v4f64, Legal); - setOperationAction(ISD::FSUB, MVT::v4f64, Legal); - setOperationAction(ISD::FMUL, MVT::v4f64, Legal); - setOperationAction(ISD::FDIV, MVT::v4f64, Legal); - setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); - setOperationAction(ISD::FNEG, MVT::v4f64, Custom); - - setOperationAction(ISD::VSETCC, MVT::v4f64, Custom); - // setOperationAction(ISD::VSETCC, MVT::v32i8, Custom); - // setOperationAction(ISD::VSETCC, MVT::v16i16, Custom); - setOperationAction(ISD::VSETCC, MVT::v8i32, Custom); - - // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v32i8, Custom); - // setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i16, Custom); - // setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i16, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i32, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8f32, Custom); - - setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom); - setOperationAction(ISD::BUILD_VECTOR, MVT::v4i64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f64, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i64, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f64, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f64, Custom); + //setOperationAction(ISD::ADD, EVT::v16i16, Legal); + setOperationAction(ISD::ADD, EVT::v8i32, Custom); + setOperationAction(ISD::ADD, EVT::v4i64, Custom); + //setOperationAction(ISD::SUB, EVT::v32i8, Legal); + //setOperationAction(ISD::SUB, EVT::v16i16, Legal); + setOperationAction(ISD::SUB, EVT::v8i32, Custom); + setOperationAction(ISD::SUB, EVT::v4i64, Custom); + //setOperationAction(ISD::MUL, EVT::v16i16, Legal); + setOperationAction(ISD::FADD, EVT::v4f64, Legal); + setOperationAction(ISD::FSUB, EVT::v4f64, Legal); + setOperationAction(ISD::FMUL, EVT::v4f64, Legal); + setOperationAction(ISD::FDIV, EVT::v4f64, Legal); + setOperationAction(ISD::FSQRT, EVT::v4f64, Legal); + setOperationAction(ISD::FNEG, EVT::v4f64, Custom); + + setOperationAction(ISD::VSETCC, EVT::v4f64, Custom); + // setOperationAction(ISD::VSETCC, EVT::v32i8, Custom); + // setOperationAction(ISD::VSETCC, EVT::v16i16, Custom); + setOperationAction(ISD::VSETCC, EVT::v8i32, Custom); + + // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v32i8, Custom); + // setOperationAction(ISD::SCALAR_TO_VECTOR, EVT::v16i16, Custom); + // setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v16i16, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8i32, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v8f32, Custom); + + setOperationAction(ISD::BUILD_VECTOR, EVT::v4f64, Custom); + setOperationAction(ISD::BUILD_VECTOR, EVT::v4i64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4f64, Custom); + setOperationAction(ISD::VECTOR_SHUFFLE, EVT::v4i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4f64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4f64, Custom); #if 0 // Not sure we want to do this since there are no 256-bit integer @@ -867,8 +867,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // Custom lower build_vector, vector_shuffle, and extract_vector_elt. // This includes 256-bit vectors - for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; ++i) { - MVT VT = (MVT::SimpleValueType)i; + for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; ++i) { + EVT VT = (EVT::SimpleValueType)i; // Do not attempt to custom lower non-power-of-2 vectors if (!isPowerOf2_32(VT.getVectorNumElements())) @@ -880,8 +880,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } if (Subtarget->is64Bit()) { - setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i64, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i64, Custom); + setOperationAction(ISD::INSERT_VECTOR_ELT, EVT::v4i64, Custom); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, EVT::v4i64, Custom); } #endif @@ -891,42 +891,42 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // Promote v32i8, v16i16, v8i32 load, select, and, or, xor to v4i64. // Including 256-bit vectors - for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v4i64; i++) { - MVT VT = (MVT::SimpleValueType)i; + for (unsigned i = (unsigned)EVT::v16i8; i != (unsigned)EVT::v4i64; i++) { + EVT VT = (EVT::SimpleValueType)i; if (!VT.is256BitVector()) { continue; } setOperationAction(ISD::AND, VT, Promote); - AddPromotedToType (ISD::AND, VT, MVT::v4i64); + AddPromotedToType (ISD::AND, VT, EVT::v4i64); setOperationAction(ISD::OR, VT, Promote); - AddPromotedToType (ISD::OR, VT, MVT::v4i64); + AddPromotedToType (ISD::OR, VT, EVT::v4i64); setOperationAction(ISD::XOR, VT, Promote); - AddPromotedToType (ISD::XOR, VT, MVT::v4i64); + AddPromotedToType (ISD::XOR, VT, EVT::v4i64); setOperationAction(ISD::LOAD, VT, Promote); - AddPromotedToType (ISD::LOAD, VT, MVT::v4i64); + AddPromotedToType (ISD::LOAD, VT, EVT::v4i64); setOperationAction(ISD::SELECT, VT, Promote); - AddPromotedToType (ISD::SELECT, VT, MVT::v4i64); + AddPromotedToType (ISD::SELECT, VT, EVT::v4i64); } - setTruncStoreAction(MVT::f64, MVT::f32, Expand); + setTruncStoreAction(EVT::f64, EVT::f32, Expand); #endif } // We want to custom lower some of our intrinsics. - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); + setOperationAction(ISD::INTRINSIC_WO_CHAIN, EVT::Other, Custom); // Add/Sub/Mul with overflow operations are custom lowered. - setOperationAction(ISD::SADDO, MVT::i32, Custom); - setOperationAction(ISD::SADDO, MVT::i64, Custom); - setOperationAction(ISD::UADDO, MVT::i32, Custom); - setOperationAction(ISD::UADDO, MVT::i64, Custom); - setOperationAction(ISD::SSUBO, MVT::i32, Custom); - setOperationAction(ISD::SSUBO, MVT::i64, Custom); - setOperationAction(ISD::USUBO, MVT::i32, Custom); - setOperationAction(ISD::USUBO, MVT::i64, Custom); - setOperationAction(ISD::SMULO, MVT::i32, Custom); - setOperationAction(ISD::SMULO, MVT::i64, Custom); + setOperationAction(ISD::SADDO, EVT::i32, Custom); + setOperationAction(ISD::SADDO, EVT::i64, Custom); + setOperationAction(ISD::UADDO, EVT::i32, Custom); + setOperationAction(ISD::UADDO, EVT::i64, Custom); + setOperationAction(ISD::SSUBO, EVT::i32, Custom); + setOperationAction(ISD::SSUBO, EVT::i64, Custom); + setOperationAction(ISD::USUBO, EVT::i32, Custom); + setOperationAction(ISD::USUBO, EVT::i64, Custom); + setOperationAction(ISD::SMULO, EVT::i32, Custom); + setOperationAction(ISD::SMULO, EVT::i64, Custom); if (!Subtarget->is64Bit()) { // These libcalls are not available in 32-bit. @@ -960,8 +960,8 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) } -MVT::SimpleValueType X86TargetLowering::getSetCCResultType(MVT VT) const { - return MVT::i8; +EVT::SimpleValueType X86TargetLowering::getSetCCResultType(EVT VT) const { + return EVT::i8; } @@ -1012,9 +1012,9 @@ unsigned X86TargetLowering::getByValTypeAlignment(const Type *Ty) const { /// getOptimalMemOpType - Returns the target specific optimal type for load /// and store operations as a result of memset, memcpy, and memmove -/// lowering. It returns MVT::iAny if SelectionDAG should be responsible for +/// lowering. It returns EVT::iAny if SelectionDAG should be responsible for /// determining it. -MVT +EVT X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr, SelectionDAG &DAG) const { @@ -1025,13 +1025,13 @@ X86TargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align, bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); if (!NoImplicitFloatOps && Subtarget->getStackAlignment() >= 16) { if ((isSrcConst || isSrcStr) && Subtarget->hasSSE2() && Size >= 16) - return MVT::v4i32; + return EVT::v4i32; if ((isSrcConst || isSrcStr) && Subtarget->hasSSE1() && Size >= 16) - return MVT::v4f32; + return EVT::v4f32; } if (Subtarget->is64Bit() && Size >= 8) - return MVT::i64; - return MVT::i32; + return EVT::i64; + return EVT::i32; } /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC @@ -1083,7 +1083,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, SmallVector<SDValue, 6> RetOps; RetOps.push_back(Chain); // Operand #0 = Chain (updated below) // Operand #1 = Bytes To Pop - RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), MVT::i16)); + RetOps.push_back(DAG.getConstant(getBytesToPopOnReturn(), EVT::i16)); // Copy the result values into the output registers. for (unsigned i = 0; i != RVLocs.size(); ++i) { @@ -1098,7 +1098,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, // If this is a copy from an xmm register to ST(0), use an FPExtend to // change the value to the FP stack register class. if (isScalarFPTypeInSSEReg(VA.getValVT())) - ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); + ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, EVT::f80, ValToCopy); RetOps.push_back(ValToCopy); // Don't emit a copytoreg. continue; @@ -1107,11 +1107,11 @@ X86TargetLowering::LowerReturn(SDValue Chain, // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 // which is returned in RAX / RDX. if (Subtarget->is64Bit()) { - MVT ValVT = ValToCopy.getValueType(); + EVT ValVT = ValToCopy.getValueType(); if (ValVT.isVector() && ValVT.getSizeInBits() == 64) { - ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, ValToCopy); + ValToCopy = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, ValToCopy); if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) - ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, ValToCopy); + ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, ValToCopy); } } @@ -1129,7 +1129,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); unsigned Reg = FuncInfo->getSRetReturnReg(); if (!Reg) { - Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64)); FuncInfo->setSRetReturnReg(Reg); } SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); @@ -1145,7 +1145,7 @@ X86TargetLowering::LowerReturn(SDValue Chain, RetOps.push_back(Flag); return DAG.getNode(X86ISD::RET_FLAG, dl, - MVT::Other, &RetOps[0], RetOps.size()); + EVT::Other, &RetOps[0], RetOps.size()); } /// LowerCallResult - Lower the result values of a call into the @@ -1168,10 +1168,10 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, // Copy all of the result registers out of their specified physreg. for (unsigned i = 0; i != RVLocs.size(); ++i) { CCValAssign &VA = RVLocs[i]; - MVT CopyVT = VA.getValVT(); + EVT CopyVT = VA.getValVT(); // If this is x86-64, and we disabled SSE, we can't return FP values - if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && + if ((CopyVT == EVT::f32 || CopyVT == EVT::f64) && ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { llvm_report_error("SSE register return with SSE disabled"); } @@ -1182,7 +1182,7 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, if ((VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) && isScalarFPTypeInSSEReg(VA.getValVT())) { - CopyVT = MVT::f80; + CopyVT = EVT::f80; } SDValue Val; @@ -1190,13 +1190,13 @@ X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), - MVT::v2i64, InFlag).getValue(1); + EVT::v2i64, InFlag).getValue(1); Val = Chain.getValue(0); - Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, - Val, DAG.getConstant(0, MVT::i64)); + Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64, + Val, DAG.getConstant(0, EVT::i64)); } else { Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), - MVT::i64, InFlag).getValue(1); + EVT::i64, InFlag).getValue(1); Val = Chain.getValue(0); } Val = DAG.getNode(ISD::BIT_CONVERT, dl, CopyVT, Val); @@ -1307,7 +1307,7 @@ static SDValue CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, ISD::ArgFlagsTy Flags, SelectionDAG &DAG, DebugLoc dl) { - SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), EVT::i32); return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), /*AlwaysInline=*/true, NULL, 0, NULL, 0); } @@ -1384,15 +1384,15 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, LastVal = VA.getValNo(); if (VA.isRegLoc()) { - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); TargetRegisterClass *RC = NULL; - if (RegVT == MVT::i32) + if (RegVT == EVT::i32) RC = X86::GR32RegisterClass; - else if (Is64Bit && RegVT == MVT::i64) + else if (Is64Bit && RegVT == EVT::i64) RC = X86::GR64RegisterClass; - else if (RegVT == MVT::f32) + else if (RegVT == EVT::f32) RC = X86::FR32RegisterClass; - else if (RegVT == MVT::f64) + else if (RegVT == EVT::f64) RC = X86::FR64RegisterClass; else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) RC = X86::VR128RegisterClass; @@ -1419,8 +1419,8 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, if (VA.isExtInLoc()) { // Handle MMX values passed in XMM regs. if (RegVT.isVector()) { - ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, - ArgValue, DAG.getConstant(0, MVT::i64)); + ArgValue = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i64, + ArgValue, DAG.getConstant(0, EVT::i64)); ArgValue = DAG.getNode(ISD::BIT_CONVERT, dl, VA.getValVT(), ArgValue); } else ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); @@ -1444,11 +1444,11 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); unsigned Reg = FuncInfo->getSRetReturnReg(); if (!Reg) { - Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); + Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(EVT::i64)); FuncInfo->setSRetReturnReg(Reg); } SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Copy, Chain); } unsigned StackSize = CCInfo.getNextStackOffset(); @@ -1521,7 +1521,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], X86::GR64RegisterClass); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i64); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); @@ -1536,7 +1536,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { unsigned VReg = MF.addLiveIn(XMMArgRegs[NumXMMRegs], X86::VR128RegisterClass); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::v4f32); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, PseudoSourceValue::getFixedStack(RegSaveFrameIndex), 0); @@ -1545,7 +1545,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, DAG.getIntPtrConstant(16)); } if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOps[0], MemOps.size()); } } @@ -1603,7 +1603,7 @@ X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, if (!IsTailCall || FPDiff==0) return Chain; // Adjust the Return address stack slot. - MVT VT = getPointerTy(); + EVT VT = getPointerTy(); OutRetAddr = getReturnAddressFrameIndex(DAG); // Load the "old" Return address. @@ -1623,7 +1623,7 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, int SlotSize = Is64Bit ? 8 : 4; int NewReturnAddrFI = MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize); - MVT VT = Is64Bit ? MVT::i64 : MVT::i32; + EVT VT = Is64Bit ? EVT::i64 : EVT::i32; SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, PseudoSourceValue::getFixedStack(NewReturnAddrFI), 0); @@ -1687,7 +1687,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, // of tail call optimization arguments are handle later. for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { CCValAssign &VA = ArgLocs[i]; - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); SDValue Arg = Outs[i].Val; ISD::ArgFlagsTy Flags = Outs[i].Flags; bool isByVal = Flags.isByVal(); @@ -1705,9 +1705,9 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, case CCValAssign::AExt: if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { // Special case: passing MMX values in XMM registers. - Arg = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i64, Arg); - Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); - Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); + Arg = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i64, Arg); + Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i64, Arg); + Arg = getMOVL(DAG, dl, EVT::v2i64, DAG.getUNDEF(EVT::v2i64), Arg); } else Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); break; @@ -1740,7 +1740,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, } if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token chain @@ -1805,7 +1805,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, && "SSE registers cannot be used when SSE is disabled"); Chain = DAG.getCopyToReg(Chain, dl, X86::AL, - DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); + DAG.getConstant(NumXMMRegs, EVT::i8), InFlag); InFlag = Chain.getValue(1); } @@ -1858,7 +1858,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, } if (!MemOpChains2.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains2[0], MemOpChains2.size()); // Copy arguments to their registers. @@ -1933,7 +1933,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, } // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; if (isTailCall) { @@ -1946,7 +1946,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, Ops.push_back(Callee); if (isTailCall) - Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); + Ops.push_back(DAG.getConstant(FPDiff, EVT::i32)); // Add argument registers to the end of the list so that they are known live // into the call. @@ -1960,7 +1960,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, // Add an implicit use of AL for x86 vararg functions. if (Is64Bit && isVarArg) - Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); + Ops.push_back(DAG.getRegister(X86::AL, EVT::i8)); if (InFlag.getNode()) Ops.push_back(InFlag); @@ -2277,10 +2277,10 @@ static bool isUndefOrEqual(int Val, int CmpVal) { /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference /// the second operand. -static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, MVT VT) { - if (VT == MVT::v4f32 || VT == MVT::v4i32 || VT == MVT::v4i16) +static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { + if (VT == EVT::v4f32 || VT == EVT::v4i32 || VT == EVT::v4i16) return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); - if (VT == MVT::v2f64 || VT == MVT::v2i64) + if (VT == EVT::v2f64 || VT == EVT::v2i64) return (Mask[0] < 2 && Mask[1] < 2); return false; } @@ -2293,8 +2293,8 @@ bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that /// is suitable for input to PSHUFHW. -static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, MVT VT) { - if (VT != MVT::v8i16) +static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { + if (VT != EVT::v8i16) return false; // Lower quadword copied in order or undef. @@ -2318,8 +2318,8 @@ bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that /// is suitable for input to PSHUFLW. -static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, MVT VT) { - if (VT != MVT::v8i16) +static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { + if (VT != EVT::v8i16) return false; // Upper quadword copied in order. @@ -2343,7 +2343,7 @@ bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to SHUFP*. -static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) { +static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { int NumElems = VT.getVectorNumElements(); if (NumElems != 2 && NumElems != 4) return false; @@ -2369,7 +2369,7 @@ bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { /// the reverse of what x86 shuffles want. x86 shuffles requires the lower /// half elements to come from vector 1 (which would equal the dest.) and /// the upper half to come from vector 2. -static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, MVT VT) { +static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { int NumElems = VT.getVectorNumElements(); if (NumElems != 2 && NumElems != 4) @@ -2460,7 +2460,7 @@ bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to UNPCKL. -static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, MVT VT, +static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, bool V2IsSplat = false) { int NumElts = VT.getVectorNumElements(); if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) @@ -2490,7 +2490,7 @@ bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to UNPCKH. -static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, MVT VT, +static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, bool V2IsSplat = false) { int NumElts = VT.getVectorNumElements(); if (NumElts != 2 && NumElts != 4 && NumElts != 8 && NumElts != 16) @@ -2521,7 +2521,7 @@ bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, /// <0, 0, 1, 1> -static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) { +static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { int NumElems = VT.getVectorNumElements(); if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) return false; @@ -2546,7 +2546,7 @@ bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, /// <2, 2, 3, 3> -static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, MVT VT) { +static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { int NumElems = VT.getVectorNumElements(); if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) return false; @@ -2571,7 +2571,7 @@ bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand /// specifies a shuffle of elements that is suitable for input to MOVSS, /// MOVSD, and MOVD, i.e. setting the lowest element. -static bool isMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT) { +static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { if (VT.getVectorElementType().getSizeInBits() < 32) return false; @@ -2596,7 +2596,7 @@ bool X86::isMOVLMask(ShuffleVectorSDNode *N) { /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse /// of what x86 movss want. X86 movs requires the lowest element to be lowest /// element of vector 2 and the other elements to come from vector 1 in order. -static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, MVT VT, +static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, bool V2IsSplat = false, bool V2IsUndef = false) { int NumOps = VT.getVectorNumElements(); if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) @@ -2751,7 +2751,7 @@ bool X86::isZeroNode(SDValue Elt) { /// their permute mask. static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { - MVT VT = SVOp->getValueType(0); + EVT VT = SVOp->getValueType(0); unsigned NumElems = VT.getVectorNumElements(); SmallVector<int, 8> MaskVec; @@ -2770,7 +2770,7 @@ static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming /// the two vector operands have swapped position. -static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, MVT VT) { +static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { unsigned NumElems = VT.getVectorNumElements(); for (unsigned i = 0; i != NumElems; ++i) { int idx = Mask[i]; @@ -2883,7 +2883,7 @@ static bool isZeroShuffle(ShuffleVectorSDNode *N) { /// getZeroVector - Returns a vector of specified type with all zero elements. /// -static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG, +static SDValue getZeroVector(EVT VT, bool HasSSE2, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); @@ -2891,31 +2891,31 @@ static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG, // type. This ensures they get CSE'd. SDValue Vec; if (VT.getSizeInBits() == 64) { // MMX - SDValue Cst = DAG.getTargetConstant(0, MVT::i32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + SDValue Cst = DAG.getTargetConstant(0, EVT::i32); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst); } else if (HasSSE2) { // SSE2 - SDValue Cst = DAG.getTargetConstant(0, MVT::i32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + SDValue Cst = DAG.getTargetConstant(0, EVT::i32); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst); } else { // SSE1 - SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); + SDValue Cst = DAG.getTargetConstantFP(+0.0, EVT::f32); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4f32, Cst, Cst, Cst, Cst); } return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } /// getOnesVector - Returns a vector of specified type with all bits set. /// -static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { +static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { assert(VT.isVector() && "Expected a vector type"); // Always build ones vectors as <4 x i32> or <2 x i32> bitcasted to their dest // type. This ensures they get CSE'd. - SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); + SDValue Cst = DAG.getTargetConstant(~0U, EVT::i32); SDValue Vec; if (VT.getSizeInBits() == 64) // MMX - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v2i32, Cst, Cst); else // SSE - Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); + Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32, Cst, Cst, Cst, Cst); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec); } @@ -2923,7 +2923,7 @@ static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) { /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements /// that point to V2 points to its first element. static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { - MVT VT = SVOp->getValueType(0); + EVT VT = SVOp->getValueType(0); unsigned NumElems = VT.getVectorNumElements(); bool Changed = false; @@ -2944,7 +2944,7 @@ static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd /// operation of specified width. -static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, +static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) { unsigned NumElems = VT.getVectorNumElements(); SmallVector<int, 8> Mask; @@ -2955,7 +2955,7 @@ static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, } /// getUnpackl - Returns a vector_shuffle node for an unpackl operation. -static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, +static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) { unsigned NumElems = VT.getVectorNumElements(); SmallVector<int, 8> Mask; @@ -2967,7 +2967,7 @@ static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, } /// getUnpackhMask - Returns a vector_shuffle node for an unpackh operation. -static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, MVT VT, SDValue V1, +static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, SDValue V2) { unsigned NumElems = VT.getVectorNumElements(); unsigned Half = NumElems/2; @@ -2985,8 +2985,8 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, if (SV->getValueType(0).getVectorNumElements() <= 4) return SDValue(SV, 0); - MVT PVT = MVT::v4f32; - MVT VT = SV->getValueType(0); + EVT PVT = EVT::v4f32; + EVT VT = SV->getValueType(0); DebugLoc dl = SV->getDebugLoc(); SDValue V1 = SV->getOperand(0); int NumElems = VT.getVectorNumElements(); @@ -3017,7 +3017,7 @@ static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG, static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, bool isZero, bool HasSSE2, SelectionDAG &DAG) { - MVT VT = V2.getValueType(); + EVT VT = V2.getValueType(); SDValue V1 = isZero ? getZeroVector(VT, HasSSE2, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); unsigned NumElems = VT.getVectorNumElements(); @@ -3105,9 +3105,9 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; if (ThisIsNonZero && First) { if (NumZero) - V = getZeroVector(MVT::v8i16, true, DAG, dl); + V = getZeroVector(EVT::v8i16, true, DAG, dl); else - V = DAG.getUNDEF(MVT::v8i16); + V = DAG.getUNDEF(EVT::v8i16); First = false; } @@ -3116,24 +3116,24 @@ static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; if (LastIsNonZero) { LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, - MVT::i16, Op.getOperand(i-1)); + EVT::i16, Op.getOperand(i-1)); } if (ThisIsNonZero) { - ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); - ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, - ThisElt, DAG.getConstant(8, MVT::i8)); + ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i16, Op.getOperand(i)); + ThisElt = DAG.getNode(ISD::SHL, dl, EVT::i16, + ThisElt, DAG.getConstant(8, EVT::i8)); if (LastIsNonZero) - ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); + ThisElt = DAG.getNode(ISD::OR, dl, EVT::i16, ThisElt, LastElt); } else ThisElt = LastElt; if (ThisElt.getNode()) - V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, + V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, V, ThisElt, DAG.getIntPtrConstant(i/2)); } } - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V); } /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. @@ -3152,13 +3152,13 @@ static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, if (isNonZero) { if (First) { if (NumZero) - V = getZeroVector(MVT::v8i16, true, DAG, dl); + V = getZeroVector(EVT::v8i16, true, DAG, dl); else - V = DAG.getUNDEF(MVT::v8i16); + V = DAG.getUNDEF(EVT::v8i16); First = false; } V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, - MVT::v8i16, V, Op.getOperand(i), + EVT::v8i16, V, Op.getOperand(i), DAG.getIntPtrConstant(i)); } } @@ -3168,11 +3168,11 @@ static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, /// getVShift - Return a vector logical shift node. /// -static SDValue getVShift(bool isLeft, MVT VT, SDValue SrcOp, +static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, unsigned NumBits, SelectionDAG &DAG, const TargetLowering &TLI, DebugLoc dl) { bool isMMX = VT.getSizeInBits() == 64; - MVT ShVT = isMMX ? MVT::v1i64 : MVT::v2i64; + EVT ShVT = isMMX ? EVT::v1i64 : EVT::v2i64; unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; SrcOp = DAG.getNode(ISD::BIT_CONVERT, dl, ShVT, SrcOp); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, @@ -3189,7 +3189,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // Canonicalize this to either <4 x i32> or <2 x i32> (SSE vs MMX) to // 1) ensure the zero vectors are CSE'd, and 2) ensure that i64 scalars are // eliminated on x86-32 hosts. - if (Op.getValueType() == MVT::v4i32 || Op.getValueType() == MVT::v2i32) + if (Op.getValueType() == EVT::v4i32 || Op.getValueType() == EVT::v2i32) return Op; if (ISD::isBuildVectorAllOnes(Op.getNode())) @@ -3197,9 +3197,9 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { return getZeroVector(Op.getValueType(), Subtarget->hasSSE2(), DAG, dl); } - MVT VT = Op.getValueType(); - MVT EVT = VT.getVectorElementType(); - unsigned EVTBits = EVT.getSizeInBits(); + EVT VT = Op.getValueType(); + EVT ExtVT = VT.getVectorElementType(); + unsigned EVTBits = ExtVT.getSizeInBits(); unsigned NumElems = Op.getNumOperands(); unsigned NumZero = 0; @@ -3238,16 +3238,16 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { // insertion that way. Only do this if the value is non-constant or if the // value is a constant being inserted into element 0. It is cheaper to do // a constant pool load than it is to do a movd + shuffle. - if (EVT == MVT::i64 && !Subtarget->is64Bit() && + if (ExtVT == EVT::i64 && !Subtarget->is64Bit() && (!IsAllConstants || Idx == 0)) { if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { // Handle MMX and SSE both. - MVT VecVT = VT == MVT::v2i64 ? MVT::v4i32 : MVT::v2i32; - unsigned VecElts = VT == MVT::v2i64 ? 4 : 2; + EVT VecVT = VT == EVT::v2i64 ? EVT::v4i32 : EVT::v2i32; + unsigned VecElts = VT == EVT::v2i64 ? 4 : 2; // Truncate the value (which may itself be a constant) to i32, and // convert it to a vector with movd (S2V+shuffle to zero extend). - Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); + Item = DAG.getNode(ISD::TRUNCATE, dl, EVT::i32, Item); Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), DAG); @@ -3274,15 +3274,15 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) { if (Idx == 0) { if (NumZero == 0) { return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); - } else if (EVT == MVT::i32 || EVT == MVT::f32 || EVT == MVT::f64 || - (EVT == MVT::i64 && Subtarget->is64Bit())) { + } else if (ExtVT == EVT::i32 || ExtVT == EVT::f32 || ExtVT == EVT::f64 || + (ExtVT == EVT::i64 && Subtarget->is64Bit())) { Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. return getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), DAG); - } else if (EVT == MVT::i16 || EVT == MVT::i8) { - Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); - MVT MiddleVT = VT.getSizeInBits() == 64 ? MVT::v2i32 : MVT::v4i32; + } else if (ExtVT == EVT::i16 || ExtVT == EVT::i8) { + Item = DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Item); + EVT MiddleVT = VT.getSizeInBits() == 64 ? EVT::v2i32 : EVT::v4i32; Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); Item = getShuffleVectorZeroOrUndef(Item, 0, true, Subtarget->hasSSE2(), DAG); @@ -3508,10 +3508,10 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, SmallVector<int, 8> MaskV; MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); - NewV = DAG.getVectorShuffle(MVT::v2i64, dl, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1), - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V2), &MaskV[0]); - NewV = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, NewV); + NewV = DAG.getVectorShuffle(EVT::v2i64, dl, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V1), + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, V2), &MaskV[0]); + NewV = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, NewV); // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the // source words for the shuffle, to aid later transformations. @@ -3548,8 +3548,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, // If we've eliminated the use of V2, and the new mask is a pshuflw or // pshufhw, that's as cheap as it gets. Return the new shuffle. if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { - return DAG.getVectorShuffle(MVT::v8i16, dl, NewV, - DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); + return DAG.getVectorShuffle(EVT::v8i16, dl, NewV, + DAG.getUNDEF(EVT::v8i16), &MaskVals[0]); } } @@ -3567,19 +3567,19 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, for (unsigned i = 0; i != 8; ++i) { int EltIdx = MaskVals[i] * 2; if (TwoInputs && (EltIdx >= 16)) { - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); continue; } - pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); - pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx+1, EVT::i8)); } - V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1); - V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, + V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V1); + V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1, DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::v16i8, &pshufbMask[0], 16)); + EVT::v16i8, &pshufbMask[0], 16)); if (!TwoInputs) - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1); // Calculate the shuffle mask for the second input, shuffle it, and // OR it with the first shuffled input. @@ -3587,19 +3587,19 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, for (unsigned i = 0; i != 8; ++i) { int EltIdx = MaskVals[i] * 2; if (EltIdx < 16) { - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); continue; } - pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); - pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx - 15, EVT::i8)); } - V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2); - V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, + V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, V2); + V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2, DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::v16i8, &pshufbMask[0], 16)); - V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); + EVT::v16i8, &pshufbMask[0], 16)); + V1 = DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1); } // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, @@ -3621,7 +3621,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, } for (unsigned i = 4; i != 8; ++i) MaskV.push_back(i); - NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), + NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16), &MaskV[0]); } @@ -3643,7 +3643,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, MaskV.push_back(-1); } } - NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), + NewV = DAG.getVectorShuffle(EVT::v8i16, dl, NewV, DAG.getUNDEF(EVT::v8i16), &MaskV[0]); } @@ -3665,11 +3665,11 @@ SDValue LowerVECTOR_SHUFFLEv8i16(ShuffleVectorSDNode *SVOp, if (EltIdx < 0) continue; SDValue ExtOp = (EltIdx < 8) - ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, + ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V1, DAG.getIntPtrConstant(EltIdx)) - : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, + : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, V2, DAG.getIntPtrConstant(EltIdx - 8)); - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, ExtOp, DAG.getIntPtrConstant(i)); } return NewV; @@ -3718,18 +3718,18 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, for (unsigned i = 0; i != 16; ++i) { int EltIdx = MaskVals[i]; if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); continue; } - pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx, EVT::i8)); } // If all the elements are from V2, assign it to V1 and return after // building the first pshufb. if (V2Only) V1 = V2; - V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, + V1 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V1, DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::v16i8, &pshufbMask[0], 16)); + EVT::v16i8, &pshufbMask[0], 16)); if (!TwoInputs) return V1; @@ -3739,22 +3739,22 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, for (unsigned i = 0; i != 16; ++i) { int EltIdx = MaskVals[i]; if (EltIdx < 16) { - pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(0x80, EVT::i8)); continue; } - pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); + pshufbMask.push_back(DAG.getConstant(EltIdx - 16, EVT::i8)); } - V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, + V2 = DAG.getNode(X86ISD::PSHUFB, dl, EVT::v16i8, V2, DAG.getNode(ISD::BUILD_VECTOR, dl, - MVT::v16i8, &pshufbMask[0], 16)); - return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); + EVT::v16i8, &pshufbMask[0], 16)); + return DAG.getNode(ISD::OR, dl, EVT::v16i8, V1, V2); } // No SSSE3 - Calculate in place words and then fix all out of place words // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from // the 16 different words that comprise the two doublequadword input vectors. - V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1); - V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V2); + V1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V1); + V2 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v8i16, V2); SDValue NewV = V2Only ? V2 : V1; for (int i = 0; i != 8; ++i) { int Elt0 = MaskVals[i*2]; @@ -3777,9 +3777,9 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, // If Elt0 and Elt1 are defined, are consecutive, and can be load // using a single extract together, load it and store it. if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { - InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, + InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src, DAG.getIntPtrConstant(Elt1 / 2)); - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt, DAG.getIntPtrConstant(i)); continue; } @@ -3788,35 +3788,35 @@ SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, // source byte is not also odd, shift the extracted word left 8 bits // otherwise clear the bottom 8 bits if we need to do an or. if (Elt1 >= 0) { - InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, + InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt1Src, DAG.getIntPtrConstant(Elt1 / 2)); if ((Elt1 & 1) == 0) - InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, + InsElt = DAG.getNode(ISD::SHL, dl, EVT::i16, InsElt, DAG.getConstant(8, TLI.getShiftAmountTy())); else if (Elt0 >= 0) - InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, - DAG.getConstant(0xFF00, MVT::i16)); + InsElt = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt, + DAG.getConstant(0xFF00, EVT::i16)); } // If Elt0 is defined, extract it from the appropriate source. If the // source byte is not also even, shift the extracted word right 8 bits. If // Elt1 was also defined, OR the extracted values together before // inserting them in the result. if (Elt0 >= 0) { - SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, + SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i16, Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); if ((Elt0 & 1) != 0) - InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, + InsElt0 = DAG.getNode(ISD::SRL, dl, EVT::i16, InsElt0, DAG.getConstant(8, TLI.getShiftAmountTy())); else if (Elt1 >= 0) - InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, - DAG.getConstant(0x00FF, MVT::i16)); - InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) + InsElt0 = DAG.getNode(ISD::AND, dl, EVT::i16, InsElt0, + DAG.getConstant(0x00FF, EVT::i16)); + InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, EVT::i16, InsElt, InsElt0) : InsElt0; } - NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, + NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, EVT::v8i16, NewV, InsElt, DAG.getIntPtrConstant(i)); } - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, NewV); + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v16i8, NewV); } /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide @@ -3828,27 +3828,27 @@ static SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, TargetLowering &TLI, DebugLoc dl) { - MVT VT = SVOp->getValueType(0); + EVT VT = SVOp->getValueType(0); SDValue V1 = SVOp->getOperand(0); SDValue V2 = SVOp->getOperand(1); unsigned NumElems = VT.getVectorNumElements(); unsigned NewWidth = (NumElems == 4) ? 2 : 4; - MVT MaskVT = MVT::getIntVectorWithNumElements(NewWidth); - MVT MaskEltVT = MaskVT.getVectorElementType(); - MVT NewVT = MaskVT; + EVT MaskVT = EVT::getIntVectorWithNumElements(NewWidth); + EVT MaskEltVT = MaskVT.getVectorElementType(); + EVT NewVT = MaskVT; switch (VT.getSimpleVT()) { default: assert(false && "Unexpected!"); - case MVT::v4f32: NewVT = MVT::v2f64; break; - case MVT::v4i32: NewVT = MVT::v2i64; break; - case MVT::v8i16: NewVT = MVT::v4i32; break; - case MVT::v16i8: NewVT = MVT::v4i32; break; + case EVT::v4f32: NewVT = EVT::v2f64; break; + case EVT::v4i32: NewVT = EVT::v2i64; break; + case EVT::v8i16: NewVT = EVT::v4i32; break; + case EVT::v16i8: NewVT = EVT::v4i32; break; } if (NewWidth == 2) { if (VT.isInteger()) - NewVT = MVT::v2i64; + NewVT = EVT::v2i64; else - NewVT = MVT::v2f64; + NewVT = EVT::v2f64; } int Scale = NumElems / NewWidth; SmallVector<int, 8> MaskVec; @@ -3876,23 +3876,23 @@ SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, /// getVZextMovL - Return a zero-extending vector move low node. /// -static SDValue getVZextMovL(MVT VT, MVT OpVT, +static SDValue getVZextMovL(EVT VT, EVT OpVT, SDValue SrcOp, SelectionDAG &DAG, const X86Subtarget *Subtarget, DebugLoc dl) { - if (VT == MVT::v2f64 || VT == MVT::v4f32) { + if (VT == EVT::v2f64 || VT == EVT::v4f32) { LoadSDNode *LD = NULL; if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) LD = dyn_cast<LoadSDNode>(SrcOp); if (!LD) { // movssrr and movsdrr do not clear top bits. Try to use movd, movq // instead. - MVT EVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; - if ((EVT != MVT::i64 || Subtarget->is64Bit()) && + EVT EVT = (OpVT == EVT::v2f64) ? EVT::i64 : EVT::i32; + if ((EVT != EVT::i64 || Subtarget->is64Bit()) && SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && SrcOp.getOperand(0).getOpcode() == ISD::BIT_CONVERT && SrcOp.getOperand(0).getOperand(0).getValueType() == EVT) { // PR2108 - OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; + OpVT = (OpVT == EVT::v2f64) ? EVT::v2i64 : EVT::v4i32; return DAG.getNode(ISD::BIT_CONVERT, dl, VT, DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, @@ -3916,7 +3916,7 @@ LowerVECTOR_SHUFFLE_4wide(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { SDValue V1 = SVOp->getOperand(0); SDValue V2 = SVOp->getOperand(1); DebugLoc dl = SVOp->getDebugLoc(); - MVT VT = SVOp->getValueType(0); + EVT VT = SVOp->getValueType(0); SmallVector<std::pair<int, int>, 8> Locs; Locs.resize(4); @@ -4063,7 +4063,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); SDValue V1 = Op.getOperand(0); SDValue V2 = Op.getOperand(1); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); unsigned NumElems = VT.getVectorNumElements(); bool isMMX = VT.getSizeInBits() == 64; @@ -4084,12 +4084,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { // If the shuffle can be profitably rewritten as a narrower shuffle, then // do it! - if (VT == MVT::v8i16 || VT == MVT::v16i8) { + if (VT == EVT::v8i16 || VT == EVT::v16i8) { SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, *this, dl); if (NewOp.getNode()) return DAG.getNode(ISD::BIT_CONVERT, dl, VT, LowerVECTOR_SHUFFLE(NewOp, DAG)); - } else if ((VT == MVT::v4i32 || (VT == MVT::v4f32 && Subtarget->hasSSE2()))) { + } else if ((VT == EVT::v4i32 || (VT == EVT::v4f32 && Subtarget->hasSSE2()))) { // FIXME: Figure out a cleaner way to do this. // Try to make use of movq to zero out the top part. if (ISD::isBuildVectorAllZeros(V2.getNode())) { @@ -4119,7 +4119,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { if (isShift && ShVal.hasOneUse()) { // If the shifted value has multiple uses, it may be cheaper to use // v_set0 + movlhps or movhlps, etc. - MVT EVT = VT.getVectorElementType(); + EVT EVT = VT.getVectorElementType(); ShAmt *= EVT.getSizeInBits(); return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); } @@ -4147,7 +4147,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { if (isShift) { // No better options. Use a vshl / vsrl. - MVT EVT = VT.getVectorElementType(); + EVT EVT = VT.getVectorElementType(); ShAmt *= EVT.getSizeInBits(); return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); } @@ -4225,13 +4225,13 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { return Op; // Handle v8i16 specifically since SSE can do byte extraction and insertion. - if (VT == MVT::v8i16) { + if (VT == EVT::v8i16) { SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(SVOp, DAG, *this); if (NewOp.getNode()) return NewOp; } - if (VT == MVT::v16i8) { + if (VT == EVT::v16i8) { SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); if (NewOp.getNode()) return NewOp; @@ -4247,30 +4247,30 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); if (VT.getSizeInBits() == 8) { - SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, EVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); } else if (VT.getSizeInBits() == 16) { unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); // If Idx is 0, it's cheaper to do a move instead of a pextrw. if (Idx == 0) - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16, + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::v4i32, + EVT::v4i32, Op.getOperand(0)), Op.getOperand(1))); - SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, + SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT::i32, Op.getOperand(0), Op.getOperand(1)); - SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, + SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT::i32, Extract, DAG.getValueType(VT)); return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); - } else if (VT == MVT::f32) { + } else if (VT == EVT::f32) { // EXTRACTPS outputs to a GPR32 register which will require a movd to copy // the result back to FR32 register. It's only worth matching if the // result has a single use which is a store or a bitcast to i32. And in @@ -4283,14 +4283,14 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, (isa<ConstantSDNode>(Op.getOperand(1)) && cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && (User->getOpcode() != ISD::BIT_CONVERT || - User->getValueType(0) != MVT::i32)) + User->getValueType(0) != EVT::i32)) return SDValue(); - SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4i32, + SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4i32, Op.getOperand(0)), Op.getOperand(1)); - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, Extract); - } else if (VT == MVT::i32) { + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, Extract); + } else if (VT == EVT::i32) { // ExtractPS works with constant index. if (isa<ConstantSDNode>(Op.getOperand(1))) return Op; @@ -4310,20 +4310,20 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { return Res; } - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); // TODO: handle v16i8. if (VT.getSizeInBits() == 16) { SDValue Vec = Op.getOperand(0); unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); if (Idx == 0) - return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, - DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, + return DAG.getNode(ISD::TRUNCATE, dl, EVT::i16, + DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::i32, DAG.getNode(ISD::BIT_CONVERT, dl, - MVT::v4i32, Vec), + EVT::v4i32, Vec), Op.getOperand(1))); // Transform it so it match pextrw which produces a 32-bit result. - MVT EVT = (MVT::SimpleValueType)(VT.getSimpleVT()+1); + EVT EVT = (EVT::SimpleValueType)(VT.getSimpleVT()+1); SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EVT, Op.getOperand(0), Op.getOperand(1)); SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EVT, Extract, @@ -4336,7 +4336,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // SHUFPS the element to the lowest double word, then movss. int Mask[4] = { Idx, -1, -1, -1 }; - MVT VVT = Op.getOperand(0).getValueType(); + EVT VVT = Op.getOperand(0).getValueType(); SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), DAG.getUNDEF(VVT), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, @@ -4353,7 +4353,7 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { // Note if the lower 64 bits of the result of the UNPCKHPD is then stored // to a f64mem, the whole operation is folded into a single MOVHPDmr. int Mask[2] = { 1, -1 }; - MVT VVT = Op.getOperand(0).getValueType(); + EVT VVT = Op.getOperand(0).getValueType(); SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), DAG.getUNDEF(VVT), Mask); return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, @@ -4365,8 +4365,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ - MVT VT = Op.getValueType(); - MVT EVT = VT.getVectorElementType(); + EVT VT = Op.getValueType(); + EVT EVT = VT.getVectorElementType(); DebugLoc dl = Op.getDebugLoc(); SDValue N0 = Op.getOperand(0); @@ -4379,12 +4379,12 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ : X86ISD::PINSRW; // Transform it so it match pinsr{b,w} which expects a GR32 as its second // argument. - if (N1.getValueType() != MVT::i32) - N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); - if (N2.getValueType() != MVT::i32) + if (N1.getValueType() != EVT::i32) + N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1); + if (N2.getValueType() != EVT::i32) N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); return DAG.getNode(Opc, dl, VT, N0, N1, N2); - } else if (EVT == MVT::f32 && isa<ConstantSDNode>(N2)) { + } else if (EVT == EVT::f32 && isa<ConstantSDNode>(N2)) { // Bits [7:6] of the constant are the source select. This will always be // zero here. The DAG Combiner may combine an extract_elt index into these // bits. For example (insert (extract, 3), 2) could be matched by putting @@ -4395,9 +4395,9 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ // combine either bitwise AND or insert of float 0.0 to set these bits. N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); // Create this as a scalar to vector.. - N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); + N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4f32, N1); return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); - } else if (EVT == MVT::i32 && isa<ConstantSDNode>(N2)) { + } else if (EVT == EVT::i32 && isa<ConstantSDNode>(N2)) { // PINSR* works with constant index. return Op; } @@ -4406,13 +4406,13 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){ SDValue X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - MVT EVT = VT.getVectorElementType(); + EVT VT = Op.getValueType(); + EVT EVT = VT.getVectorElementType(); if (Subtarget->hasSSE41()) return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); - if (EVT == MVT::i8) + if (EVT == EVT::i8) return SDValue(); DebugLoc dl = Op.getDebugLoc(); @@ -4423,9 +4423,9 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { if (EVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { // Transform it so it match pinsrw which expects a 16-bit value in a GR32 // as its second argument. - if (N1.getValueType() != MVT::i32) - N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); - if (N2.getValueType() != MVT::i32) + if (N1.getValueType() != EVT::i32) + N1 = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, N1); + if (N2.getValueType() != EVT::i32) N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); } @@ -4435,22 +4435,22 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); - if (Op.getValueType() == MVT::v2f32) - return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f32, - DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i32, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, + if (Op.getValueType() == EVT::v2f32) + return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f32, + DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2i32, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op.getOperand(0)))); - if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64) - return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); + if (Op.getValueType() == EVT::v1i64 && Op.getOperand(0).getValueType() == EVT::i64) + return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v1i64, Op.getOperand(0)); - SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); - MVT VT = MVT::v2i32; + SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, Op.getOperand(0)); + EVT VT = EVT::v2i32; switch (Op.getValueType().getSimpleVT()) { default: break; - case MVT::v16i8: - case MVT::v8i16: - VT = MVT::v4i32; + case EVT::v16i8: + case EVT::v8i16: + VT = EVT::v4i32; break; } return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), @@ -4623,9 +4623,9 @@ X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { static SDValue GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, - SDValue *InFlag, const MVT PtrVT, unsigned ReturnReg, + SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, unsigned char OperandFlags) { - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); DebugLoc dl = GA->getDebugLoc(); SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), GA->getValueType(0), @@ -4645,7 +4645,7 @@ GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit static SDValue LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT PtrVT) { + const EVT PtrVT) { SDValue InFlag; DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, @@ -4660,7 +4660,7 @@ LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit static SDValue LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT PtrVT) { + const EVT PtrVT) { return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, X86::RAX, X86II::MO_TLSGD); } @@ -4668,14 +4668,14 @@ LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or // "local exec" model. static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, - const MVT PtrVT, TLSModel::Model model, + const EVT PtrVT, TLSModel::Model model, bool is64Bit) { DebugLoc dl = GA->getDebugLoc(); // Get the Thread Pointer SDValue Base = DAG.getNode(X86ISD::SegmentBaseAddress, DebugLoc::getUnknownLoc(), PtrVT, DAG.getRegister(is64Bit? X86::FS : X86::GS, - MVT::i32)); + EVT::i32)); SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Base, NULL, 0); @@ -4749,7 +4749,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) { /// take a 2 x i32 value to shift plus a shift amount. SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { assert(Op.getNumOperands() == 3 && "Not a double-shift!"); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); unsigned VTBits = VT.getSizeInBits(); DebugLoc dl = Op.getDebugLoc(); bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; @@ -4757,7 +4757,7 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { SDValue ShOpHi = Op.getOperand(1); SDValue ShAmt = Op.getOperand(2); SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, - DAG.getConstant(VTBits - 1, MVT::i8)) + DAG.getConstant(VTBits - 1, EVT::i8)) : DAG.getConstant(0, VT); SDValue Tmp2, Tmp3; @@ -4769,13 +4769,13 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); } - SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, - DAG.getConstant(VTBits, MVT::i8)); + SDValue AndNode = DAG.getNode(ISD::AND, dl, EVT::i8, ShAmt, + DAG.getConstant(VTBits, EVT::i8)); SDValue Cond = DAG.getNode(X86ISD::CMP, dl, VT, - AndNode, DAG.getConstant(0, MVT::i8)); + AndNode, DAG.getConstant(0, EVT::i8)); SDValue Hi, Lo; - SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); + SDValue CC = DAG.getConstant(X86::COND_NE, EVT::i8); SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; @@ -4792,23 +4792,23 @@ SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) { } SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { - MVT SrcVT = Op.getOperand(0).getValueType(); + EVT SrcVT = Op.getOperand(0).getValueType(); if (SrcVT.isVector()) { - if (SrcVT == MVT::v2i32 && Op.getValueType() == MVT::v2f64) { + if (SrcVT == EVT::v2i32 && Op.getValueType() == EVT::v2f64) { return Op; } return SDValue(); } - assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && + assert(SrcVT.getSimpleVT() <= EVT::i64 && SrcVT.getSimpleVT() >= EVT::i16 && "Unknown SINT_TO_FP to lower!"); // These are really Legal; return the operand so the caller accepts it as // Legal. - if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) + if (SrcVT == EVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) return Op; - if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && + if (SrcVT == EVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && Subtarget->is64Bit()) { return Op; } @@ -4824,7 +4824,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); } -SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, +SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG) { // Build the FILD @@ -4832,9 +4832,9 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, SDVTList Tys; bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); if (useSSE) - Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag); + Tys = DAG.getVTList(EVT::f64, EVT::Other, EVT::Flag); else - Tys = DAG.getVTList(Op.getValueType(), MVT::Other); + Tys = DAG.getVTList(Op.getValueType(), EVT::Other); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(StackSlot); @@ -4852,7 +4852,7 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, MachineFunction &MF = DAG.getMachineFunction(); int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - Tys = DAG.getVTList(MVT::Other); + Tys = DAG.getVTList(EVT::Other); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Result); @@ -4923,31 +4923,31 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) { Constant *C1 = ConstantVector::get(CV1); SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); - SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(1))); - SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(0))); - SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); - SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, + SDValue Unpck1 = getUnpackl(DAG, dl, EVT::v4i32, XR1, XR2); + SDValue CLod0 = DAG.getLoad(EVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); - SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Unpck2); - SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, + SDValue Unpck2 = getUnpackl(DAG, dl, EVT::v4i32, Unpck1, CLod0); + SDValue XR2F = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Unpck2); + SDValue CLod1 = DAG.getLoad(EVT::v2f64, dl, CLod0.getValue(1), CPIdx1, PseudoSourceValue::getConstantPool(), 0, false, 16); - SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::v2f64, XR2F, CLod1); // Add the halves; easiest way is to swap them into another reg first. int ShufMask[2] = { 1, -1 }; - SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, - DAG.getUNDEF(MVT::v2f64), ShufMask); - SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); - return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, + SDValue Shuf = DAG.getVectorShuffle(EVT::v2f64, dl, Sub, + DAG.getUNDEF(EVT::v2f64), ShufMask); + SDValue Add = DAG.getNode(ISD::FADD, dl, EVT::v2f64, Shuf, Sub); + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, Add, DAG.getIntPtrConstant(0)); } @@ -4956,40 +4956,40 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); // FP constant to bias correct the final result. SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), - MVT::f64); + EVT::f64); // Load the 32-bit value into an XMM register. - SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, - DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v4i32, + DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Op.getOperand(0), DAG.getIntPtrConstant(0))); - Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Load), + Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Load), DAG.getIntPtrConstant(0)); // Or the load with the bias. - SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + SDValue Or = DAG.getNode(ISD::OR, dl, EVT::v2i64, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, - MVT::v2f64, Load)), - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + EVT::v2f64, Load)), + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, - MVT::v2f64, Bias))); - Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2f64, Or), + EVT::v2f64, Bias))); + Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f64, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2f64, Or), DAG.getIntPtrConstant(0)); // Subtract the bias. - SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); + SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Or, Bias); // Handle final rounding. - MVT DestVT = Op.getValueType(); + EVT DestVT = Op.getValueType(); - if (DestVT.bitsLT(MVT::f64)) { + if (DestVT.bitsLT(EVT::f64)) { return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, DAG.getIntPtrConstant(0)); - } else if (DestVT.bitsGT(MVT::f64)) { + } else if (DestVT.bitsGT(EVT::f64)) { return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); } @@ -5007,52 +5007,52 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) { if (DAG.SignBitIsZero(N0)) return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); - MVT SrcVT = N0.getValueType(); - if (SrcVT == MVT::i64) { + EVT SrcVT = N0.getValueType(); + if (SrcVT == EVT::i64) { // We only handle SSE2 f64 target here; caller can expand the rest. - if (Op.getValueType() != MVT::f64 || !X86ScalarSSEf64) + if (Op.getValueType() != EVT::f64 || !X86ScalarSSEf64) return SDValue(); return LowerUINT_TO_FP_i64(Op, DAG); - } else if (SrcVT == MVT::i32 && X86ScalarSSEf64) { + } else if (SrcVT == EVT::i32 && X86ScalarSSEf64) { return LowerUINT_TO_FP_i32(Op, DAG); } - assert(SrcVT == MVT::i32 && "Unknown UINT_TO_FP to lower!"); + assert(SrcVT == EVT::i32 && "Unknown UINT_TO_FP to lower!"); // Make a 64-bit buffer, and use it to build an FILD. - SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); + SDValue StackSlot = DAG.CreateStackTemporary(EVT::i64); SDValue WordOff = DAG.getConstant(4, getPointerTy()); SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackSlot, WordOff); SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), StackSlot, NULL, 0); - SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), + SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, EVT::i32), OffsetSlot, NULL, 0); - return BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); + return BuildFILD(Op, EVT::i64, Store2, StackSlot, DAG); } std::pair<SDValue,SDValue> X86TargetLowering:: FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { DebugLoc dl = Op.getDebugLoc(); - MVT DstTy = Op.getValueType(); + EVT DstTy = Op.getValueType(); if (!IsSigned) { - assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); - DstTy = MVT::i64; + assert(DstTy == EVT::i32 && "Unexpected FP_TO_UINT"); + DstTy = EVT::i64; } - assert(DstTy.getSimpleVT() <= MVT::i64 && - DstTy.getSimpleVT() >= MVT::i16 && + assert(DstTy.getSimpleVT() <= EVT::i64 && + DstTy.getSimpleVT() >= EVT::i16 && "Unknown FP_TO_SINT to lower!"); // These are really Legal. - if (DstTy == MVT::i32 && + if (DstTy == EVT::i32 && isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) return std::make_pair(SDValue(), SDValue()); if (Subtarget->is64Bit() && - DstTy == MVT::i64 && + DstTy == EVT::i64 && isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) return std::make_pair(SDValue(), SDValue()); @@ -5066,18 +5066,18 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { unsigned Opc; switch (DstTy.getSimpleVT()) { default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); - case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; - case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; - case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; + case EVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; + case EVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; + case EVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; } SDValue Chain = DAG.getEntryNode(); SDValue Value = Op.getOperand(0); if (isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) { - assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); + assert(DstTy == EVT::i64 && "Invalid FP_TO_SINT to lower!"); Chain = DAG.getStore(Chain, dl, Value, StackSlot, PseudoSourceValue::getFixedStack(SSFI), 0); - SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); + SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), EVT::Other); SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(Op.getOperand(0).getValueType()) }; @@ -5089,15 +5089,15 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) { // Build the FP_TO_INT*_IN_MEM SDValue Ops[] = { Chain, Value, StackSlot }; - SDValue FIST = DAG.getNode(Opc, dl, MVT::Other, Ops, 3); + SDValue FIST = DAG.getNode(Opc, dl, EVT::Other, Ops, 3); return std::make_pair(FIST, StackSlot); } SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) { if (Op.getValueType().isVector()) { - if (Op.getValueType() == MVT::v2i32 && - Op.getOperand(0).getValueType() == MVT::v2f64) { + if (Op.getValueType() == EVT::v2i32 && + Op.getOperand(0).getValueType() == EVT::v2f64) { return Op; } return SDValue(); @@ -5126,12 +5126,12 @@ SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { LLVMContext *Context = DAG.getContext(); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); - MVT EltVT = VT; + EVT VT = Op.getValueType(); + EVT EltVT = VT; if (VT.isVector()) EltVT = VT.getVectorElementType(); std::vector<Constant*> CV; - if (EltVT == MVT::f64) { + if (EltVT == EVT::f64) { Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); CV.push_back(C); CV.push_back(C); @@ -5153,15 +5153,15 @@ SDValue X86TargetLowering::LowerFABS(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { LLVMContext *Context = DAG.getContext(); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); - MVT EltVT = VT; + EVT VT = Op.getValueType(); + EVT EltVT = VT; unsigned EltNum = 1; if (VT.isVector()) { EltVT = VT.getVectorElementType(); EltNum = VT.getVectorNumElements(); } std::vector<Constant*> CV; - if (EltVT == MVT::f64) { + if (EltVT == EVT::f64) { Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); CV.push_back(C); CV.push_back(C); @@ -5179,10 +5179,10 @@ SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) { false, 16); if (VT.isVector()) { return DAG.getNode(ISD::BIT_CONVERT, dl, VT, - DAG.getNode(ISD::XOR, dl, MVT::v2i64, - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, + DAG.getNode(ISD::XOR, dl, EVT::v2i64, + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, Op.getOperand(0)), - DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, Mask))); + DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v2i64, Mask))); } else { return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); } @@ -5193,8 +5193,8 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); DebugLoc dl = Op.getDebugLoc(); - MVT VT = Op.getValueType(); - MVT SrcVT = Op1.getValueType(); + EVT VT = Op.getValueType(); + EVT SrcVT = Op1.getValueType(); // If second operand is smaller, extend it first. if (SrcVT.bitsLT(VT)) { @@ -5212,7 +5212,7 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // First get the sign bit of second operand. std::vector<Constant*> CV; - if (SrcVT == MVT::f64) { + if (SrcVT == EVT::f64) { CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); } else { @@ -5230,18 +5230,18 @@ SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) { // Shift sign bit right or left if the two operands have different types. if (SrcVT.bitsGT(VT)) { - // Op0 is MVT::f32, Op1 is MVT::f64. - SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); - SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, - DAG.getConstant(32, MVT::i32)); - SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v4f32, SignBit); - SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, + // Op0 is EVT::f32, Op1 is EVT::f64. + SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, EVT::v2f64, SignBit); + SignBit = DAG.getNode(X86ISD::FSRL, dl, EVT::v2f64, SignBit, + DAG.getConstant(32, EVT::i32)); + SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::v4f32, SignBit); + SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EVT::f32, SignBit, DAG.getIntPtrConstant(0)); } // Clear first operand sign bit. CV.clear(); - if (VT == MVT::f64) { + if (VT == EVT::f64) { CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); } else { @@ -5342,7 +5342,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, break; } if (Opcode != 0) { - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); + SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::i32); SmallVector<SDValue, 4> Ops; for (unsigned i = 0; i != NumOperands; ++i) Ops.push_back(Op.getOperand(i)); @@ -5353,7 +5353,7 @@ SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, } // Otherwise just emit a CMP with 0, which is the TEST pattern. - return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, + return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op, DAG.getConstant(0, Op.getValueType())); } @@ -5366,11 +5366,11 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, return EmitTest(Op0, X86CC, DAG); DebugLoc dl = Op0.getDebugLoc(); - return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); + return DAG.getNode(X86ISD::CMP, dl, EVT::i32, Op0, Op1); } SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { - assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); + assert(Op.getValueType() == EVT::i8 && "SetCC type must be 8-bit integer"); SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); DebugLoc dl = Op.getDebugLoc(); @@ -5413,18 +5413,18 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { // instruction. Since the shift amount is in-range-or-undefined, we know // that doing a bittest on the i16 value is ok. We extend to i32 because // the encoding for the i16 version is larger than the i32 version. - if (LHS.getValueType() == MVT::i8) - LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); + if (LHS.getValueType() == EVT::i8) + LHS = DAG.getNode(ISD::ANY_EXTEND, dl, EVT::i32, LHS); // If the operand types disagree, extend the shift amount to match. Since // BT ignores high bits (like shifts) we can use anyextend. if (LHS.getValueType() != RHS.getValueType()) RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); - SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); + SDValue BT = DAG.getNode(X86ISD::BT, dl, EVT::i32, LHS, RHS); unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; - return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, - DAG.getConstant(Cond, MVT::i8), BT); + return DAG.getNode(X86ISD::SETCC, dl, EVT::i8, + DAG.getConstant(Cond, EVT::i8), BT); } } @@ -5432,8 +5432,8 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) { unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); SDValue Cond = EmitCmp(Op0, Op1, X86CC, DAG); - return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, - DAG.getConstant(X86CC, MVT::i8), Cond); + return DAG.getNode(X86ISD::SETCC, dl, EVT::i8, + DAG.getConstant(X86CC, EVT::i8), Cond); } SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { @@ -5441,16 +5441,16 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { SDValue Op0 = Op.getOperand(0); SDValue Op1 = Op.getOperand(1); SDValue CC = Op.getOperand(2); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); DebugLoc dl = Op.getDebugLoc(); if (isFP) { unsigned SSECC = 8; - MVT VT0 = Op0.getValueType(); - assert(VT0 == MVT::v4f32 || VT0 == MVT::v2f64); - unsigned Opc = VT0 == MVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; + EVT VT0 = Op0.getValueType(); + assert(VT0 == EVT::v4f32 || VT0 == EVT::v2f64); + unsigned Opc = VT0 == EVT::v4f32 ? X86ISD::CMPPS : X86ISD::CMPPD; bool Swap = false; switch (SetCCOpcode) { @@ -5481,20 +5481,20 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { if (SSECC == 8) { if (SetCCOpcode == ISD::SETUEQ) { SDValue UNORD, EQ; - UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); - EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); + UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, EVT::i8)); + EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, EVT::i8)); return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); } else if (SetCCOpcode == ISD::SETONE) { SDValue ORD, NEQ; - ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); - NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); + ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, EVT::i8)); + NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, EVT::i8)); return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); } llvm_unreachable("Illegal FP comparison"); } // Handle all other FP comparisons here. - return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); + return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, EVT::i8)); } // We are handling one of the integer comparisons here. Since SSE only has @@ -5505,13 +5505,13 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { switch (VT.getSimpleVT()) { default: break; - case MVT::v8i8: - case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; - case MVT::v4i16: - case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; - case MVT::v2i32: - case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; - case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; + case EVT::v8i8: + case EVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; + case EVT::v4i16: + case EVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; + case EVT::v2i32: + case EVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; + case EVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; } switch (SetCCOpcode) { @@ -5533,7 +5533,7 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) { // Since SSE has no unsigned integer comparisons, we need to flip the sign // bits of the inputs before performing those operations. if (FlipSigns) { - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), EltVT); std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); @@ -5585,7 +5585,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { SDValue Cmp = Cond.getOperand(1); unsigned Opc = Cmp.getOpcode(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); bool IllegalFPCMov = false; if (VT.isFloatingPoint() && !VT.isVector() && @@ -5600,11 +5600,11 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) { } if (addTest) { - CC = DAG.getConstant(X86::COND_NE, MVT::i8); + CC = DAG.getConstant(X86::COND_NE, EVT::i8); Cond = EmitTest(Cond, X86::COND_NE, DAG); } - SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag); + SDVTList VTs = DAG.getVTList(Op.getValueType(), EVT::Flag); SmallVector<SDValue, 4> Ops; // X86ISD::CMOV means set the result (which is operand 1) to the RHS if // condition is true. @@ -5712,7 +5712,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { X86::CondCode CCode = (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); CCode = X86::GetOppositeBranchCondition(CCode); - CC = DAG.getConstant(CCode, MVT::i8); + CC = DAG.getConstant(CCode, EVT::i8); SDValue User = SDValue(*Op.getNode()->use_begin(), 0); // Look for an unconditional branch following this conditional branch. // We need this because we need to reverse the successors in order @@ -5729,7 +5729,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { X86::CondCode CCode = (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); CCode = X86::GetOppositeBranchCondition(CCode); - CC = DAG.getConstant(CCode, MVT::i8); + CC = DAG.getConstant(CCode, EVT::i8); Cond = Cmp; addTest = false; } @@ -5742,14 +5742,14 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) { X86::CondCode CCode = (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); CCode = X86::GetOppositeBranchCondition(CCode); - CC = DAG.getConstant(CCode, MVT::i8); + CC = DAG.getConstant(CCode, EVT::i8); Cond = Cond.getOperand(0).getOperand(1); addTest = false; } } if (addTest) { - CC = DAG.getConstant(X86::COND_NE, MVT::i8); + CC = DAG.getConstant(X86::COND_NE, EVT::i8); Cond = EmitTest(Cond, X86::COND_NE, DAG); } return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), @@ -5776,15 +5776,15 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue Flag; - MVT IntPtr = getPointerTy(); - MVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; + EVT IntPtr = getPointerTy(); + EVT SPTy = Subtarget->is64Bit() ? EVT::i64 : EVT::i32; Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); Flag = Chain.getValue(1); - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue Ops[] = { Chain, DAG.getTargetExternalSymbol("_alloca", IntPtr), DAG.getRegister(X86::EAX, IntPtr), @@ -5827,7 +5827,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, if (const char *bzeroEntry = V && V->isNullValue() ? Subtarget->getBZeroEntry() : 0) { - MVT IntPtr = getPointerTy(); + EVT IntPtr = getPointerTy(); const Type *IntPtrTy = TD->getIntPtrType(); TargetLowering::ArgListTy Args; TargetLowering::ArgListEntry Entry; @@ -5849,7 +5849,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, uint64_t SizeVal = ConstantSize->getZExtValue(); SDValue InFlag(0, 0); - MVT AVT; + EVT AVT; SDValue Count; ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src); unsigned BytesLeft = 0; @@ -5861,29 +5861,29 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, // If the value is a constant, then we can potentially use larger sets. switch (Align & 3) { case 2: // WORD aligned - AVT = MVT::i16; + AVT = EVT::i16; ValReg = X86::AX; Val = (Val << 8) | Val; break; case 0: // DWORD aligned - AVT = MVT::i32; + AVT = EVT::i32; ValReg = X86::EAX; Val = (Val << 8) | Val; Val = (Val << 16) | Val; if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned - AVT = MVT::i64; + AVT = EVT::i64; ValReg = X86::RAX; Val = (Val << 32) | Val; } break; default: // Byte aligned - AVT = MVT::i8; + AVT = EVT::i8; ValReg = X86::AL; Count = DAG.getIntPtrConstant(SizeVal); break; } - if (AVT.bitsGT(MVT::i8)) { + if (AVT.bitsGT(EVT::i8)) { unsigned UBytes = AVT.getSizeInBits() / 8; Count = DAG.getIntPtrConstant(SizeVal / UBytes); BytesLeft = SizeVal % UBytes; @@ -5893,7 +5893,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, InFlag); InFlag = Chain.getValue(1); } else { - AVT = MVT::i8; + AVT = EVT::i8; Count = DAG.getIntPtrConstant(SizeVal); Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); InFlag = Chain.getValue(1); @@ -5908,7 +5908,7 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, Dst, InFlag); InFlag = Chain.getValue(1); - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); @@ -5918,24 +5918,24 @@ X86TargetLowering::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, if (TwoRepStos) { InFlag = Chain.getValue(1); Count = Size; - MVT CVT = Count.getValueType(); + EVT CVT = Count.getValueType(); SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count, - DAG.getConstant((AVT == MVT::i64) ? 7 : 3, CVT)); - Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : + DAG.getConstant((AVT == EVT::i64) ? 7 : 3, CVT)); + Chain = DAG.getCopyToReg(Chain, dl, (CVT == EVT::i64) ? X86::RCX : X86::ECX, Left, InFlag); InFlag = Chain.getValue(1); - Tys = DAG.getVTList(MVT::Other, MVT::Flag); + Tys = DAG.getVTList(EVT::Other, EVT::Flag); Ops.clear(); Ops.push_back(Chain); - Ops.push_back(DAG.getValueType(MVT::i8)); + Ops.push_back(DAG.getValueType(EVT::i8)); Ops.push_back(InFlag); Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, &Ops[0], Ops.size()); } else if (BytesLeft) { // Handle the last 1 - 7 bytes. unsigned Offset = SizeVal - BytesLeft; - MVT AddrVT = Dst.getValueType(); - MVT SizeVT = Size.getValueType(); + EVT AddrVT = Dst.getValueType(); + EVT SizeVT = Size.getValueType(); Chain = DAG.getMemset(Chain, dl, DAG.getNode(ISD::ADD, dl, AddrVT, Dst, @@ -5970,9 +5970,9 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, return SDValue(); // DWORD aligned - MVT AVT = MVT::i32; + EVT AVT = EVT::i32; if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) // QWORD aligned - AVT = MVT::i64; + AVT = EVT::i64; unsigned UBytes = AVT.getSizeInBits() / 8; unsigned CountVal = SizeVal / UBytes; @@ -5993,7 +5993,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, Src, InFlag); InFlag = Chain.getValue(1); - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(DAG.getValueType(AVT)); @@ -6005,9 +6005,9 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, if (BytesLeft) { // Handle the last 1 - 7 bytes. unsigned Offset = SizeVal - BytesLeft; - MVT DstVT = Dst.getValueType(); - MVT SrcVT = Src.getValueType(); - MVT SizeVT = Size.getValueType(); + EVT DstVT = Dst.getValueType(); + EVT SrcVT = Src.getValueType(); + EVT SizeVT = Size.getValueType(); Results.push_back(DAG.getMemcpy(Chain, dl, DAG.getNode(ISD::ADD, dl, DstVT, Dst, DAG.getConstant(Offset, DstVT)), @@ -6019,7 +6019,7 @@ X86TargetLowering::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl, SrcSV, SrcSVOff + Offset)); } - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Results[0], Results.size()); } @@ -6043,7 +6043,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { SDValue FIN = Op.getOperand(1); // Store gp_offset SDValue Store = DAG.getStore(Op.getOperand(0), dl, - DAG.getConstant(VarArgsGPOffset, MVT::i32), + DAG.getConstant(VarArgsGPOffset, EVT::i32), FIN, SV, 0); MemOps.push_back(Store); @@ -6051,7 +6051,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), FIN, DAG.getIntPtrConstant(4)); Store = DAG.getStore(Op.getOperand(0), dl, - DAG.getConstant(VarArgsFPOffset, MVT::i32), + DAG.getConstant(VarArgsFPOffset, EVT::i32), FIN, SV, 0); MemOps.push_back(Store); @@ -6068,7 +6068,7 @@ SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) { SDValue RSFIN = DAG.getFrameIndex(RegSaveFrameIndex, getPointerTy()); Store = DAG.getStore(Op.getOperand(0), dl, RSFIN, FIN, SV, 0); MemOps.push_back(Store); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOps[0], MemOps.size()); } @@ -6198,10 +6198,10 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { SDValue LHS = Op.getOperand(1); SDValue RHS = Op.getOperand(2); unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); - SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); - SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, - DAG.getConstant(X86CC, MVT::i8), Cond); - return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); + SDValue Cond = DAG.getNode(Opc, dl, EVT::i32, LHS, RHS); + SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8, + DAG.getConstant(X86CC, EVT::i8), Cond); + return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC); } // ptest intrinsics. The intrinsic these come from are designed to return // an integer value, not just an instruction so lower it to the ptest @@ -6228,10 +6228,10 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { SDValue LHS = Op.getOperand(1); SDValue RHS = Op.getOperand(2); - SDValue Test = DAG.getNode(X86ISD::PTEST, dl, MVT::i32, LHS, RHS); - SDValue CC = DAG.getConstant(X86CC, MVT::i8); - SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); - return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); + SDValue Test = DAG.getNode(X86ISD::PTEST, dl, EVT::i32, LHS, RHS); + SDValue CC = DAG.getConstant(X86CC, EVT::i8); + SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, EVT::i8, CC, Test); + return DAG.getNode(ISD::ZERO_EXTEND, dl, EVT::i32, SetCC); } // Fix vector shift instructions where the last operand is a non-immediate @@ -6257,7 +6257,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { return SDValue(); unsigned NewIntNo = 0; - MVT ShAmtVT = MVT::v4i32; + EVT ShAmtVT = EVT::v4i32; switch (IntNo) { case Intrinsic::x86_sse2_pslli_w: NewIntNo = Intrinsic::x86_sse2_psll_w; @@ -6284,7 +6284,7 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { NewIntNo = Intrinsic::x86_sse2_psra_d; break; default: { - ShAmtVT = MVT::v2i32; + ShAmtVT = EVT::v2i32; switch (IntNo) { case Intrinsic::x86_mmx_pslli_w: NewIntNo = Intrinsic::x86_mmx_psll_w; @@ -6315,11 +6315,11 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) { break; } } - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt)); return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(NewIntNo, MVT::i32), + DAG.getConstant(NewIntNo, EVT::i32), Op.getOperand(1), ShAmt); } } @@ -6333,7 +6333,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue Offset = DAG.getConstant(TD->getPointerSize(), - Subtarget->is64Bit() ? MVT::i64 : MVT::i32); + Subtarget->is64Bit() ? EVT::i64 : EVT::i32); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, getPointerTy(), FrameAddr, Offset), @@ -6349,7 +6349,7 @@ SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setFrameAddressIsTaken(true); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; @@ -6384,7 +6384,7 @@ SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) MF.getRegInfo().addLiveOut(StoreAddrReg); return DAG.getNode(X86ISD::EH_RETURN, dl, - MVT::Other, + EVT::Other, Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); } @@ -6417,40 +6417,40 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, // Load the pointer to the nested function into R11. unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 SDValue Addr = Trmp; - OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16), Addr, TrmpAddr, 0); - Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, - DAG.getConstant(2, MVT::i64)); + Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp, + DAG.getConstant(2, EVT::i64)); OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, TrmpAddr, 2, false, 2); // Load the 'nest' parameter value into R10. // R10 is specified in X86CallingConv.td OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 - Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, - DAG.getConstant(10, MVT::i64)); - OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp, + DAG.getConstant(10, EVT::i64)); + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16), Addr, TrmpAddr, 10); - Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, - DAG.getConstant(12, MVT::i64)); + Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp, + DAG.getConstant(12, EVT::i64)); OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 12, false, 2); // Jump to the nested function. OpCode = (JMP64r << 8) | REX_WB; // jmpq *... - Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, - DAG.getConstant(20, MVT::i64)); - OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), + Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp, + DAG.getConstant(20, EVT::i64)); + OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, EVT::i16), Addr, TrmpAddr, 20); unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 - Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, - DAG.getConstant(22, MVT::i64)); - OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, + Addr = DAG.getNode(ISD::ADD, dl, EVT::i64, Trmp, + DAG.getConstant(22, EVT::i64)); + OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, EVT::i8), Addr, TrmpAddr, 22); SDValue Ops[] = - { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6) }; + { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 6) }; return DAG.getMergeValues(Ops, 2, dl); } else { const Function *Func = @@ -6498,32 +6498,32 @@ SDValue X86TargetLowering::LowerTRAMPOLINE(SDValue Op, SDValue OutChains[4]; SDValue Addr, Disp; - Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, - DAG.getConstant(10, MVT::i32)); - Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); + Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp, + DAG.getConstant(10, EVT::i32)); + Disp = DAG.getNode(ISD::SUB, dl, EVT::i32, FPtr, Addr); const unsigned char MOV32ri = TII->getBaseOpcodeFor(X86::MOV32ri); const unsigned char N86Reg = RegInfo->getX86RegNum(NestReg); OutChains[0] = DAG.getStore(Root, dl, - DAG.getConstant(MOV32ri|N86Reg, MVT::i8), + DAG.getConstant(MOV32ri|N86Reg, EVT::i8), Trmp, TrmpAddr, 0); - Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, - DAG.getConstant(1, MVT::i32)); + Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp, + DAG.getConstant(1, EVT::i32)); OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, TrmpAddr, 1, false, 1); const unsigned char JMP = TII->getBaseOpcodeFor(X86::JMP); - Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, - DAG.getConstant(5, MVT::i32)); - OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, + Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp, + DAG.getConstant(5, EVT::i32)); + OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, EVT::i8), Addr, TrmpAddr, 5, false, 1); - Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, - DAG.getConstant(6, MVT::i32)); + Addr = DAG.getNode(ISD::ADD, dl, EVT::i32, Trmp, + DAG.getConstant(6, EVT::i32)); OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, TrmpAddr, 6, false, 1); SDValue Ops[] = - { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4) }; + { Trmp, DAG.getNode(ISD::TokenFactor, dl, EVT::Other, OutChains, 4) }; return DAG.getMergeValues(Ops, 2, dl); } } @@ -6552,37 +6552,37 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { const TargetMachine &TM = MF.getTarget(); const TargetFrameInfo &TFI = *TM.getFrameInfo(); unsigned StackAlignment = TFI.getStackAlignment(); - MVT VT = Op.getValueType(); + EVT VT = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); // Save FP Control Word to stack slot int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); - SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, MVT::Other, + SDValue Chain = DAG.getNode(X86ISD::FNSTCW16m, dl, EVT::Other, DAG.getEntryNode(), StackSlot); // Load FP Control Word from stack slot - SDValue CWD = DAG.getLoad(MVT::i16, dl, Chain, StackSlot, NULL, 0); + SDValue CWD = DAG.getLoad(EVT::i16, dl, Chain, StackSlot, NULL, 0); // Transform as necessary SDValue CWD1 = - DAG.getNode(ISD::SRL, dl, MVT::i16, - DAG.getNode(ISD::AND, dl, MVT::i16, - CWD, DAG.getConstant(0x800, MVT::i16)), - DAG.getConstant(11, MVT::i8)); + DAG.getNode(ISD::SRL, dl, EVT::i16, + DAG.getNode(ISD::AND, dl, EVT::i16, + CWD, DAG.getConstant(0x800, EVT::i16)), + DAG.getConstant(11, EVT::i8)); SDValue CWD2 = - DAG.getNode(ISD::SRL, dl, MVT::i16, - DAG.getNode(ISD::AND, dl, MVT::i16, - CWD, DAG.getConstant(0x400, MVT::i16)), - DAG.getConstant(9, MVT::i8)); + DAG.getNode(ISD::SRL, dl, EVT::i16, + DAG.getNode(ISD::AND, dl, EVT::i16, + CWD, DAG.getConstant(0x400, EVT::i16)), + DAG.getConstant(9, EVT::i8)); SDValue RetVal = - DAG.getNode(ISD::AND, dl, MVT::i16, - DAG.getNode(ISD::ADD, dl, MVT::i16, - DAG.getNode(ISD::OR, dl, MVT::i16, CWD1, CWD2), - DAG.getConstant(1, MVT::i16)), - DAG.getConstant(3, MVT::i16)); + DAG.getNode(ISD::AND, dl, EVT::i16, + DAG.getNode(ISD::ADD, dl, EVT::i16, + DAG.getNode(ISD::OR, dl, EVT::i16, CWD1, CWD2), + DAG.getConstant(1, EVT::i16)), + DAG.getConstant(3, EVT::i16)); return DAG.getNode((VT.getSizeInBits() < 16 ? @@ -6590,70 +6590,70 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) { } SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - MVT OpVT = VT; + EVT VT = Op.getValueType(); + EVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); DebugLoc dl = Op.getDebugLoc(); Op = Op.getOperand(0); - if (VT == MVT::i8) { + if (VT == EVT::i8) { // Zero extend to i32 since there is not an i8 bsr. - OpVT = MVT::i32; + OpVT = EVT::i32; Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); } // Issue a bsr (scan bits in reverse) which also sets EFLAGS. - SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); + SDVTList VTs = DAG.getVTList(OpVT, EVT::i32); Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); // If src is zero (i.e. bsr sets ZF), returns NumBits. SmallVector<SDValue, 4> Ops; Ops.push_back(Op); Ops.push_back(DAG.getConstant(NumBits+NumBits-1, OpVT)); - Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); + Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8)); Ops.push_back(Op.getValue(1)); Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); // Finally xor with NumBits-1. Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); - if (VT == MVT::i8) - Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); + if (VT == EVT::i8) + Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op); return Op; } SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - MVT OpVT = VT; + EVT VT = Op.getValueType(); + EVT OpVT = VT; unsigned NumBits = VT.getSizeInBits(); DebugLoc dl = Op.getDebugLoc(); Op = Op.getOperand(0); - if (VT == MVT::i8) { - OpVT = MVT::i32; + if (VT == EVT::i8) { + OpVT = EVT::i32; Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); } // Issue a bsf (scan bits forward) which also sets EFLAGS. - SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); + SDVTList VTs = DAG.getVTList(OpVT, EVT::i32); Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); // If src is zero (i.e. bsf sets ZF), returns NumBits. SmallVector<SDValue, 4> Ops; Ops.push_back(Op); Ops.push_back(DAG.getConstant(NumBits, OpVT)); - Ops.push_back(DAG.getConstant(X86::COND_E, MVT::i8)); + Ops.push_back(DAG.getConstant(X86::COND_E, EVT::i8)); Ops.push_back(Op.getValue(1)); Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, &Ops[0], 4); - if (VT == MVT::i8) - Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); + if (VT == EVT::i8) + Op = DAG.getNode(ISD::TRUNCATE, dl, EVT::i8, Op); return Op; } SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { - MVT VT = Op.getValueType(); - assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); + EVT VT = Op.getValueType(); + assert(VT == EVT::v2i64 && "Only know how to lower V2I64 multiply"); DebugLoc dl = Op.getDebugLoc(); // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); @@ -6670,26 +6670,26 @@ SDValue X86TargetLowering::LowerMUL_V2I64(SDValue Op, SelectionDAG &DAG) { SDValue B = Op.getOperand(1); SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), - A, DAG.getConstant(32, MVT::i32)); + DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32), + A, DAG.getConstant(32, EVT::i32)); SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), - B, DAG.getConstant(32, MVT::i32)); + DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32), + B, DAG.getConstant(32, EVT::i32)); SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32), A, B); SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32), A, Bhi); SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, EVT::i32), Ahi, B); AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), - AloBhi, DAG.getConstant(32, MVT::i32)); + DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32), + AloBhi, DAG.getConstant(32, EVT::i32)); AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, - DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), - AhiBlo, DAG.getConstant(32, MVT::i32)); + DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32), + AhiBlo, DAG.getConstant(32, EVT::i32)); SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); return Res; @@ -6753,29 +6753,29 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) { } // Also sets EFLAGS. - SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); + SDVTList VTs = DAG.getVTList(N->getValueType(0), EVT::i32); SDValue Sum = DAG.getNode(BaseOp, dl, VTs, LHS, RHS); SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, N->getValueType(1), - DAG.getConstant(Cond, MVT::i32), SDValue(Sum.getNode(), 1)); + DAG.getConstant(Cond, EVT::i32), SDValue(Sum.getNode(), 1)); DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); return Sum; } SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { - MVT T = Op.getValueType(); + EVT T = Op.getValueType(); DebugLoc dl = Op.getDebugLoc(); unsigned Reg = 0; unsigned size = 0; switch(T.getSimpleVT()) { default: assert(false && "Invalid value type!"); - case MVT::i8: Reg = X86::AL; size = 1; break; - case MVT::i16: Reg = X86::AX; size = 2; break; - case MVT::i32: Reg = X86::EAX; size = 4; break; - case MVT::i64: + case EVT::i8: Reg = X86::AL; size = 1; break; + case EVT::i16: Reg = X86::AX; size = 2; break; + case EVT::i32: Reg = X86::EAX; size = 4; break; + case EVT::i64: assert(Subtarget->is64Bit() && "Node not type legal!"); Reg = X86::RAX; size = 8; break; @@ -6785,9 +6785,9 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { SDValue Ops[] = { cpIn.getValue(0), Op.getOperand(1), Op.getOperand(3), - DAG.getTargetConstant(size, MVT::i8), + DAG.getTargetConstant(size, EVT::i8), cpIn.getValue(1) }; - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue Result = DAG.getNode(X86ISD::LCMPXCHG_DAG, dl, Tys, Ops, 5); SDValue cpOut = DAG.getCopyFromReg(Result.getValue(0), dl, Reg, T, Result.getValue(1)); @@ -6797,17 +6797,17 @@ SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) { SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) { assert(Subtarget->is64Bit() && "Result not type legalized?"); - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue TheChain = Op.getOperand(0); DebugLoc dl = Op.getDebugLoc(); SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); - SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); - SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, + SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, EVT::i64, rd.getValue(1)); + SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, EVT::i64, rax.getValue(2)); - SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, - DAG.getConstant(32, MVT::i8)); + SDValue Tmp = DAG.getNode(ISD::SHL, dl, EVT::i64, rdx, + DAG.getConstant(32, EVT::i8)); SDValue Ops[] = { - DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), + DAG.getNode(ISD::OR, dl, EVT::i64, rax, Tmp), rdx.getValue(1) }; return DAG.getMergeValues(Ops, 2, dl); @@ -6816,7 +6816,7 @@ SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) { SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); - MVT T = Node->getValueType(0); + EVT T = Node->getValueType(0); SDValue negOp = DAG.getNode(ISD::SUB, dl, T, DAG.getConstant(0, T), Node->getOperand(2)); return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, @@ -6886,24 +6886,24 @@ SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { void X86TargetLowering:: ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, SelectionDAG &DAG, unsigned NewOp) { - MVT T = Node->getValueType(0); + EVT T = Node->getValueType(0); DebugLoc dl = Node->getDebugLoc(); - assert (T == MVT::i64 && "Only know how to expand i64 atomics"); + assert (T == EVT::i64 && "Only know how to expand i64 atomics"); SDValue Chain = Node->getOperand(0); SDValue In1 = Node->getOperand(1); - SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Node->getOperand(2), DAG.getIntPtrConstant(0)); - SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, + SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, Node->getOperand(2), DAG.getIntPtrConstant(1)); // This is a generalized SDNode, not an AtomicSDNode, so it doesn't // have a MemOperand. Pass the info through as a normal operand. SDValue LSI = DAG.getMemOperand(cast<MemSDNode>(Node)->getMemOperand()); SDValue Ops[] = { Chain, In1, In2L, In2H, LSI }; - SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); + SDVTList Tys = DAG.getVTList(EVT::i32, EVT::i32, EVT::Other); SDValue Result = DAG.getNode(NewOp, dl, Tys, Ops, 5); SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2)); Results.push_back(Result.getValue(2)); } @@ -6922,42 +6922,42 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, FP_TO_INTHelper(SDValue(N, 0), DAG, true); SDValue FIST = Vals.first, StackSlot = Vals.second; if (FIST.getNode() != 0) { - MVT VT = N->getValueType(0); + EVT VT = N->getValueType(0); // Return a load from the stack slot. Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, NULL, 0)); } return; } case ISD::READCYCLECOUNTER: { - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue TheChain = N->getOperand(0); SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); - SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, + SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, EVT::i32, rd.getValue(1)); - SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, + SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, EVT::i32, eax.getValue(2)); // Use a buildpair to merge the two 32-bit values into a 64-bit one. SDValue Ops[] = { eax, edx }; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Ops, 2)); Results.push_back(edx.getValue(1)); return; } case ISD::ATOMIC_CMP_SWAP: { - MVT T = N->getValueType(0); - assert (T == MVT::i64 && "Only know how to expand i64 Cmp and Swap"); + EVT T = N->getValueType(0); + assert (T == EVT::i64 && "Only know how to expand i64 Cmp and Swap"); SDValue cpInL, cpInH; - cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), - DAG.getConstant(0, MVT::i32)); - cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(2), - DAG.getConstant(1, MVT::i32)); + cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2), + DAG.getConstant(0, EVT::i32)); + cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(2), + DAG.getConstant(1, EVT::i32)); cpInL = DAG.getCopyToReg(N->getOperand(0), dl, X86::EAX, cpInL, SDValue()); cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, X86::EDX, cpInH, cpInL.getValue(1)); SDValue swapInL, swapInH; - swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), - DAG.getConstant(0, MVT::i32)); - swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, N->getOperand(3), - DAG.getConstant(1, MVT::i32)); + swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3), + DAG.getConstant(0, EVT::i32)); + swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, N->getOperand(3), + DAG.getConstant(1, EVT::i32)); swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, X86::EBX, swapInL, cpInH.getValue(1)); swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, X86::ECX, swapInH, @@ -6965,14 +6965,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N, SDValue Ops[] = { swapInH.getValue(0), N->getOperand(1), swapInH.getValue(1) }; - SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList Tys = DAG.getVTList(EVT::Other, EVT::Flag); SDValue Result = DAG.getNode(X86ISD::LCMPXCHG8_DAG, dl, Tys, Ops, 3); SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, X86::EAX, - MVT::i32, Result.getValue(1)); + EVT::i32, Result.getValue(1)); SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, X86::EDX, - MVT::i32, cpOutL.getValue(2)); + EVT::i32, cpOutL.getValue(2)); SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; - Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); + Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, OpsF, 2)); Results.push_back(cpOutH.getValue(1)); return; } @@ -7144,7 +7144,7 @@ bool X86TargetLowering::isTruncateFree(const Type *Ty1, const Type *Ty2) const { return Subtarget->is64Bit() || NumBits1 < 64; } -bool X86TargetLowering::isTruncateFree(MVT VT1, MVT VT2) const { +bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { if (!VT1.isInteger() || !VT2.isInteger()) return false; unsigned NumBits1 = VT1.getSizeInBits(); @@ -7159,14 +7159,14 @@ bool X86TargetLowering::isZExtFree(const Type *Ty1, const Type *Ty2) const { return Ty1 == Type::Int32Ty && Ty2 == Type::Int64Ty && Subtarget->is64Bit(); } -bool X86TargetLowering::isZExtFree(MVT VT1, MVT VT2) const { +bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. - return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); + return VT1 == EVT::i32 && VT2 == EVT::i64 && Subtarget->is64Bit(); } -bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const { +bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { // i16 instructions are longer (0x66 prefix) and potentially slower. - return !(VT1 == MVT::i32 && VT2 == MVT::i16); + return !(VT1 == EVT::i32 && VT2 == EVT::i16); } /// isShuffleMaskLegal - Targets can use this to indicate that they only @@ -7175,7 +7175,7 @@ bool X86TargetLowering::isNarrowingProfitable(MVT VT1, MVT VT2) const { /// are assumed to be legal. bool X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, - MVT VT) const { + EVT VT) const { // Only do shuffles on 128-bit vector types for now. if (VT.getSizeInBits() == 64) return false; @@ -7196,7 +7196,7 @@ X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, bool X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, - MVT VT) const { + EVT VT) const { unsigned NumElts = VT.getVectorNumElements(); // FIXME: This collection of masks seems suspect. if (NumElts == 2) @@ -7941,7 +7941,7 @@ static bool isBaseAlignmentOfN(unsigned N, SDNode *Base, } static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, - MVT EVT, LoadSDNode *&LDBase, + EVT EVT, LoadSDNode *&LDBase, unsigned &LastLoadedElt, SelectionDAG &DAG, MachineFrameInfo *MFI, const TargetLowering &TLI) { @@ -7985,8 +7985,8 @@ static bool EltsFromConsecutiveLoads(ShuffleVectorSDNode *N, unsigned NumElems, static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, const TargetLowering &TLI) { DebugLoc dl = N->getDebugLoc(); - MVT VT = N->getValueType(0); - MVT EVT = VT.getVectorElementType(); + EVT VT = N->getValueType(0); + EVT EVT = VT.getVectorElementType(); ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); unsigned NumElems = VT.getVectorNumElements(); @@ -8010,7 +8010,7 @@ static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, LD->getSrcValue(), LD->getSrcValueOffset(), LD->isVolatile(), LD->getAlignment()); } else if (NumElems == 4 && LastLoadedElt == 1) { - SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); + SDVTList Tys = DAG.getVTList(EVT::v2i64, EVT::Other); SDValue Ops[] = { LD->getChain(), LD->getBasePtr() }; SDValue ResNode = DAG.getNode(X86ISD::VZEXT_LOAD, dl, Tys, Ops, 2); return DAG.getNode(ISD::BIT_CONVERT, dl, VT, ResNode); @@ -8029,7 +8029,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // If we have SSE[12] support, try to form min/max nodes. if (Subtarget->hasSSE2() && - (LHS.getValueType() == MVT::f32 || LHS.getValueType() == MVT::f64) && + (LHS.getValueType() == EVT::f32 || LHS.getValueType() == EVT::f64) && Cond.getOpcode() == ISD::SETCC) { ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); @@ -8117,7 +8117,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, unsigned ShAmt = TrueC->getAPIntValue().logBase2(); return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, - DAG.getConstant(ShAmt, MVT::i8)); + DAG.getConstant(ShAmt, EVT::i8)); } // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. @@ -8135,9 +8135,9 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, // Optimize cases that will turn into an LEA instruction. This requires // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). - if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { + if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) { uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); - if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; + if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff; bool isFastMultiplier = false; if (Diff < 10) { @@ -8210,15 +8210,15 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, // shift amount. if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { SDValue Cond = N->getOperand(3); - Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, - DAG.getConstant(CC, MVT::i8), Cond); + Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8, + DAG.getConstant(CC, EVT::i8), Cond); // Zero extend the condition if needed. Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); unsigned ShAmt = TrueC->getAPIntValue().logBase2(); Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, - DAG.getConstant(ShAmt, MVT::i8)); + DAG.getConstant(ShAmt, EVT::i8)); if (N->getNumValues() == 2) // Dead flag value? return DCI.CombineTo(N, Cond, SDValue()); return Cond; @@ -8228,8 +8228,8 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, // for any integer data type, including i8/i16. if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { SDValue Cond = N->getOperand(3); - Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, - DAG.getConstant(CC, MVT::i8), Cond); + Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8, + DAG.getConstant(CC, EVT::i8), Cond); // Zero extend the condition if needed. Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, @@ -8244,9 +8244,9 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, // Optimize cases that will turn into an LEA instruction. This requires // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). - if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { + if (N->getValueType(0) == EVT::i32 || N->getValueType(0) == EVT::i64) { uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); - if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; + if (N->getValueType(0) == EVT::i32) Diff = (unsigned)Diff; bool isFastMultiplier = false; if (Diff < 10) { @@ -8267,8 +8267,8 @@ static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, if (isFastMultiplier) { APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); SDValue Cond = N->getOperand(3); - Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, - DAG.getConstant(CC, MVT::i8), Cond); + Cond = DAG.getNode(X86ISD::SETCC, DL, EVT::i8, + DAG.getConstant(CC, EVT::i8), Cond); // Zero extend the condition if needed. Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), Cond); @@ -8304,8 +8304,8 @@ static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) return SDValue(); - MVT VT = N->getValueType(0); - if (VT != MVT::i64) + EVT VT = N->getValueType(0); + if (VT != EVT::i64) return SDValue(); ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); @@ -8341,14 +8341,14 @@ static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, SDValue NewMul; if (isPowerOf2_64(MulAmt1)) NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), - DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); + DAG.getConstant(Log2_64(MulAmt1), EVT::i8)); else NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), DAG.getConstant(MulAmt1, VT)); if (isPowerOf2_64(MulAmt2)) NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, - DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); + DAG.getConstant(Log2_64(MulAmt2), EVT::i8)); else NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, DAG.getConstant(MulAmt2, VT)); @@ -8371,12 +8371,12 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, if (!Subtarget->hasSSE2()) return SDValue(); - MVT VT = N->getValueType(0); - if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) + EVT VT = N->getValueType(0); + if (VT != EVT::v2i64 && VT != EVT::v4i32 && VT != EVT::v8i16) return SDValue(); SDValue ShAmtOp = N->getOperand(1); - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); DebugLoc DL = N->getDebugLoc(); SDValue BaseShAmt; if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { @@ -8402,10 +8402,10 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, } else return SDValue(); - if (EltVT.bitsGT(MVT::i32)) - BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); - else if (EltVT.bitsLT(MVT::i32)) - BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt); + if (EltVT.bitsGT(EVT::i32)) + BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, EVT::i32, BaseShAmt); + else if (EltVT.bitsLT(EVT::i32)) + BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, EVT::i32, BaseShAmt); // The shift amount is identical so we can do a vector shift. SDValue ValOp = N->getOperand(0); @@ -8414,41 +8414,41 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, llvm_unreachable("Unknown shift opcode!"); break; case ISD::SHL: - if (VT == MVT::v2i64) + if (VT == EVT::v2i64) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pslli_q, EVT::i32), ValOp, BaseShAmt); - if (VT == MVT::v4i32) + if (VT == EVT::v4i32) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pslli_d, EVT::i32), ValOp, BaseShAmt); - if (VT == MVT::v8i16) + if (VT == EVT::v8i16) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_pslli_w, EVT::i32), ValOp, BaseShAmt); break; case ISD::SRA: - if (VT == MVT::v4i32) + if (VT == EVT::v4i32) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_psrai_d, EVT::i32), ValOp, BaseShAmt); - if (VT == MVT::v8i16) + if (VT == EVT::v8i16) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_psrai_w, EVT::i32), ValOp, BaseShAmt); break; case ISD::SRL: - if (VT == MVT::v2i64) + if (VT == EVT::v2i64) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_psrli_q, EVT::i32), ValOp, BaseShAmt); - if (VT == MVT::v4i32) + if (VT == EVT::v4i32) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_psrli_d, EVT::i32), ValOp, BaseShAmt); - if (VT == MVT::v8i16) + if (VT == EVT::v8i16) return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, - DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), + DAG.getConstant(Intrinsic::x86_sse2_psrli_w, EVT::i32), ValOp, BaseShAmt); break; } @@ -8465,7 +8465,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. StoreSDNode *St = cast<StoreSDNode>(N); - MVT VT = St->getValue().getValueType(); + EVT VT = St->getValue().getValueType(); if (VT.getSizeInBits() != 64) return SDValue(); @@ -8474,7 +8474,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps && Subtarget->hasSSE2(); if ((VT.isVector() || - (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && + (VT == EVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && isa<LoadSDNode>(St->getValue()) && !cast<LoadSDNode>(St->getValue())->isVolatile() && St->getChain().hasOneUse() && !St->isVolatile()) { @@ -8514,7 +8514,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store // pair instead. if (Subtarget->is64Bit() || F64IsLegal) { - MVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; + EVT LdVT = Subtarget->is64Bit() ? EVT::i64 : EVT::f64; SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), @@ -8522,7 +8522,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, SDValue NewChain = NewLd.getValue(1); if (TokenFactorIndex != -1) { Ops.push_back(NewChain); - NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], + NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0], Ops.size()); } return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), @@ -8532,13 +8532,13 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, // Otherwise, lower to two pairs of 32-bit loads / stores. SDValue LoAddr = Ld->getBasePtr(); - SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, - DAG.getConstant(4, MVT::i32)); + SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, EVT::i32, LoAddr, + DAG.getConstant(4, EVT::i32)); - SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, + SDValue LoLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), LoAddr, Ld->getSrcValue(), Ld->getSrcValueOffset(), Ld->isVolatile(), Ld->getAlignment()); - SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, + SDValue HiLd = DAG.getLoad(EVT::i32, LdDL, Ld->getChain(), HiAddr, Ld->getSrcValue(), Ld->getSrcValueOffset()+4, Ld->isVolatile(), MinAlign(Ld->getAlignment(), 4)); @@ -8547,13 +8547,13 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, if (TokenFactorIndex != -1) { Ops.push_back(LoLd); Ops.push_back(HiLd); - NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], + NewChain = DAG.getNode(ISD::TokenFactor, LdDL, EVT::Other, &Ops[0], Ops.size()); } LoAddr = St->getBasePtr(); - HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, - DAG.getConstant(4, MVT::i32)); + HiAddr = DAG.getNode(ISD::ADD, StDL, EVT::i32, LoAddr, + DAG.getConstant(4, EVT::i32)); SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, St->getSrcValue(), St->getSrcValueOffset(), @@ -8563,7 +8563,7 @@ static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, St->getSrcValueOffset() + 4, St->isVolatile(), MinAlign(St->getAlignment(), 4)); - return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); + return DAG.getNode(ISD::TokenFactor, StDL, EVT::Other, LoSt, HiSt); } return SDValue(); } @@ -8618,7 +8618,7 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { SDValue Op = N->getOperand(0); if (Op.getOpcode() == ISD::BIT_CONVERT) Op = Op.getOperand(0); - MVT VT = N->getValueType(0), OpVT = Op.getValueType(); + EVT VT = N->getValueType(0), OpVT = Op.getValueType(); if (Op.getOpcode() == X86ISD::VZEXT_LOAD && VT.getVectorElementType().getSizeInBits() == OpVT.getVectorElementType().getSizeInBits()) { @@ -8833,7 +8833,7 @@ X86TargetLowering::getConstraintType(const std::string &Constraint) const { /// with another that has more specific requirements based on the type of the /// corresponding operand. const char *X86TargetLowering:: -LowerXConstraint(MVT ConstraintVT) const { +LowerXConstraint(EVT ConstraintVT) const { // FP X constraints get lowered to SSE1/2 registers if available, otherwise // 'f' like normal targets. if (ConstraintVT.isFloatingPoint()) { @@ -8895,7 +8895,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, const ConstantInt *CI = C->getConstantIntValue(); if (CI->isValueValidForType(Type::Int32Ty, C->getSExtValue())) { // Widen to 64 bits here to get it sign extended. - Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); + Result = DAG.getTargetConstant(C->getSExtValue(), EVT::i64); break; } // FIXME gcc accepts some relocatable values here too, but only in certain @@ -8920,7 +8920,7 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, // Literal immediates are always ok. if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { // Widen to 64 bits here to get it sign extended. - Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); + Result = DAG.getTargetConstant(CST->getSExtValue(), EVT::i64); break; } @@ -8978,33 +8978,33 @@ void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, std::vector<unsigned> X86TargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { if (Constraint.size() == 1) { // FIXME: not handling fp-stack yet! switch (Constraint[0]) { // GCC X86 Constraint Letters default: break; // Unknown constraint letter case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. if (Subtarget->is64Bit()) { - if (VT == MVT::i32) + if (VT == EVT::i32) return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, X86::ESI, X86::EDI, X86::R8D, X86::R9D, X86::R10D,X86::R11D,X86::R12D, X86::R13D,X86::R14D,X86::R15D, X86::EBP, X86::ESP, 0); - else if (VT == MVT::i16) + else if (VT == EVT::i16) return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, X86::SI, X86::DI, X86::R8W,X86::R9W, X86::R10W,X86::R11W,X86::R12W, X86::R13W,X86::R14W,X86::R15W, X86::BP, X86::SP, 0); - else if (VT == MVT::i8) + else if (VT == EVT::i8) return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, X86::SIL, X86::DIL, X86::R8B,X86::R9B, X86::R10B,X86::R11B,X86::R12B, X86::R13B,X86::R14B,X86::R15B, X86::BPL, X86::SPL, 0); - else if (VT == MVT::i64) + else if (VT == EVT::i64) return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, X86::RSI, X86::RDI, X86::R8, X86::R9, X86::R10, X86::R11, X86::R12, @@ -9015,13 +9015,13 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, } // 32-bit fallthrough case 'Q': // Q_REGS - if (VT == MVT::i32) + if (VT == EVT::i32) return make_vector<unsigned>(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); - else if (VT == MVT::i16) + else if (VT == EVT::i16) return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0); - else if (VT == MVT::i8) + else if (VT == EVT::i8) return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0); - else if (VT == MVT::i64) + else if (VT == EVT::i64) return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); break; } @@ -9032,7 +9032,7 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint, std::pair<unsigned, const TargetRegisterClass*> X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const { + EVT VT) const { // First, see if this is a constraint that directly corresponds to an LLVM // register class. if (Constraint.size() == 1) { @@ -9042,19 +9042,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, case 'r': // GENERAL_REGS case 'R': // LEGACY_REGS case 'l': // INDEX_REGS - if (VT == MVT::i8) + if (VT == EVT::i8) return std::make_pair(0U, X86::GR8RegisterClass); - if (VT == MVT::i16) + if (VT == EVT::i16) return std::make_pair(0U, X86::GR16RegisterClass); - if (VT == MVT::i32 || !Subtarget->is64Bit()) + if (VT == EVT::i32 || !Subtarget->is64Bit()) return std::make_pair(0U, X86::GR32RegisterClass); return std::make_pair(0U, X86::GR64RegisterClass); case 'f': // FP Stack registers. // If SSE is enabled for this VT, use f80 to ensure the isel moves the // value to the correct fpstack register class. - if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) + if (VT == EVT::f32 && !isScalarFPTypeInSSEReg(VT)) return std::make_pair(0U, X86::RFP32RegisterClass); - if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) + if (VT == EVT::f64 && !isScalarFPTypeInSSEReg(VT)) return std::make_pair(0U, X86::RFP64RegisterClass); return std::make_pair(0U, X86::RFP80RegisterClass); case 'y': // MMX_REGS if MMX allowed. @@ -9069,19 +9069,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, switch (VT.getSimpleVT()) { default: break; // Scalar SSE types. - case MVT::f32: - case MVT::i32: + case EVT::f32: + case EVT::i32: return std::make_pair(0U, X86::FR32RegisterClass); - case MVT::f64: - case MVT::i64: + case EVT::f64: + case EVT::i64: return std::make_pair(0U, X86::FR64RegisterClass); // Vector types. - case MVT::v16i8: - case MVT::v8i16: - case MVT::v4i32: - case MVT::v2i64: - case MVT::v4f32: - case MVT::v2f64: + case EVT::v16i8: + case EVT::v8i16: + case EVT::v4i32: + case EVT::v2i64: + case EVT::v4f32: + case EVT::v2f64: return std::make_pair(0U, X86::VR128RegisterClass); } break; @@ -9119,7 +9119,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, // really want an 8-bit or 32-bit register, map to the appropriate register // class and return the appropriate register. if (Res.second == X86::GR16RegisterClass) { - if (VT == MVT::i8) { + if (VT == EVT::i8) { unsigned DestReg = 0; switch (Res.first) { default: break; @@ -9132,7 +9132,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, Res.first = DestReg; Res.second = X86::GR8RegisterClass; } - } else if (VT == MVT::i32) { + } else if (VT == EVT::i32) { unsigned DestReg = 0; switch (Res.first) { default: break; @@ -9149,7 +9149,7 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, Res.first = DestReg; Res.second = X86::GR32RegisterClass; } - } else if (VT == MVT::i64) { + } else if (VT == EVT::i64) { unsigned DestReg = 0; switch (Res.first) { default: break; @@ -9174,9 +9174,9 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, // wrong class. This can happen with constraints like {xmm0} where the // target independent register mapper will just pick the first match it can // find, ignoring the required type. - if (VT == MVT::f32) + if (VT == EVT::f32) Res.second = X86::FR32RegisterClass; - else if (VT == MVT::f64) + else if (VT == EVT::f64) Res.second = X86::FR64RegisterClass; else if (X86::VR128RegisterClass->hasType(VT)) Res.second = X86::VR128RegisterClass; @@ -9191,11 +9191,11 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, /// getWidenVectorType: given a vector type, returns the type to widen /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. -/// If there is no vector type that we want to widen to, returns MVT::Other +/// If there is no vector type that we want to widen to, returns EVT::Other /// When and where to widen is target dependent based on the cost of /// scalarizing vs using the wider vector type. -MVT X86TargetLowering::getWidenVectorType(MVT VT) const { +EVT X86TargetLowering::getWidenVectorType(EVT VT) const { assert(VT.isVector()); if (isTypeLegal(VT)) return VT; @@ -9204,21 +9204,21 @@ MVT X86TargetLowering::getWidenVectorType(MVT VT) const { // type based on element type. This would speed up our search (though // it may not be worth it since the size of the list is relatively // small). - MVT EltVT = VT.getVectorElementType(); + EVT EltVT = VT.getVectorElementType(); unsigned NElts = VT.getVectorNumElements(); // On X86, it make sense to widen any vector wider than 1 if (NElts <= 1) - return MVT::Other; + return EVT::Other; - for (unsigned nVT = MVT::FIRST_VECTOR_VALUETYPE; - nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { - MVT SVT = (MVT::SimpleValueType)nVT; + for (unsigned nVT = EVT::FIRST_VECTOR_VALUETYPE; + nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) { + EVT SVT = (EVT::SimpleValueType)nVT; if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts) return SVT; } - return MVT::Other; + return EVT::Other; } diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 459b7be56d..d9c745b3b3 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -382,10 +382,10 @@ namespace llvm { /// getOptimalMemOpType - Returns the target specific optimal type for load /// and store operations as a result of memset, memcpy, and memmove - /// lowering. It returns MVT::iAny if SelectionDAG should be responsible for + /// lowering. It returns EVT::iAny if SelectionDAG should be responsible for /// determining it. virtual - MVT getOptimalMemOpType(uint64_t Size, unsigned Align, + EVT getOptimalMemOpType(uint64_t Size, unsigned Align, bool isSrcConst, bool isSrcStr, SelectionDAG &DAG) const; @@ -411,7 +411,7 @@ namespace llvm { virtual const char *getTargetNodeName(unsigned Opcode) const; /// getSetCCResultType - Return the ISD::SETCC ValueType - virtual MVT::SimpleValueType getSetCCResultType(MVT VT) const; + virtual EVT::SimpleValueType getSetCCResultType(EVT VT) const; /// computeMaskedBitsForTargetNode - Determine which of the bits specified /// in Mask are known to be either zero or one and return them in the @@ -434,9 +434,9 @@ namespace llvm { std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; - virtual const char *LowerXConstraint(MVT ConstraintVT) const; + virtual const char *LowerXConstraint(EVT ConstraintVT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. If hasMemory is @@ -454,7 +454,7 @@ namespace llvm { /// error, this returns a register number of 0. std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; /// isLegalAddressingMode - Return true if the addressing mode represented /// by AM is legal for this target, for a load/store of the specified type. @@ -464,7 +464,7 @@ namespace llvm { /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in /// register EAX to i16 by referencing its sub-register AX. virtual bool isTruncateFree(const Type *Ty1, const Type *Ty2) const; - virtual bool isTruncateFree(MVT VT1, MVT VT2) const; + virtual bool isTruncateFree(EVT VT1, EVT VT2) const; /// isZExtFree - Return true if any actual instruction that defines a /// value of type Ty1 implicit zero-extends the value to Ty2 in the result @@ -475,35 +475,35 @@ namespace llvm { /// all instructions that define 32-bit values implicit zero-extend the /// result out to 64 bits. virtual bool isZExtFree(const Type *Ty1, const Type *Ty2) const; - virtual bool isZExtFree(MVT VT1, MVT VT2) const; + virtual bool isZExtFree(EVT VT1, EVT VT2) const; /// isNarrowingProfitable - Return true if it's profitable to narrow /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow /// from i32 to i8 but not from i32 to i16. - virtual bool isNarrowingProfitable(MVT VT1, MVT VT2) const; + virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const; /// isShuffleMaskLegal - Targets can use this to indicate that they only /// support *some* VECTOR_SHUFFLE operations, those with specific masks. /// By default, if a target supports the VECTOR_SHUFFLE node, all mask /// values are assumed to be legal. virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask, - MVT VT) const; + EVT VT) const; /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is /// used by Targets can use this to indicate if there is a suitable /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant /// pool entry. virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, - MVT VT) const; + EVT VT) const; /// ShouldShrinkFPConstant - If true, then instruction selection should /// seek to shrink the FP constant of the specified type to a smaller type /// in order to save space and / or reduce runtime. - virtual bool ShouldShrinkFPConstant(MVT VT) const { + virtual bool ShouldShrinkFPConstant(EVT VT) const { // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more // expensive than a straight movsd. On the other hand, it's important to // shrink long double fp constant since fldt is very slow. - return !X86ScalarSSEf64 || VT == MVT::f80; + return !X86ScalarSSEf64 || VT == EVT::f80; } /// IsEligibleForTailCallOptimization - Check whether the call is eligible @@ -522,17 +522,17 @@ namespace llvm { /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is /// computed in an SSE register, not on the X87 floating point stack. - bool isScalarFPTypeInSSEReg(MVT VT) const { - return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 - (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 + bool isScalarFPTypeInSSEReg(EVT VT) const { + return (VT == EVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 + (VT == EVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 } /// getWidenVectorType: given a vector type, returns the type to widen /// to (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself. - /// If there is no vector type that we want to widen to, returns MVT::Other + /// If there is no vector type that we want to widen to, returns EVT::Other /// When and were to widen is target dependent based on the cost of /// scalarizing vs using the wider vector type. - virtual MVT getWidenVectorType(MVT VT) const; + virtual EVT getWidenVectorType(EVT VT) const; /// createFastISel - This method returns a target specific FastISel object, /// or null if the target does not support "fast" ISel. @@ -610,7 +610,7 @@ namespace llvm { SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG); SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG); SDValue LowerShift(SDValue Op, SelectionDAG &DAG); - SDValue BuildFILD(SDValue Op, MVT SrcVT, SDValue Chain, SDValue StackSlot, + SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot, SelectionDAG &DAG); SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG); SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG); diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index b59f8e854c..79bd0af99e 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2525,24 +2525,24 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, SDNode *Load = 0; const MachineFunction &MF = DAG.getMachineFunction(); if (FoldedLoad) { - MVT VT = *RC->vt_begin(); + EVT VT = *RC->vt_begin(); bool isAligned = (RI.getStackAlignment() >= 16) || RI.needsStackRealignment(MF); Load = DAG.getTargetNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, - VT, MVT::Other, &AddrOps[0], AddrOps.size()); + VT, EVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Load); } // Emit the data processing instruction. - std::vector<MVT> VTs; + std::vector<EVT> VTs; const TargetRegisterClass *DstRC = 0; if (TID.getNumDefs() > 0) { DstRC = TID.OpInfo[0].getRegClass(&RI); VTs.push_back(*DstRC->vt_begin()); } for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { - MVT VT = N->getValueType(i); - if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) + EVT VT = N->getValueType(i); + if (VT != EVT::Other && i >= (unsigned)TID.getNumDefs()) VTs.push_back(VT); } if (Load) @@ -2561,7 +2561,7 @@ X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, RI.needsStackRealignment(MF); SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(0, DstRC, isAligned, TM), - dl, MVT::Other, + dl, EVT::Other, &AddrOps[0], AddrOps.size()); NewNodes.push_back(Store); } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index cae62905d3..09457a13b8 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -1262,10 +1262,10 @@ unsigned X86RegisterInfo::getEHHandlerRegister() const { } namespace llvm { -unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { +unsigned getX86SubSuperRegister(unsigned Reg, EVT VT, bool High) { switch (VT.getSimpleVT()) { default: return Reg; - case MVT::i8: + case EVT::i8: if (High) { switch (Reg) { default: return 0; @@ -1315,7 +1315,7 @@ unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { return X86::R15B; } } - case MVT::i16: + case EVT::i16: switch (Reg) { default: return Reg; case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: @@ -1351,7 +1351,7 @@ unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: return X86::R15W; } - case MVT::i32: + case EVT::i32: switch (Reg) { default: return Reg; case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: @@ -1387,7 +1387,7 @@ unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { case X86::R15B: case X86::R15W: case X86::R15D: case X86::R15: return X86::R15D; } - case MVT::i64: + case EVT::i64: switch (Reg) { default: return Reg; case X86::AH: case X86::AL: case X86::AX: case X86::EAX: case X86::RAX: diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index f6c119d18a..c89a57cd58 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -163,8 +163,8 @@ public: // getX86SubSuperRegister - X86 utility function. It returns the sub or super // register of a specific X86 register. -// e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX -unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false); +// e.g. getX86SubSuperRegister(X86::EAX, EVT::i16) return X86:AX +unsigned getX86SubSuperRegister(unsigned, EVT, bool High=false); } // End llvm namespace diff --git a/lib/Target/XCore/XCoreISelDAGToDAG.cpp b/lib/Target/XCore/XCoreISelDAGToDAG.cpp index ebd0a261b8..750747d7d2 100644 --- a/lib/Target/XCore/XCoreISelDAGToDAG.cpp +++ b/lib/Target/XCore/XCoreISelDAGToDAG.cpp @@ -54,7 +54,7 @@ namespace { /// getI32Imm - Return a target constant with the specified value, of type /// i32. inline SDValue getI32Imm(unsigned Imm) { - return CurDAG->getTargetConstant(Imm, MVT::i32); + return CurDAG->getTargetConstant(Imm, EVT::i32); } // Complex Pattern Selectors. @@ -87,8 +87,8 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Offset) { FrameIndexSDNode *FIN = 0; if ((FIN = dyn_cast<FrameIndexSDNode>(Addr))) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } if (Addr.getOpcode() == ISD::ADD) { @@ -97,8 +97,8 @@ bool XCoreDAGToDAGISel::SelectADDRspii(SDValue Op, SDValue Addr, && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) { // Constant positive word offset from frame index - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), EVT::i32); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32); return true; } } @@ -109,7 +109,7 @@ bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Offset) { if (Addr.getOpcode() == XCoreISD::DPRelativeWrapper) { Base = Addr.getOperand(0); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } if (Addr.getOpcode() == ISD::ADD) { @@ -119,7 +119,7 @@ bool XCoreDAGToDAGISel::SelectADDRdpii(SDValue Op, SDValue Addr, && (CN->getSExtValue() % 4 == 0)) { // Constant word offset from a object in the data region Base = Addr.getOperand(0).getOperand(0); - Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32); return true; } } @@ -130,7 +130,7 @@ bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Op, SDValue Addr, SDValue &Base, SDValue &Offset) { if (Addr.getOpcode() == XCoreISD::CPRelativeWrapper) { Base = Addr.getOperand(0); - Offset = CurDAG->getTargetConstant(0, MVT::i32); + Offset = CurDAG->getTargetConstant(0, EVT::i32); return true; } if (Addr.getOpcode() == ISD::ADD) { @@ -140,7 +140,7 @@ bool XCoreDAGToDAGISel::SelectADDRcpii(SDValue Op, SDValue Addr, && (CN->getSExtValue() % 4 == 0)) { // Constant word offset from a object in the data region Base = Addr.getOperand(0).getOperand(0); - Offset = CurDAG->getTargetConstant(CN->getSExtValue(), MVT::i32); + Offset = CurDAG->getTargetConstant(CN->getSExtValue(), EVT::i32); return true; } } @@ -162,22 +162,22 @@ InstructionSelect() { SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { SDNode *N = Op.getNode(); DebugLoc dl = N->getDebugLoc(); - MVT NVT = N->getValueType(0); - if (NVT == MVT::i32) { + EVT NVT = N->getValueType(0); + if (NVT == EVT::i32) { switch (N->getOpcode()) { default: break; case ISD::Constant: { if (Predicate_immMskBitp(N)) { SDValue MskSize = Transform_msksize_xform(N); - return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, MVT::i32, MskSize); + return CurDAG->getTargetNode(XCore::MKMSK_rus, dl, EVT::i32, MskSize); } else if (! Predicate_immU16(N)) { unsigned Val = cast<ConstantSDNode>(N)->getZExtValue(); SDValue CPIdx = CurDAG->getTargetConstantPool(ConstantInt::get(Type::Int32Ty, Val), TLI.getPointerTy()); - return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, MVT::i32, - MVT::Other, CPIdx, + return CurDAG->getTargetNode(XCore::LDWCP_lru6, dl, EVT::i32, + EVT::Other, CPIdx, CurDAG->getEntryNode()); } break; @@ -185,11 +185,11 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { case ISD::SMUL_LOHI: { // FIXME fold addition into the macc instruction if (!Subtarget.isXS1A()) { - SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32, - CurDAG->getTargetConstant(0, MVT::i32)), 0); + SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, EVT::i32, + CurDAG->getTargetConstant(0, EVT::i32)), 0); SDValue Ops[] = { Zero, Zero, Op.getOperand(0), Op.getOperand(1) }; SDNode *ResNode = CurDAG->getTargetNode(XCore::MACCS_l4r, dl, - MVT::i32, MVT::i32, Ops, 4); + EVT::i32, EVT::i32, Ops, 4); ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1)); ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0)); return NULL; @@ -198,12 +198,12 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { } case ISD::UMUL_LOHI: { // FIXME fold addition into the macc / lmul instruction - SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, MVT::i32, - CurDAG->getTargetConstant(0, MVT::i32)), 0); + SDValue Zero(CurDAG->getTargetNode(XCore::LDC_ru6, dl, EVT::i32, + CurDAG->getTargetConstant(0, EVT::i32)), 0); SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Zero, Zero }; - SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, MVT::i32, - MVT::i32, Ops, 4); + SDNode *ResNode = CurDAG->getTargetNode(XCore::LMUL_l6r, dl, EVT::i32, + EVT::i32, Ops, 4); ReplaceUses(SDValue(N, 0), SDValue(ResNode, 1)); ReplaceUses(SDValue(N, 1), SDValue(ResNode, 0)); return NULL; @@ -212,7 +212,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) }; - return CurDAG->getTargetNode(XCore::LADD_l5r, dl, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(XCore::LADD_l5r, dl, EVT::i32, EVT::i32, Ops, 3); } break; @@ -221,7 +221,7 @@ SDNode *XCoreDAGToDAGISel::Select(SDValue Op) { if (!Subtarget.isXS1A()) { SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1), Op.getOperand(2) }; - return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, MVT::i32, MVT::i32, + return CurDAG->getTargetNode(XCore::LSUB_l5r, dl, EVT::i32, EVT::i32, Ops, 3); } break; diff --git a/lib/Target/XCore/XCoreISelLowering.cpp b/lib/Target/XCore/XCoreISelLowering.cpp index 38648e0b7e..cc1f1f7105 100644 --- a/lib/Target/XCore/XCoreISelLowering.cpp +++ b/lib/Target/XCore/XCoreISelLowering.cpp @@ -61,7 +61,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) Subtarget(*XTM.getSubtargetImpl()) { // Set up the register classes. - addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass); + addRegisterClass(EVT::i32, XCore::GRRegsRegisterClass); // Compute derived properties from the register classes computeRegisterProperties(); @@ -69,7 +69,7 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) // Division is expensive setIntDivIsCheap(false); - setShiftAmountType(MVT::i32); + setShiftAmountType(EVT::i32); setStackPointerRegisterToSaveRestore(XCore::SP); setSchedulingPreference(SchedulingForRegPressure); @@ -78,75 +78,75 @@ XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM) setBooleanContents(ZeroOrOneBooleanContent); // XCore does not have the NodeTypes below. - setOperationAction(ISD::BR_CC, MVT::Other, Expand); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - setOperationAction(ISD::ADDC, MVT::i32, Expand); - setOperationAction(ISD::ADDE, MVT::i32, Expand); - setOperationAction(ISD::SUBC, MVT::i32, Expand); - setOperationAction(ISD::SUBE, MVT::i32, Expand); + setOperationAction(ISD::BR_CC, EVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::i32, Custom); + setOperationAction(ISD::ADDC, EVT::i32, Expand); + setOperationAction(ISD::ADDE, EVT::i32, Expand); + setOperationAction(ISD::SUBC, EVT::i32, Expand); + setOperationAction(ISD::SUBE, EVT::i32, Expand); // Stop the combiner recombining select and set_cc - setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); + setOperationAction(ISD::SELECT_CC, EVT::Other, Expand); // 64bit if (!Subtarget.isXS1A()) { - setOperationAction(ISD::ADD, MVT::i64, Custom); - setOperationAction(ISD::SUB, MVT::i64, Custom); + setOperationAction(ISD::ADD, EVT::i64, Custom); + setOperationAction(ISD::SUB, EVT::i64, Custom); } if (Subtarget.isXS1A()) { - setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand); + setOperationAction(ISD::SMUL_LOHI, EVT::i32, Expand); } - setOperationAction(ISD::MULHS, MVT::i32, Expand); - setOperationAction(ISD::MULHU, MVT::i32, Expand); - setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); - setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); + setOperationAction(ISD::MULHS, EVT::i32, Expand); + setOperationAction(ISD::MULHU, EVT::i32, Expand); + setOperationAction(ISD::SHL_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRA_PARTS, EVT::i32, Expand); + setOperationAction(ISD::SRL_PARTS, EVT::i32, Expand); // Bit Manipulation - setOperationAction(ISD::CTPOP, MVT::i32, Expand); - setOperationAction(ISD::ROTL , MVT::i32, Expand); - setOperationAction(ISD::ROTR , MVT::i32, Expand); + setOperationAction(ISD::CTPOP, EVT::i32, Expand); + setOperationAction(ISD::ROTL , EVT::i32, Expand); + setOperationAction(ISD::ROTR , EVT::i32, Expand); - setOperationAction(ISD::TRAP, MVT::Other, Legal); + setOperationAction(ISD::TRAP, EVT::Other, Legal); // Expand jump tables for now - setOperationAction(ISD::BR_JT, MVT::Other, Expand); - setOperationAction(ISD::JumpTable, MVT::i32, Custom); + setOperationAction(ISD::BR_JT, EVT::Other, Expand); + setOperationAction(ISD::JumpTable, EVT::i32, Custom); - setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalAddress, EVT::i32, Custom); // Thread Local Storage - setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); + setOperationAction(ISD::GlobalTLSAddress, EVT::i32, Custom); // Conversion of i64 -> double produces constantpool nodes - setOperationAction(ISD::ConstantPool, MVT::i32, Custom); + setOperationAction(ISD::ConstantPool, EVT::i32, Custom); // Loads - setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i1, Promote); + setLoadExtAction(ISD::SEXTLOAD, EVT::i1, Promote); - setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); - setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand); + setLoadExtAction(ISD::SEXTLOAD, EVT::i8, Expand); + setLoadExtAction(ISD::ZEXTLOAD, EVT::i16, Expand); // Custom expand misaligned loads / stores. - setOperationAction(ISD::LOAD, MVT::i32, Custom); - setOperationAction(ISD::STORE, MVT::i32, Custom); + setOperationAction(ISD::LOAD, EVT::i32, Custom); + setOperationAction(ISD::STORE, EVT::i32, Custom); // Varargs - setOperationAction(ISD::VAEND, MVT::Other, Expand); - setOperationAction(ISD::VACOPY, MVT::Other, Expand); - setOperationAction(ISD::VAARG, MVT::Other, Custom); - setOperationAction(ISD::VASTART, MVT::Other, Custom); + setOperationAction(ISD::VAEND, EVT::Other, Expand); + setOperationAction(ISD::VACOPY, EVT::Other, Expand); + setOperationAction(ISD::VAARG, EVT::Other, Custom); + setOperationAction(ISD::VASTART, EVT::Other, Custom); // Dynamic stack - setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); - setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::STACKSAVE, EVT::Other, Expand); + setOperationAction(ISD::STACKRESTORE, EVT::Other, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, EVT::i32, Expand); // Debug - setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand); - setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand); + setOperationAction(ISD::DBG_STOPPOINT, EVT::Other, Expand); + setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand); maxStoresPerMemset = 4; maxStoresPerMemmove = maxStoresPerMemcpy = 2; @@ -208,9 +208,9 @@ SDValue XCoreTargetLowering:: LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); - SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2), + SDValue Cond = DAG.getNode(ISD::SETCC, dl, EVT::i32, Op.getOperand(2), Op.getOperand(3), Op.getOperand(4)); - return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0), + return DAG.getNode(ISD::SELECT, dl, EVT::i32, Cond, Op.getOperand(0), Op.getOperand(1)); } @@ -220,7 +220,7 @@ getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG) // FIXME there is no actual debug info here DebugLoc dl = GA.getDebugLoc(); if (isa<Function>(GV)) { - return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA); + return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, EVT::i32, GA); } else if (!Subtarget.isXS1A()) { const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); if (!GVar) { @@ -230,17 +230,17 @@ getGlobalAddressWrapper(SDValue GA, GlobalValue *GV, SelectionDAG &DAG) } bool isConst = GVar && GVar->isConstant(); if (isConst) { - return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA); + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, EVT::i32, GA); } } - return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA); + return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, EVT::i32, GA); } SDValue XCoreTargetLowering:: LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) { GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32); // If it's a debug information descriptor, don't mess with it. if (DAG.isVerifiedDebugInfoDesc(Op)) return GA; @@ -248,8 +248,8 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) } static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) { - return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, - DAG.getConstant(Intrinsic::xcore_getid, MVT::i32)); + return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, EVT::i32, + DAG.getConstant(Intrinsic::xcore_getid, EVT::i32)); } static inline bool isZeroLengthArray(const Type *Ty) { @@ -264,7 +264,7 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) DebugLoc dl = Op.getDebugLoc(); // transform to label + getid() * size GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); - SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32); + SDValue GA = DAG.getTargetGlobalAddress(GV, EVT::i32); const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); if (!GVar) { // If GV is an alias then use the aliasee to determine size @@ -286,9 +286,9 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) SDValue base = getGlobalAddressWrapper(GA, GV, DAG); const TargetData *TD = TM.getTargetData(); unsigned Size = TD->getTypeAllocSize(Ty); - SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl), - DAG.getConstant(Size, MVT::i32)); - return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset); + SDValue offset = DAG.getNode(ISD::MUL, dl, EVT::i32, BuildGetId(DAG, dl), + DAG.getConstant(Size, EVT::i32)); + return DAG.getNode(ISD::ADD, dl, EVT::i32, base, offset); } SDValue XCoreTargetLowering:: @@ -301,7 +301,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) llvm_unreachable("Lowering of constant pool unimplemented"); return SDValue(); } else { - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); SDValue Res; if (CP->isMachineConstantPoolEntry()) { Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT, @@ -310,7 +310,7 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlignment()); } - return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res); + return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, EVT::i32, Res); } } @@ -319,10 +319,10 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) { // FIXME there isn't really debug info here DebugLoc dl = Op.getDebugLoc(); - MVT PtrVT = Op.getValueType(); + EVT PtrVT = Op.getValueType(); JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT); - return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, JTI); + return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, EVT::i32, JTI); } static bool @@ -368,12 +368,12 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) { LoadSDNode *LD = cast<LoadSDNode>(Op); assert(LD->getExtensionType() == ISD::NON_EXTLOAD && "Unexpected extension type"); - assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load MVT"); + assert(LD->getMemoryVT() == EVT::i32 && "Unexpected load EVT"); if (allowsUnalignedMemoryAccesses()) { return SDValue(); } unsigned ABIAlignment = getTargetData()-> - getABITypeAlignment(LD->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(LD->getMemoryVT().getTypeForEVT()); // Leave aligned load alone. if (LD->getAlignment() >= ABIAlignment) { return SDValue(); @@ -397,22 +397,22 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) // shr low_shifted, low, (offset & 0x3) * 8 // shl high_shifted, high, 32 - (offset & 0x3) * 8 // or result, low_shifted, high_shifted - SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32); - SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32); - SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32); - SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32); + SDValue LowOffset = DAG.getConstant(Offset & ~0x3, EVT::i32); + SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, EVT::i32); + SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, EVT::i32); + SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, EVT::i32); - SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset); - SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset); + SDValue LowAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, Base, LowOffset); + SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, Base, HighOffset); SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain, LowAddr, NULL, 4); SDValue High = DAG.getLoad(getPointerTy(), dl, Chain, HighAddr, NULL, 4); - SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift); - SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift); - SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), + SDValue LowShifted = DAG.getNode(ISD::SRL, dl, EVT::i32, Low, LowShift); + SDValue HighShifted = DAG.getNode(ISD::SHL, dl, EVT::i32, High, HighShift); + SDValue Result = DAG.getNode(ISD::OR, dl, EVT::i32, LowShifted, HighShifted); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Low.getValue(1), High.getValue(1)); SDValue Ops[] = { Result, Chain }; return DAG.getMergeValues(Ops, 2, dl); @@ -420,18 +420,18 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) if (LD->getAlignment() == 2) { int SVOffset = LD->getSrcValueOffset(); - SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, - BasePtr, LD->getSrcValue(), SVOffset, MVT::i16, + SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, EVT::i32, Chain, + BasePtr, LD->getSrcValue(), SVOffset, EVT::i16, LD->isVolatile(), 2); - SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, - DAG.getConstant(2, MVT::i32)); - SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain, + SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, BasePtr, + DAG.getConstant(2, EVT::i32)); + SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, EVT::i32, Chain, HighAddr, LD->getSrcValue(), SVOffset + 2, - MVT::i16, LD->isVolatile(), 2); - SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, - DAG.getConstant(16, MVT::i32)); - SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted); - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1), + EVT::i16, LD->isVolatile(), 2); + SDValue HighShifted = DAG.getNode(ISD::SHL, dl, EVT::i32, High, + DAG.getConstant(16, EVT::i32)); + SDValue Result = DAG.getNode(ISD::OR, dl, EVT::i32, Low, HighShifted); + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Low.getValue(1), High.getValue(1)); SDValue Ops[] = { Result, Chain }; return DAG.getMergeValues(Ops, 2, dl); @@ -464,12 +464,12 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) { StoreSDNode *ST = cast<StoreSDNode>(Op); assert(!ST->isTruncatingStore() && "Unexpected store type"); - assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store MVT"); + assert(ST->getMemoryVT() == EVT::i32 && "Unexpected store EVT"); if (allowsUnalignedMemoryAccesses()) { return SDValue(); } unsigned ABIAlignment = getTargetData()-> - getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(ST->getMemoryVT().getTypeForEVT()); // Leave aligned store alone. if (ST->getAlignment() >= ABIAlignment) { return SDValue(); @@ -482,17 +482,17 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) if (ST->getAlignment() == 2) { int SVOffset = ST->getSrcValueOffset(); SDValue Low = Value; - SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value, - DAG.getConstant(16, MVT::i32)); + SDValue High = DAG.getNode(ISD::SRL, dl, EVT::i32, Value, + DAG.getConstant(16, EVT::i32)); SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr, - ST->getSrcValue(), SVOffset, MVT::i16, + ST->getSrcValue(), SVOffset, EVT::i16, ST->isVolatile(), 2); - SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr, - DAG.getConstant(2, MVT::i32)); + SDValue HighAddr = DAG.getNode(ISD::ADD, dl, EVT::i32, BasePtr, + DAG.getConstant(2, EVT::i32)); SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr, ST->getSrcValue(), SVOffset + 2, - MVT::i16, ST->isVolatile(), 2); - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh); + EVT::i16, ST->isVolatile(), 2); + return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, StoreLow, StoreHigh); } // Lower to a call to __misaligned_store(BasePtr, Value). @@ -520,35 +520,35 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) SDValue XCoreTargetLowering:: ExpandADDSUB(SDNode *N, SelectionDAG &DAG) { - assert(N->getValueType(0) == MVT::i64 && + assert(N->getValueType(0) == EVT::i64 && (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) && "Unknown operand to lower!"); assert(!Subtarget.isXS1A() && "Cannot custom lower ADD/SUB on xs1a"); DebugLoc dl = N->getDebugLoc(); // Extract components - SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - N->getOperand(0), DAG.getConstant(0, MVT::i32)); - SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - N->getOperand(0), DAG.getConstant(1, MVT::i32)); - SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - N->getOperand(1), DAG.getConstant(0, MVT::i32)); - SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, - N->getOperand(1), DAG.getConstant(1, MVT::i32)); + SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, + N->getOperand(0), DAG.getConstant(0, EVT::i32)); + SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, + N->getOperand(0), DAG.getConstant(1, EVT::i32)); + SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, + N->getOperand(1), DAG.getConstant(0, EVT::i32)); + SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, EVT::i32, + N->getOperand(1), DAG.getConstant(1, EVT::i32)); // Expand unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD : XCoreISD::LSUB; - SDValue Zero = DAG.getConstant(0, MVT::i32); - SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Zero = DAG.getConstant(0, EVT::i32); + SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(EVT::i32, EVT::i32), LHSL, RHSL, Zero); SDValue Lo(Carry.getNode(), 1); - SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32), + SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(EVT::i32, EVT::i32), LHSH, RHSH, Carry); SDValue Hi(Ignored.getNode(), 1); // Merge the pieces - return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); + return DAG.getNode(ISD::BUILD_PAIR, dl, EVT::i64, Lo, Hi); } SDValue XCoreTargetLowering:: @@ -559,7 +559,7 @@ LowerVAARG(SDValue Op, SelectionDAG &DAG) SDNode *Node = Op.getNode(); DebugLoc dl = Node->getDebugLoc(); const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); - MVT VT = Node->getValueType(0); + EVT VT = Node->getValueType(0); SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0), Node->getOperand(1), V, 0); // Increment the pointer, VAList, to the next vararg @@ -580,7 +580,7 @@ LowerVASTART(SDValue Op, SelectionDAG &DAG) // memory location argument MachineFunction &MF = DAG.getMachineFunction(); XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>(); - SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32); + SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), EVT::i32); const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0); } @@ -594,7 +594,7 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { MachineFunction &MF = DAG.getMachineFunction(); const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo(); return DAG.getCopyFromReg(DAG.getEntryNode(), dl, - RegInfo->getFrameRegister(MF), MVT::i32); + RegInfo->getFrameRegister(MF), EVT::i32); } //===----------------------------------------------------------------------===// @@ -691,16 +691,16 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, int Offset = VA.getLocMemOffset(); - MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other, + MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, EVT::Other, Chain, Arg, - DAG.getConstant(Offset/4, MVT::i32))); + DAG.getConstant(Offset/4, EVT::i32))); } } // Transform all store nodes into one single node because // all store nodes are independent of each other. if (!MemOpChains.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOpChains[0], MemOpChains.size()); // Build a sequence of copy-to-reg nodes chained together with token @@ -718,15 +718,15 @@ XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee, // turn it into a TargetGlobalAddress node so that legalize doesn't hack it. // Likewise ExternalSymbol -> TargetExternalSymbol. if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) - Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32); + Callee = DAG.getTargetGlobalAddress(G->getGlobal(), EVT::i32); else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) - Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), EVT::i32); // XCoreBranchLink = #chain, #target_address, #opt_in_flags... // = Chain, Callee, Reg#1, Reg#2, ... // // Returns a chain & a flag for retval copy to use. - SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag); + SDVTList NodeTys = DAG.getVTList(EVT::Other, EVT::Flag); SmallVector<SDValue, 8> Ops; Ops.push_back(Chain); Ops.push_back(Callee); @@ -841,7 +841,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, if (VA.isRegLoc()) { // Arguments passed in registers - MVT RegVT = VA.getLocVT(); + EVT RegVT = VA.getLocVT(); switch (RegVT.getSimpleVT()) { default: { @@ -851,7 +851,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, #endif llvm_unreachable(0); } - case MVT::i32: + case EVT::i32: unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(VA.getLocReg(), VReg); @@ -873,7 +873,7 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, // Create the SelectionDAG nodes corresponding to a load //from this parameter - SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + SDValue FIN = DAG.getFrameIndex(FI, EVT::i32); InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0)); } } @@ -898,18 +898,18 @@ XCoreTargetLowering::LowerCCCArguments(SDValue Chain, XFI->setVarArgsFrameIndex(FI); } offset -= StackSlotSize; - SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + SDValue FIN = DAG.getFrameIndex(FI, EVT::i32); // Move argument from phys reg -> virt reg unsigned VReg = RegInfo.createVirtualRegister( XCore::GRRegsRegisterClass); RegInfo.addLiveIn(ArgRegs[i], VReg); - SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32); + SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, EVT::i32); // Move argument from virt reg -> stack SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); MemOps.push_back(Store); } if (!MemOps.empty()) - Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, + Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &MemOps[0], MemOps.size()); } else { // This will point to the next argument passed via stack. @@ -967,11 +967,11 @@ XCoreTargetLowering::LowerReturn(SDValue Chain, // Return on XCore is always a "retsp 0" if (Flag.getNode()) - return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, - Chain, DAG.getConstant(0, MVT::i32), Flag); + return DAG.getNode(XCoreISD::RETSP, dl, EVT::Other, + Chain, DAG.getConstant(0, EVT::i32), Flag); else // Return Void - return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, - Chain, DAG.getConstant(0, MVT::i32)); + return DAG.getNode(XCoreISD::RETSP, dl, EVT::Other, + Chain, DAG.getConstant(0, EVT::i32)); } //===----------------------------------------------------------------------===// @@ -1059,7 +1059,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, break; } unsigned ABIAlignment = getTargetData()-> - getABITypeAlignment(ST->getMemoryVT().getTypeForMVT()); + getABITypeAlignment(ST->getMemoryVT().getTypeForEVT()); unsigned Alignment = ST->getAlignment(); if (Alignment >= ABIAlignment) { break; @@ -1072,7 +1072,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N, Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) { return DAG.getMemmove(Chain, dl, ST->getBasePtr(), LD->getBasePtr(), - DAG.getConstant(StoreBits/8, MVT::i32), + DAG.getConstant(StoreBits/8, EVT::i32), Alignment, ST->getSrcValue(), ST->getSrcValueOffset(), LD->getSrcValue(), LD->getSrcValueOffset()); @@ -1154,7 +1154,7 @@ XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM, std::vector<unsigned> XCoreTargetLowering:: getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const + EVT VT) const { if (Constraint.size() != 1) return std::vector<unsigned>(); diff --git a/lib/Target/XCore/XCoreISelLowering.h b/lib/Target/XCore/XCoreISelLowering.h index a21744ef40..1265934633 100644 --- a/lib/Target/XCore/XCoreISelLowering.h +++ b/lib/Target/XCore/XCoreISelLowering.h @@ -129,7 +129,7 @@ namespace llvm { // Inline asm support std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, - MVT VT) const; + EVT VT) const; // Expand specifics SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG); diff --git a/lib/Transforms/Scalar/CodeGenPrepare.cpp b/lib/Transforms/Scalar/CodeGenPrepare.cpp index cae70cdd46..76792c9564 100644 --- a/lib/Transforms/Scalar/CodeGenPrepare.cpp +++ b/lib/Transforms/Scalar/CodeGenPrepare.cpp @@ -409,8 +409,8 @@ static void SplitEdgeNicely(TerminatorInst *TI, unsigned SuccNum, /// static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI){ // If this is a noop copy, - MVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); - MVT DstVT = TLI.getValueType(CI->getType()); + EVT SrcVT = TLI.getValueType(CI->getOperand(0)->getType()); + EVT DstVT = TLI.getValueType(CI->getType()); // This is an fp<->int conversion? if (SrcVT.isInteger() != DstVT.isInteger()) diff --git a/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/lib/Transforms/Scalar/LoopStrengthReduce.cpp index f8be95fc0d..0db3a964fa 100644 --- a/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -2209,7 +2209,7 @@ void LoopStrengthReduce::OptimizeShadowIV(Loop *L) { if (TLI) { // If target does not support DestTy natively then do not apply // this transformation. - MVT DVT = TLI->getValueType(DestTy); + EVT DVT = TLI->getValueType(DestTy); if (!TLI->isTypeLegal(DVT)) continue; } diff --git a/lib/VMCore/Function.cpp b/lib/VMCore/Function.cpp index 9fc300043d..481300500c 100644 --- a/lib/VMCore/Function.cpp +++ b/lib/VMCore/Function.cpp @@ -327,10 +327,10 @@ std::string Intrinsic::getName(ID id, const Type **Tys, unsigned numTys) { for (unsigned i = 0; i < numTys; ++i) { if (const PointerType* PTyp = dyn_cast<PointerType>(Tys[i])) { Result += ".p" + llvm::utostr(PTyp->getAddressSpace()) + - MVT::getMVT(PTyp->getElementType()).getMVTString(); + EVT::getEVT(PTyp->getElementType()).getEVTString(); } else if (Tys[i]) - Result += "." + MVT::getMVT(Tys[i]).getMVTString(); + Result += "." + EVT::getEVT(Tys[i]).getEVTString(); } return Result; } diff --git a/lib/VMCore/ValueTypes.cpp b/lib/VMCore/ValueTypes.cpp index 244659607f..de3b6400a7 100644 --- a/lib/VMCore/ValueTypes.cpp +++ b/lib/VMCore/ValueTypes.cpp @@ -1,4 +1,4 @@ -//===----------- ValueTypes.cpp - Implementation of MVT methods -----------===// +//===----------- ValueTypes.cpp - Implementation of EVT methods -----------===// // // The LLVM Compiler Infrastructure // @@ -19,58 +19,58 @@ #include "llvm/Support/ErrorHandling.h" using namespace llvm; -MVT MVT::getExtendedIntegerVT(unsigned BitWidth) { - MVT VT; +EVT EVT::getExtendedIntegerVT(unsigned BitWidth) { + EVT VT; VT.LLVMTy = IntegerType::get(BitWidth); assert(VT.isExtended() && "Type is not extended!"); return VT; } -MVT MVT::getExtendedVectorVT(MVT VT, unsigned NumElements) { - MVT ResultVT; - ResultVT.LLVMTy = VectorType::get(VT.getTypeForMVT(), NumElements); +EVT EVT::getExtendedVectorVT(EVT VT, unsigned NumElements) { + EVT ResultVT; + ResultVT.LLVMTy = VectorType::get(VT.getTypeForEVT(), NumElements); assert(ResultVT.isExtended() && "Type is not extended!"); return ResultVT; } -bool MVT::isExtendedFloatingPoint() const { +bool EVT::isExtendedFloatingPoint() const { assert(isExtended() && "Type is not extended!"); return LLVMTy->isFPOrFPVector(); } -bool MVT::isExtendedInteger() const { +bool EVT::isExtendedInteger() const { assert(isExtended() && "Type is not extended!"); return LLVMTy->isIntOrIntVector(); } -bool MVT::isExtendedVector() const { +bool EVT::isExtendedVector() const { assert(isExtended() && "Type is not extended!"); return isa<VectorType>(LLVMTy); } -bool MVT::isExtended64BitVector() const { +bool EVT::isExtended64BitVector() const { return isExtendedVector() && getSizeInBits() == 64; } -bool MVT::isExtended128BitVector() const { +bool EVT::isExtended128BitVector() const { return isExtendedVector() && getSizeInBits() == 128; } -bool MVT::isExtended256BitVector() const { +bool EVT::isExtended256BitVector() const { return isExtendedVector() && getSizeInBits() == 256; } -MVT MVT::getExtendedVectorElementType() const { +EVT EVT::getExtendedVectorElementType() const { assert(isExtended() && "Type is not extended!"); - return MVT::getMVT(cast<VectorType>(LLVMTy)->getElementType()); + return EVT::getEVT(cast<VectorType>(LLVMTy)->getElementType()); } -unsigned MVT::getExtendedVectorNumElements() const { +unsigned EVT::getExtendedVectorNumElements() const { assert(isExtended() && "Type is not extended!"); return cast<VectorType>(LLVMTy)->getNumElements(); } -unsigned MVT::getExtendedSizeInBits() const { +unsigned EVT::getExtendedSizeInBits() const { assert(isExtended() && "Type is not extended!"); if (const IntegerType *ITy = dyn_cast<IntegerType>(LLVMTy)) return ITy->getBitWidth(); @@ -80,119 +80,119 @@ unsigned MVT::getExtendedSizeInBits() const { return 0; // Suppress warnings. } -/// getMVTString - This function returns value type as a string, e.g. "i32". -std::string MVT::getMVTString() const { +/// getEVTString - This function returns value type as a string, e.g. "i32". +std::string EVT::getEVTString() const { switch (V) { default: if (isVector()) return "v" + utostr(getVectorNumElements()) + - getVectorElementType().getMVTString(); + getVectorElementType().getEVTString(); if (isInteger()) return "i" + utostr(getSizeInBits()); - llvm_unreachable("Invalid MVT!"); + llvm_unreachable("Invalid EVT!"); return "?"; - case MVT::i1: return "i1"; - case MVT::i8: return "i8"; - case MVT::i16: return "i16"; - case MVT::i32: return "i32"; - case MVT::i64: return "i64"; - case MVT::i128: return "i128"; - case MVT::f32: return "f32"; - case MVT::f64: return "f64"; - case MVT::f80: return "f80"; - case MVT::f128: return "f128"; - case MVT::ppcf128: return "ppcf128"; - case MVT::isVoid: return "isVoid"; - case MVT::Other: return "ch"; - case MVT::Flag: return "flag"; - case MVT::v2i8: return "v2i8"; - case MVT::v4i8: return "v4i8"; - case MVT::v8i8: return "v8i8"; - case MVT::v16i8: return "v16i8"; - case MVT::v32i8: return "v32i8"; - case MVT::v2i16: return "v2i16"; - case MVT::v4i16: return "v4i16"; - case MVT::v8i16: return "v8i16"; - case MVT::v16i16: return "v16i16"; - case MVT::v2i32: return "v2i32"; - case MVT::v4i32: return "v4i32"; - case MVT::v8i32: return "v8i32"; - case MVT::v1i64: return "v1i64"; - case MVT::v2i64: return "v2i64"; - case MVT::v4i64: return "v4i64"; - case MVT::v2f32: return "v2f32"; - case MVT::v4f32: return "v4f32"; - case MVT::v8f32: return "v8f32"; - case MVT::v2f64: return "v2f64"; - case MVT::v4f64: return "v4f64"; + case EVT::i1: return "i1"; + case EVT::i8: return "i8"; + case EVT::i16: return "i16"; + case EVT::i32: return "i32"; + case EVT::i64: return "i64"; + case EVT::i128: return "i128"; + case EVT::f32: return "f32"; + case EVT::f64: return "f64"; + case EVT::f80: return "f80"; + case EVT::f128: return "f128"; + case EVT::ppcf128: return "ppcf128"; + case EVT::isVoid: return "isVoid"; + case EVT::Other: return "ch"; + case EVT::Flag: return "flag"; + case EVT::v2i8: return "v2i8"; + case EVT::v4i8: return "v4i8"; + case EVT::v8i8: return "v8i8"; + case EVT::v16i8: return "v16i8"; + case EVT::v32i8: return "v32i8"; + case EVT::v2i16: return "v2i16"; + case EVT::v4i16: return "v4i16"; + case EVT::v8i16: return "v8i16"; + case EVT::v16i16: return "v16i16"; + case EVT::v2i32: return "v2i32"; + case EVT::v4i32: return "v4i32"; + case EVT::v8i32: return "v8i32"; + case EVT::v1i64: return "v1i64"; + case EVT::v2i64: return "v2i64"; + case EVT::v4i64: return "v4i64"; + case EVT::v2f32: return "v2f32"; + case EVT::v4f32: return "v4f32"; + case EVT::v8f32: return "v8f32"; + case EVT::v2f64: return "v2f64"; + case EVT::v4f64: return "v4f64"; } } -/// getTypeForMVT - This method returns an LLVM type corresponding to the -/// specified MVT. For integer types, this returns an unsigned type. Note +/// getTypeForEVT - This method returns an LLVM type corresponding to the +/// specified EVT. For integer types, this returns an unsigned type. Note /// that this will abort for types that cannot be represented. -const Type *MVT::getTypeForMVT() const { +const Type *EVT::getTypeForEVT() const { switch (V) { default: assert(isExtended() && "Type is not extended!"); return LLVMTy; - case MVT::isVoid: return Type::VoidTy; - case MVT::i1: return Type::Int1Ty; - case MVT::i8: return Type::Int8Ty; - case MVT::i16: return Type::Int16Ty; - case MVT::i32: return Type::Int32Ty; - case MVT::i64: return Type::Int64Ty; - case MVT::i128: return IntegerType::get(128); - case MVT::f32: return Type::FloatTy; - case MVT::f64: return Type::DoubleTy; - case MVT::f80: return Type::X86_FP80Ty; - case MVT::f128: return Type::FP128Ty; - case MVT::ppcf128: return Type::PPC_FP128Ty; - case MVT::v2i8: return VectorType::get(Type::Int8Ty, 2); - case MVT::v4i8: return VectorType::get(Type::Int8Ty, 4); - case MVT::v8i8: return VectorType::get(Type::Int8Ty, 8); - case MVT::v16i8: return VectorType::get(Type::Int8Ty, 16); - case MVT::v32i8: return VectorType::get(Type::Int8Ty, 32); - case MVT::v2i16: return VectorType::get(Type::Int16Ty, 2); - case MVT::v4i16: return VectorType::get(Type::Int16Ty, 4); - case MVT::v8i16: return VectorType::get(Type::Int16Ty, 8); - case MVT::v16i16: return VectorType::get(Type::Int16Ty, 16); - case MVT::v2i32: return VectorType::get(Type::Int32Ty, 2); - case MVT::v4i32: return VectorType::get(Type::Int32Ty, 4); - case MVT::v8i32: return VectorType::get(Type::Int32Ty, 8); - case MVT::v1i64: return VectorType::get(Type::Int64Ty, 1); - case MVT::v2i64: return VectorType::get(Type::Int64Ty, 2); - case MVT::v4i64: return VectorType::get(Type::Int64Ty, 4); - case MVT::v2f32: return VectorType::get(Type::FloatTy, 2); - case MVT::v4f32: return VectorType::get(Type::FloatTy, 4); - case MVT::v8f32: return VectorType::get(Type::FloatTy, 8); - case MVT::v2f64: return VectorType::get(Type::DoubleTy, 2); - case MVT::v4f64: return VectorType::get(Type::DoubleTy, 4); + case EVT::isVoid: return Type::VoidTy; + case EVT::i1: return Type::Int1Ty; + case EVT::i8: return Type::Int8Ty; + case EVT::i16: return Type::Int16Ty; + case EVT::i32: return Type::Int32Ty; + case EVT::i64: return Type::Int64Ty; + case EVT::i128: return IntegerType::get(128); + case EVT::f32: return Type::FloatTy; + case EVT::f64: return Type::DoubleTy; + case EVT::f80: return Type::X86_FP80Ty; + case EVT::f128: return Type::FP128Ty; + case EVT::ppcf128: return Type::PPC_FP128Ty; + case EVT::v2i8: return VectorType::get(Type::Int8Ty, 2); + case EVT::v4i8: return VectorType::get(Type::Int8Ty, 4); + case EVT::v8i8: return VectorType::get(Type::Int8Ty, 8); + case EVT::v16i8: return VectorType::get(Type::Int8Ty, 16); + case EVT::v32i8: return VectorType::get(Type::Int8Ty, 32); + case EVT::v2i16: return VectorType::get(Type::Int16Ty, 2); + case EVT::v4i16: return VectorType::get(Type::Int16Ty, 4); + case EVT::v8i16: return VectorType::get(Type::Int16Ty, 8); + case EVT::v16i16: return VectorType::get(Type::Int16Ty, 16); + case EVT::v2i32: return VectorType::get(Type::Int32Ty, 2); + case EVT::v4i32: return VectorType::get(Type::Int32Ty, 4); + case EVT::v8i32: return VectorType::get(Type::Int32Ty, 8); + case EVT::v1i64: return VectorType::get(Type::Int64Ty, 1); + case EVT::v2i64: return VectorType::get(Type::Int64Ty, 2); + case EVT::v4i64: return VectorType::get(Type::Int64Ty, 4); + case EVT::v2f32: return VectorType::get(Type::FloatTy, 2); + case EVT::v4f32: return VectorType::get(Type::FloatTy, 4); + case EVT::v8f32: return VectorType::get(Type::FloatTy, 8); + case EVT::v2f64: return VectorType::get(Type::DoubleTy, 2); + case EVT::v4f64: return VectorType::get(Type::DoubleTy, 4); } } -/// getMVT - Return the value type corresponding to the specified type. This -/// returns all pointers as MVT::iPTR. If HandleUnknown is true, unknown types +/// getEVT - Return the value type corresponding to the specified type. This +/// returns all pointers as EVT::iPTR. If HandleUnknown is true, unknown types /// are returned as Other, otherwise they are invalid. -MVT MVT::getMVT(const Type *Ty, bool HandleUnknown){ +EVT EVT::getEVT(const Type *Ty, bool HandleUnknown){ switch (Ty->getTypeID()) { default: - if (HandleUnknown) return MVT::Other; + if (HandleUnknown) return EVT::Other; llvm_unreachable("Unknown type!"); - return MVT::isVoid; + return EVT::isVoid; case Type::VoidTyID: - return MVT::isVoid; + return EVT::isVoid; case Type::IntegerTyID: return getIntegerVT(cast<IntegerType>(Ty)->getBitWidth()); - case Type::FloatTyID: return MVT::f32; - case Type::DoubleTyID: return MVT::f64; - case Type::X86_FP80TyID: return MVT::f80; - case Type::FP128TyID: return MVT::f128; - case Type::PPC_FP128TyID: return MVT::ppcf128; - case Type::PointerTyID: return MVT::iPTR; + case Type::FloatTyID: return EVT::f32; + case Type::DoubleTyID: return EVT::f64; + case Type::X86_FP80TyID: return EVT::f80; + case Type::FP128TyID: return EVT::f128; + case Type::PPC_FP128TyID: return EVT::ppcf128; + case Type::PointerTyID: return EVT::iPTR; case Type::VectorTyID: { const VectorType *VTy = cast<VectorType>(Ty); - return getVectorVT(getMVT(VTy->getElementType(), false), + return getVectorVT(getEVT(VTy->getElementType(), false), VTy->getNumElements()); } } diff --git a/lib/VMCore/Verifier.cpp b/lib/VMCore/Verifier.cpp index 9ca048838e..a60169094f 100644 --- a/lib/VMCore/Verifier.cpp +++ b/lib/VMCore/Verifier.cpp @@ -1559,7 +1559,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, return false; } } - } else if (VT == MVT::iAny) { + } else if (VT == EVT::iAny) { if (!EltTy->isInteger()) { CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not " "an integer type.", F); @@ -1584,7 +1584,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, } break; } - } else if (VT == MVT::fAny) { + } else if (VT == EVT::fAny) { if (!EltTy->isFloatingPoint()) { CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not " "a floating-point type.", F); @@ -1596,30 +1596,30 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, if (EltTy != Ty) Suffix += "v" + utostr(NumElts); - Suffix += MVT::getMVT(EltTy).getMVTString(); - } else if (VT == MVT::iPTR) { + Suffix += EVT::getEVT(EltTy).getEVTString(); + } else if (VT == EVT::iPTR) { if (!isa<PointerType>(Ty)) { CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a " "pointer and a pointer is required.", F); return false; } - } else if (VT == MVT::iPTRAny) { + } else if (VT == EVT::iPTRAny) { // Outside of TableGen, we don't distinguish iPTRAny (to any address space) // and iPTR. In the verifier, we can not distinguish which case we have so // allow either case to be legal. if (const PointerType* PTyp = dyn_cast<PointerType>(Ty)) { Suffix += ".p" + utostr(PTyp->getAddressSpace()) + - MVT::getMVT(PTyp->getElementType()).getMVTString(); + EVT::getEVT(PTyp->getElementType()).getEVTString(); } else { CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is not a " "pointer and a pointer is required.", F); return false; } - } else if (MVT((MVT::SimpleValueType)VT).isVector()) { - MVT VVT = MVT((MVT::SimpleValueType)VT); + } else if (EVT((EVT::SimpleValueType)VT).isVector()) { + EVT VVT = EVT((EVT::SimpleValueType)VT); // If this is a vector argument, verify the number and type of elements. - if (VVT.getVectorElementType() != MVT::getMVT(EltTy)) { + if (VVT.getVectorElementType() != EVT::getEVT(EltTy)) { CheckFailed("Intrinsic prototype has incorrect vector element type!", F); return false; } @@ -1629,7 +1629,7 @@ bool Verifier::PerformTypeCheck(Intrinsic::ID ID, Function *F, const Type *Ty, "vector elements!", F); return false; } - } else if (MVT((MVT::SimpleValueType)VT).getTypeForMVT() != EltTy) { + } else if (EVT((EVT::SimpleValueType)VT).getTypeForEVT() != EltTy) { CheckFailed(IntrinsicParam(ArgNo, NumRets) + " is wrong!", F); return false; } else if (EltTy != Ty) { @@ -1671,7 +1671,7 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F, } for (unsigned ArgNo = 0; ArgNo < RetNum; ++ArgNo) { - int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative. + int VT = va_arg(VA, int); // An EVT::SimpleValueType when non-negative. if (ST) Ty = ST->getElementType(ArgNo); @@ -1681,9 +1681,9 @@ void Verifier::VerifyIntrinsicPrototype(Intrinsic::ID ID, Function *F, // Verify the parameter types. for (unsigned ArgNo = 0; ArgNo < ParamNum; ++ArgNo) { - int VT = va_arg(VA, int); // An MVT::SimpleValueType when non-negative. + int VT = va_arg(VA, int); // An EVT::SimpleValueType when non-negative. - if (VT == MVT::isVoid && ArgNo > 0) { + if (VT == EVT::isVoid && ArgNo > 0) { if (!FTy->isVarArg()) CheckFailed("Intrinsic prototype has no '...'!", F); break; |