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author | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:24:19 +0000 |
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committer | Tom Stellard <thomas.stellard@amd.com> | 2014-04-09 15:24:19 +0000 |
commit | 79944ce3dad5d138e561e39af2103c17b79a90f0 (patch) | |
tree | 90e696a4b1811bf85124daa88167d82b57ddb426 /lib | |
parent | 70f3cae772c8bf0377bf40cad51ce6000872dba6 (diff) | |
download | llvm-79944ce3dad5d138e561e39af2103c17b79a90f0.tar.gz llvm-79944ce3dad5d138e561e39af2103c17b79a90f0.tar.bz2 llvm-79944ce3dad5d138e561e39af2103c17b79a90f0.tar.xz |
Merging r201841:
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r201841 | Kevin.Qin | 2014-02-21 02:45:48 -0500 (Fri, 21 Feb 2014) | 2 lines
[AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205903 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib')
-rw-r--r-- | lib/Target/AArch64/AArch64InstrInfo.td | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td index 23d81fc478..8e5a4d3039 100644 --- a/lib/Target/AArch64/AArch64InstrInfo.td +++ b/lib/Target/AArch64/AArch64InstrInfo.td @@ -2587,6 +2587,7 @@ class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs, pat, itin> { let mayStore = 1; let PostEncoderMethod = "fixLoadStoreExclusive<1,0>"; + let Constraints = "@earlyclobber $Rs"; } multiclass A64I_SRex<string asmstr, bits<3> opcode, string prefix> { |