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author | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
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committer | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
commit | b4dc0233c9f70e8cf946822811f233bb613a02e9 (patch) | |
tree | 6cb47482e15d250ae95e5c6c96abd2afb56f6fca /test/CodeGen/AArch64/atomic-ops.ll | |
parent | ae4e1a94e3fb7d1d2d0eec6eb7d04b74326c8453 (diff) | |
download | llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.gz llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.bz2 llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.xz |
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/atomic-ops.ll')
-rw-r--r-- | test/CodeGen/AArch64/atomic-ops.ll | 116 |
1 files changed, 58 insertions, 58 deletions
diff --git a/test/CodeGen/AArch64/atomic-ops.ll b/test/CodeGen/AArch64/atomic-ops.ll index 5e87f21a21..de84ff46ec 100644 --- a/test/CodeGen/AArch64/atomic-ops.ll +++ b/test/CodeGen/AArch64/atomic-ops.ll @@ -6,7 +6,7 @@ @var64 = global i64 0 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_add_i8: +; CHECK-LABEL: test_atomic_load_add_i8: %old = atomicrmw add i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -26,7 +26,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_add_i16: +; CHECK-LABEL: test_atomic_load_add_i16: %old = atomicrmw add i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -46,7 +46,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_add_i32: +; CHECK-LABEL: test_atomic_load_add_i32: %old = atomicrmw add i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -66,7 +66,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_add_i64: +; CHECK-LABEL: test_atomic_load_add_i64: %old = atomicrmw add i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -86,7 +86,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_sub_i8: +; CHECK-LABEL: test_atomic_load_sub_i8: %old = atomicrmw sub i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -106,7 +106,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_sub_i16: +; CHECK-LABEL: test_atomic_load_sub_i16: %old = atomicrmw sub i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -126,7 +126,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_sub_i32: +; CHECK-LABEL: test_atomic_load_sub_i32: %old = atomicrmw sub i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -146,7 +146,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_sub_i64: +; CHECK-LABEL: test_atomic_load_sub_i64: %old = atomicrmw sub i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -166,7 +166,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_and_i8: +; CHECK-LABEL: test_atomic_load_and_i8: %old = atomicrmw and i8* @var8, i8 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -186,7 +186,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_and_i16: +; CHECK-LABEL: test_atomic_load_and_i16: %old = atomicrmw and i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -206,7 +206,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_and_i32: +; CHECK-LABEL: test_atomic_load_and_i32: %old = atomicrmw and i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -226,7 +226,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_and_i64: +; CHECK-LABEL: test_atomic_load_and_i64: %old = atomicrmw and i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -246,7 +246,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_or_i8: +; CHECK-LABEL: test_atomic_load_or_i8: %old = atomicrmw or i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -266,7 +266,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_or_i16: +; CHECK-LABEL: test_atomic_load_or_i16: %old = atomicrmw or i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -286,7 +286,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_or_i32: +; CHECK-LABEL: test_atomic_load_or_i32: %old = atomicrmw or i32* @var32, i32 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -306,7 +306,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_or_i64: +; CHECK-LABEL: test_atomic_load_or_i64: %old = atomicrmw or i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -326,7 +326,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_xor_i8: +; CHECK-LABEL: test_atomic_load_xor_i8: %old = atomicrmw xor i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -346,7 +346,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_xor_i16: +; CHECK-LABEL: test_atomic_load_xor_i16: %old = atomicrmw xor i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -366,7 +366,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_xor_i32: +; CHECK-LABEL: test_atomic_load_xor_i32: %old = atomicrmw xor i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -386,7 +386,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_xor_i64: +; CHECK-LABEL: test_atomic_load_xor_i64: %old = atomicrmw xor i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -406,7 +406,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i8: +; CHECK-LABEL: test_atomic_load_xchg_i8: %old = atomicrmw xchg i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -425,7 +425,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i16: +; CHECK-LABEL: test_atomic_load_xchg_i16: %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -444,7 +444,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i32: +; CHECK-LABEL: test_atomic_load_xchg_i32: %old = atomicrmw xchg i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -463,7 +463,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_xchg_i64: +; CHECK-LABEL: test_atomic_load_xchg_i64: %old = atomicrmw xchg i64* @var64, i64 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -483,7 +483,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind { define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_min_i8: +; CHECK-LABEL: test_atomic_load_min_i8: %old = atomicrmw min i8* @var8, i8 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -504,7 +504,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_min_i16: +; CHECK-LABEL: test_atomic_load_min_i16: %old = atomicrmw min i16* @var16, i16 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -525,7 +525,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_min_i32: +; CHECK-LABEL: test_atomic_load_min_i32: %old = atomicrmw min i32* @var32, i32 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -546,7 +546,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_min_i64: +; CHECK-LABEL: test_atomic_load_min_i64: %old = atomicrmw min i64* @var64, i64 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -567,7 +567,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_max_i8: +; CHECK-LABEL: test_atomic_load_max_i8: %old = atomicrmw max i8* @var8, i8 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -588,7 +588,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_max_i16: +; CHECK-LABEL: test_atomic_load_max_i16: %old = atomicrmw max i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -609,7 +609,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_max_i32: +; CHECK-LABEL: test_atomic_load_max_i32: %old = atomicrmw max i32* @var32, i32 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -630,7 +630,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_max_i64: +; CHECK-LABEL: test_atomic_load_max_i64: %old = atomicrmw max i64* @var64, i64 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -651,7 +651,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_umin_i8: +; CHECK-LABEL: test_atomic_load_umin_i8: %old = atomicrmw umin i8* @var8, i8 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -672,7 +672,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_umin_i16: +; CHECK-LABEL: test_atomic_load_umin_i16: %old = atomicrmw umin i16* @var16, i16 %offset acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -693,7 +693,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_umin_i32: +; CHECK-LABEL: test_atomic_load_umin_i32: %old = atomicrmw umin i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -714,7 +714,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_umin_i64: +; CHECK-LABEL: test_atomic_load_umin_i64: %old = atomicrmw umin i64* @var64, i64 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -735,7 +735,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind { } define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { -; CHECK: test_atomic_load_umax_i8: +; CHECK-LABEL: test_atomic_load_umax_i8: %old = atomicrmw umax i8* @var8, i8 %offset acq_rel ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -756,7 +756,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind { } define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { -; CHECK: test_atomic_load_umax_i16: +; CHECK-LABEL: test_atomic_load_umax_i16: %old = atomicrmw umax i16* @var16, i16 %offset monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -777,7 +777,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind { } define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { -; CHECK: test_atomic_load_umax_i32: +; CHECK-LABEL: test_atomic_load_umax_i32: %old = atomicrmw umax i32* @var32, i32 %offset seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -798,7 +798,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind { } define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { -; CHECK: test_atomic_load_umax_i64: +; CHECK-LABEL: test_atomic_load_umax_i64: %old = atomicrmw umax i64* @var64, i64 %offset release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -819,7 +819,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind { } define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i8: +; CHECK-LABEL: test_atomic_cmpxchg_i8: %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -841,7 +841,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind { } define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i16: +; CHECK-LABEL: test_atomic_cmpxchg_i16: %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16 @@ -863,7 +863,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind { } define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i32: +; CHECK-LABEL: test_atomic_cmpxchg_i32: %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32 @@ -885,7 +885,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind { } define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { -; CHECK: test_atomic_cmpxchg_i64: +; CHECK-LABEL: test_atomic_cmpxchg_i64: %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64 @@ -907,7 +907,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind { } define i8 @test_atomic_load_monotonic_i8() nounwind { -; CHECK: test_atomic_load_monotonic_i8: +; CHECK-LABEL: test_atomic_load_monotonic_i8: %val = load atomic i8* @var8 monotonic, align 1 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 @@ -918,7 +918,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind { } define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { -; CHECK: test_atomic_load_monotonic_regoff_i8: +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* @@ -931,7 +931,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind { } define i8 @test_atomic_load_acquire_i8() nounwind { -; CHECK: test_atomic_load_acquire_i8: +; CHECK-LABEL: test_atomic_load_acquire_i8: %val = load atomic i8* @var8 acquire, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8 @@ -944,7 +944,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind { } define i8 @test_atomic_load_seq_cst_i8() nounwind { -; CHECK: test_atomic_load_seq_cst_i8: +; CHECK-LABEL: test_atomic_load_seq_cst_i8: %val = load atomic i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -957,7 +957,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind { } define i16 @test_atomic_load_monotonic_i16() nounwind { -; CHECK: test_atomic_load_monotonic_i16: +; CHECK-LABEL: test_atomic_load_monotonic_i16: %val = load atomic i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 @@ -969,7 +969,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind { } define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind { -; CHECK: test_atomic_load_monotonic_regoff_i32: +; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* @@ -982,7 +982,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind } define i64 @test_atomic_load_seq_cst_i64() nounwind { -; CHECK: test_atomic_load_seq_cst_i64: +; CHECK-LABEL: test_atomic_load_seq_cst_i64: %val = load atomic i64* @var64 seq_cst, align 8 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 @@ -995,7 +995,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind { } define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_monotonic_i8: +; CHECK-LABEL: test_atomic_store_monotonic_i8: store atomic i8 %val, i8* @var8 monotonic, align 1 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8 ; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8] @@ -1004,7 +1004,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind { } define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind { -; CHECK: test_atomic_store_monotonic_regoff_i8: +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i8* @@ -1015,7 +1015,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) ret void } define void @test_atomic_store_release_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_release_i8: +; CHECK-LABEL: test_atomic_store_release_i8: store atomic i8 %val, i8* @var8 release, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -1028,7 +1028,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind { } define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { -; CHECK: test_atomic_store_seq_cst_i8: +; CHECK-LABEL: test_atomic_store_seq_cst_i8: store atomic i8 %val, i8* @var8 seq_cst, align 1 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var8 @@ -1042,7 +1042,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind { } define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { -; CHECK: test_atomic_store_monotonic_i16: +; CHECK-LABEL: test_atomic_store_monotonic_i16: store atomic i16 %val, i16* @var16 monotonic, align 2 ; CHECK-NOT: dmb ; CHECK: adrp x[[HIADDR:[0-9]+]], var16 @@ -1053,7 +1053,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind { } define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind { -; CHECK: test_atomic_store_monotonic_regoff_i32: +; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32: %addr_int = add i64 %base, %off %addr = inttoptr i64 %addr_int to i32* @@ -1067,7 +1067,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va } define void @test_atomic_store_release_i64(i64 %val) nounwind { -; CHECK: test_atomic_store_release_i64: +; CHECK-LABEL: test_atomic_store_release_i64: store atomic i64 %val, i64* @var64 release, align 8 ; CHECK-NOT: dmb ; CHECK: adrp [[HIADDR:x[0-9]+]], var64 |