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| author | Tim Northover <tnorthover@apple.com> | 2013-10-09 07:53:57 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-09 07:53:57 +0000 |
| commit | d29bae8bc9b393a24c7f3a1812b88763505eda11 (patch) | |
| tree | 4e93eb9cb787689b90f38bbe511d0fa51aedf890 /test/CodeGen/AArch64/fcvt-int.ll | |
| parent | ccb06ae8f3ef0135d4bddf4f0f61f619c3ce3f1e (diff) | |
| download | llvm-d29bae8bc9b393a24c7f3a1812b88763505eda11.tar.gz llvm-d29bae8bc9b393a24c7f3a1812b88763505eda11.tar.bz2 llvm-d29bae8bc9b393a24c7f3a1812b88763505eda11.tar.xz | |
AArch64: enable MISched by default.
Substantial SelectionDAG scheduling is going away soon, and is
interfering with Hao's attempts to implement LDn/STn instructions, so
I say we make the leap first.
There were a few reorderings (inevitably) which broke some tests. I
tried to replace them with CHECK-DAG variants mostly, but some too
complex for that to be useful and I just reordered them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192282 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/fcvt-int.ll')
| -rw-r--r-- | test/CodeGen/AArch64/fcvt-int.ll | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/test/CodeGen/AArch64/fcvt-int.ll b/test/CodeGen/AArch64/fcvt-int.ll index 9afcfc4a8b..b28eb3ea1b 100644 --- a/test/CodeGen/AArch64/fcvt-int.ll +++ b/test/CodeGen/AArch64/fcvt-int.ll @@ -5,8 +5,8 @@ define i32 @test_floattoi32(float %in) { %signed = fptosi float %in to i32 %unsigned = fptoui float %in to i32 -; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}} -; CHECK: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{s[0-9]+}} %res = sub i32 %signed, %unsigned ; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] @@ -20,8 +20,8 @@ define i32 @test_doubletoi32(double %in) { %signed = fptosi double %in to i32 %unsigned = fptoui double %in to i32 -; CHECK: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}} -; CHECK: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:w[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:w[0-9]+]], {{d[0-9]+}} %res = sub i32 %signed, %unsigned ; CHECK: sub {{w[0-9]+}}, [[SIG]], [[UNSIG]] @@ -35,8 +35,8 @@ define i64 @test_floattoi64(float %in) { %signed = fptosi float %in to i64 %unsigned = fptoui float %in to i64 -; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}} -; CHECK: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{s[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{s[0-9]+}} %res = sub i64 %signed, %unsigned ; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] @@ -50,8 +50,8 @@ define i64 @test_doubletoi64(double %in) { %signed = fptosi double %in to i64 %unsigned = fptoui double %in to i64 -; CHECK: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}} -; CHECK: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzu [[UNSIG:x[0-9]+]], {{d[0-9]+}} +; CHECK-DAG: fcvtzs [[SIG:x[0-9]+]], {{d[0-9]+}} %res = sub i64 %signed, %unsigned ; CHECK: sub {{x[0-9]+}}, [[SIG]], [[UNSIG]] @@ -65,8 +65,8 @@ define float @test_i32tofloat(i32 %in) { %signed = sitofp i32 %in to float %unsigned = uitofp i32 %in to float -; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} -; CHECK: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{w[0-9]+}} %res = fsub float %signed, %unsigned ; CHECL: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] @@ -79,8 +79,8 @@ define double @test_i32todouble(i32 %in) { %signed = sitofp i32 %in to double %unsigned = uitofp i32 %in to double -; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} -; CHECK: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{w[0-9]+}} +; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{w[0-9]+}} %res = fsub double %signed, %unsigned ; CHECK: fsub {{d[0-9]+}}, [[SIG]], [[UNSIG]] @@ -93,8 +93,8 @@ define float @test_i64tofloat(i64 %in) { %signed = sitofp i64 %in to float %unsigned = uitofp i64 %in to float -; CHECK: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} -; CHECK: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:s[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: scvtf [[SIG:s[0-9]+]], {{x[0-9]+}} %res = fsub float %signed, %unsigned ; CHECK: fsub {{s[0-9]+}}, [[SIG]], [[UNSIG]] @@ -107,8 +107,8 @@ define double @test_i64todouble(i64 %in) { %signed = sitofp i64 %in to double %unsigned = uitofp i64 %in to double -; CHECK: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}} -; CHECK: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: ucvtf [[UNSIG:d[0-9]+]], {{x[0-9]+}} +; CHECK-DAG: scvtf [[SIG:d[0-9]+]], {{x[0-9]+}} %res = fsub double %signed, %unsigned ; CHECK: sub {{d[0-9]+}}, [[SIG]], [[UNSIG]] |