diff options
author | Tim Northover <tnorthover@apple.com> | 2013-12-09 10:48:32 +0000 |
---|---|---|
committer | Tim Northover <tnorthover@apple.com> | 2013-12-09 10:48:32 +0000 |
commit | 863c7b48a6672f7074b2e69683fe4259c8c31bd7 (patch) | |
tree | 3d1bb471ce2d5648a6c2ce0f2e8101c7df67e1f9 /test/CodeGen/AArch64/neon-simd-shift.ll | |
parent | 54ed08e250a76b570c2162d49633e11b8ebb2d98 (diff) | |
download | llvm-863c7b48a6672f7074b2e69683fe4259c8c31bd7.tar.gz llvm-863c7b48a6672f7074b2e69683fe4259c8c31bd7.tar.bz2 llvm-863c7b48a6672f7074b2e69683fe4259c8c31bd7.tar.xz |
Merge rest of r196210. Some bits strayed into r196701, turning 3.4 red. This
should fix the issue.
------------------------------------------------------------------------
r196210 | haoliu | 2013-12-03 06:06:55 +0000 (Tue, 03 Dec 2013) | 3 lines
[AArch64]Add missing floating point convert, round and misc intrinsics.
E.g. int64x1_t vcvt_s64_f64(float64x1_t a) -> FCVTZS Dd, Dn
------------------------------------------------------------------------
git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@196772 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64/neon-simd-shift.ll')
-rw-r--r-- | test/CodeGen/AArch64/neon-simd-shift.ll | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/neon-simd-shift.ll b/test/CodeGen/AArch64/neon-simd-shift.ll index 19d1b21964..fd762656e5 100644 --- a/test/CodeGen/AArch64/neon-simd-shift.ll +++ b/test/CodeGen/AArch64/neon-simd-shift.ll @@ -1522,3 +1522,35 @@ declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) declare <2 x i64> @llvm.arm.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) +define <1 x i64> @test_vcvt_n_s64_f64(<1 x double> %a) { +; CHECK-LABEL: test_vcvt_n_s64_f64 +; CHECK: fcvtzs d{{[0-9]+}}, d{{[0-9]+}}, #64 + %1 = tail call <1 x i64> @llvm.arm.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double> %a, i32 64) + ret <1 x i64> %1 +} + +define <1 x i64> @test_vcvt_n_u64_f64(<1 x double> %a) { +; CHECK-LABEL: test_vcvt_n_u64_f64 +; CHECK: fcvtzu d{{[0-9]+}}, d{{[0-9]+}}, #64 + %1 = tail call <1 x i64> @llvm.arm.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double> %a, i32 64) + ret <1 x i64> %1 +} + +define <1 x double> @test_vcvt_n_f64_s64(<1 x i64> %a) { +; CHECK-LABEL: test_vcvt_n_f64_s64 +; CHECK: scvtf d{{[0-9]+}}, d{{[0-9]+}}, #64 + %1 = tail call <1 x double> @llvm.arm.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64> %a, i32 64) + ret <1 x double> %1 +} + +define <1 x double> @test_vcvt_n_f64_u64(<1 x i64> %a) { +; CHECK-LABEL: test_vcvt_n_f64_u64 +; CHECK: ucvtf d{{[0-9]+}}, d{{[0-9]+}}, #64 + %1 = tail call <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64> %a, i32 64) + ret <1 x double> %1 +} + +declare <1 x i64> @llvm.arm.neon.vcvtfp2fxs.v1i64.v1f64(<1 x double>, i32) +declare <1 x i64> @llvm.arm.neon.vcvtfp2fxu.v1i64.v1f64(<1 x double>, i32) +declare <1 x double> @llvm.arm.neon.vcvtfxs2fp.v1f64.v1i64(<1 x i64>, i32) +declare <1 x double> @llvm.arm.neon.vcvtfxu2fp.v1f64.v1i64(<1 x i64>, i32)
\ No newline at end of file |