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| author | Amara Emerson <amara.emerson@arm.com> | 2013-10-24 08:28:24 +0000 |
|---|---|---|
| committer | Amara Emerson <amara.emerson@arm.com> | 2013-10-24 08:28:24 +0000 |
| commit | 2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca (patch) | |
| tree | 125ba5dcedd49c3708aa083f3accc5817607d5b2 /test/CodeGen/AArch64 | |
| parent | 5e4d8a5eca03c977ba01e061078a2d740ee6130a (diff) | |
| download | llvm-2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca.tar.gz llvm-2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca.tar.bz2 llvm-2f21452ba1ee5bde8fee438b4cf1a1ce95beb6ca.tar.xz | |
[AArch64] Fix NZCV reg live-in bug in F128CSEL codegen.
When generating the IfTrue basic block during the F128CSEL pseudo-instruction
handling, the NZCV live-in for the newly created BB wasn't being added. This
caused a fault during MI-sched/live range calculation when the predecessor
for the fall-through BB didn't have a live-in for phys-reg as expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193316 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/AArch64')
| -rw-r--r-- | test/CodeGen/AArch64/regress-fp128-livein.ll | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/CodeGen/AArch64/regress-fp128-livein.ll b/test/CodeGen/AArch64/regress-fp128-livein.ll new file mode 100644 index 0000000000..cb8432a7e4 --- /dev/null +++ b/test/CodeGen/AArch64/regress-fp128-livein.ll @@ -0,0 +1,17 @@ +; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s + +; Regression test for NZCV reg live-in not being added to fp128csel IfTrue BB, +; causing a crash during live range calc. +define void @fp128_livein(i64 %a) { + %tobool = icmp ne i64 %a, 0 + %conv = zext i1 %tobool to i32 + %conv2 = sitofp i32 %conv to fp128 + %conv6 = sitofp i32 %conv to double + %call3 = tail call i32 @g(fp128 %conv2) + %call8 = tail call i32 @h(double %conv6) + ret void +} + +declare i32 @f() +declare i32 @g(fp128) +declare i32 @h(double) |