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authorTom Stellard <thomas.stellard@amd.com>2014-04-09 15:24:19 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-04-09 15:24:19 +0000
commit79944ce3dad5d138e561e39af2103c17b79a90f0 (patch)
tree90e696a4b1811bf85124daa88167d82b57ddb426 /test/CodeGen/ARM/a15-SD-dep.ll
parent70f3cae772c8bf0377bf40cad51ce6000872dba6 (diff)
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Merging r201841:
------------------------------------------------------------------------ r201841 | Kevin.Qin | 2014-02-21 02:45:48 -0500 (Fri, 21 Feb 2014) | 2 lines [AArch64] Add register constraints to avoid generating STLXR and STXR with unpredictable behavior. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_34@205903 91177308-0d34-0410-b5e6-96231b3b80d8
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