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| author | Andrew Trick <atrick@apple.com> | 2012-11-13 00:34:44 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-11-13 00:34:44 +0000 |
| commit | f546ac5f9bdedc7d1ae49238c65a93201d0e4f05 (patch) | |
| tree | 497b92c9cc20fd1627e979ba85c1e4607c0fa430 /test/CodeGen/ARM/coalesce-subregs.ll | |
| parent | 4df2826166f1339eb7ddf5c5c84565fccb794de8 (diff) | |
| download | llvm-f546ac5f9bdedc7d1ae49238c65a93201d0e4f05.tar.gz llvm-f546ac5f9bdedc7d1ae49238c65a93201d0e4f05.tar.bz2 llvm-f546ac5f9bdedc7d1ae49238c65a93201d0e4f05.tar.xz | |
Cleanup the main RegisterCoalescer loop.
Block priorities still apply outside loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167793 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/coalesce-subregs.ll')
| -rw-r--r-- | test/CodeGen/ARM/coalesce-subregs.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index 14511ad5ce..5bdad1d838 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -147,7 +147,7 @@ if.end: ; preds = %entry, %if.then ; CHECK: vmov.f32 {{.*}}, #1.0 ; CHECK-NOT: vmov ; CHECK-NOT: vorr -; CHECK: %if.end +; CHECK: bx ; We may leave the last insertelement in the if.end block. ; It is inserting the %add value into a dead lane, but %add causes interference ; in the entry block, and we don't do dead lane checks across basic blocks. |