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| author | Jush Lu <jush.msn@gmail.com> | 2012-08-29 02:41:21 +0000 |
|---|---|---|
| committer | Jush Lu <jush.msn@gmail.com> | 2012-08-29 02:41:21 +0000 |
| commit | c4dc2490c4ea2c75e451eec5950179f06d2610a2 (patch) | |
| tree | 1c70c70417c49c34ac6e12bd7e66abc56f03edc0 /test/CodeGen/ARM/fast-isel-pic.ll | |
| parent | f26e43df26bb7b0c7bf4853477e36611e2c90dea (diff) | |
| download | llvm-c4dc2490c4ea2c75e451eec5950179f06d2610a2.tar.gz llvm-c4dc2490c4ea2c75e451eec5950179f06d2610a2.tar.bz2 llvm-c4dc2490c4ea2c75e451eec5950179f06d2610a2.tar.xz | |
[arm-fast-isel] Add support for ARM PIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162823 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-pic.ll')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-pic.ll | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/fast-isel-pic.ll b/test/CodeGen/ARM/fast-isel-pic.ll new file mode 100644 index 0000000000..392a845d2c --- /dev/null +++ b/test/CodeGen/ARM/fast-isel-pic.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=arm-apple-ios | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARMv7 + +@g = global i32 0, align 4 + +define i32 @LoadGV() { +entry: +; THUMB: LoadGV +; THUMB: movw [[reg0:r[0-9]+]], +; THUMB: movt [[reg0]], +; THUMB: add [[reg0]], pc +; ARM: LoadGV +; ARM: ldr [[reg1:r[0-9]+]], +; ARM: add [[reg1]], pc, [[reg1]] +; ARMv7: LoadGV +; ARMv7: movw [[reg2:r[0-9]+]], +; ARMv7: movt [[reg2]], +; ARMv7: add [[reg2]], pc, [[reg2]] + %tmp = load i32* @g + ret i32 %tmp +} + +@i = external global i32 + +define i32 @LoadIndirectSymbol() { +entry: +; THUMB: LoadIndirectSymbol +; THUMB: movw r[[reg3:[0-9]+]], +; THUMB: movt r[[reg3]], +; THUMB: add r[[reg3]], pc +; THUMB: ldr r[[reg3]], [r[[reg3]]] +; ARM: LoadIndirectSymbol +; ARM: ldr [[reg4:r[0-9]+]], +; ARM: ldr [[reg4]], [pc, [[reg4]]] +; ARMv7: LoadIndirectSymbol +; ARMv7: movw r[[reg5:[0-9]+]], +; ARMv7: movt r[[reg5]], +; ARMv7: add r[[reg5]], pc, r[[reg5]] +; ARMv7: ldr r[[reg5]], [r[[reg5]]] + %tmp = load i32* @i + ret i32 %tmp +} |