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| author | Jim Grosbach <grosbach@apple.com> | 2013-08-16 23:37:36 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2013-08-16 23:37:36 +0000 |
| commit | 785bd598529fa12d0a0f577c4d63c4ab371bc559 (patch) | |
| tree | bbc2ee1419ce21dab52cf575972f4c06ced7c47b /test/CodeGen/ARM/fast-isel-ret.ll | |
| parent | b49860ef030cb2dba0386278ee8737eecc4e7272 (diff) | |
| download | llvm-785bd598529fa12d0a0f577c4d63c4ab371bc559.tar.gz llvm-785bd598529fa12d0a0f577c4d63c4ab371bc559.tar.bz2 llvm-785bd598529fa12d0a0f577c4d63c4ab371bc559.tar.xz | |
ARM: Fast-isel register class constrain for extends.
Properly constrain the operand register class for instructions used
in [sz]ext expansion. Update more tests to use the verifier now that
we're getting the register classes correct.
rdar://12594152
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188594 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fast-isel-ret.ll')
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-ret.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/fast-isel-ret.ll b/test/CodeGen/ARM/fast-isel-ret.ll index 89f1d463c4..8a68309dc8 100644 --- a/test/CodeGen/ARM/fast-isel-ret.ll +++ b/test/CodeGen/ARM/fast-isel-ret.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi -verify-machineinstrs | FileCheck %s -; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s +; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s ; Sign-extend of i1 currently not supported by fast-isel ;define signext i1 @ret0(i1 signext %a) nounwind uwtable ssp { |