diff options
| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-09 18:19:41 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-08-09 18:19:41 +0000 |
| commit | 4a74b3b933e2944ff313dc5d24da6f9e8ec4c1c4 (patch) | |
| tree | 93ee9fb3cd121c4c46e3644a7597784dc185a785 /test/CodeGen/ARM/fp_convert.ll | |
| parent | e2406dfd8940b3178bf452d89fed2a5df7a63043 (diff) | |
| download | llvm-4a74b3b933e2944ff313dc5d24da6f9e8ec4c1c4.tar.gz llvm-4a74b3b933e2944ff313dc5d24da6f9e8ec4c1c4.tar.bz2 llvm-4a74b3b933e2944ff313dc5d24da6f9e8ec4c1c4.tar.xz | |
Inflate register classes after coalescing.
Coalescing can remove copy-like instructions with sub-register operands
that constrained the register class. Examples are:
x86: GR32_ABCD:sub_8bit_hi -> GR32
arm: DPR_VFP2:ssub0 -> DPR
Recompute the register class of any virtual registers that are used by
less instructions after coalescing.
This affects code generation for the Cortex-A8 where we use NEON
instructions for f32 operations, c.f. fp_convert.ll:
vadd.f32 d16, d1, d0
vcvt.s32.f32 d0, d16
The register allocator is now free to use d16 for the temporary, and
that comes first in the allocation order because it doesn't interfere
with any s-registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137133 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fp_convert.ll')
| -rw-r--r-- | test/CodeGen/ARM/fp_convert.ll | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 86c06f1ddd..7002cecf36 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -7,7 +7,8 @@ define i32 @test1(float %a, float %b) { ; VFP2: test1: ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} ; NEON: test1: -; NEON: vcvt.s32.f32 d0, d0 +; NEON: vadd.f32 [[D0:d[0-9]+]] +; NEON: vcvt.s32.f32 d0, [[D0]] entry: %0 = fadd float %a, %b %1 = fptosi float %0 to i32 @@ -18,7 +19,8 @@ define i32 @test2(float %a, float %b) { ; VFP2: test2: ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} ; NEON: test2: -; NEON: vcvt.u32.f32 d0, d0 +; NEON: vadd.f32 [[D0:d[0-9]+]] +; NEON: vcvt.u32.f32 d0, [[D0]] entry: %0 = fadd float %a, %b %1 = fptoui float %0 to i32 |