diff options
| author | Bob Wilson <bob.wilson@apple.com> | 2011-04-19 18:11:45 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-04-19 18:11:45 +0000 |
| commit | f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee (patch) | |
| tree | bcf774318218b9378fb7f3390036e5281cbba4d8 /test/CodeGen/ARM/fp_convert.ll | |
| parent | b34d837397053da8e9bff90dd714e24f2a3b98b3 (diff) | |
| download | llvm-f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee.tar.gz llvm-f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee.tar.bz2 llvm-f6a4d3c2f3e1029af252a0f6999edfa3c2f326ee.tar.xz | |
Avoid write-after-write issue hazards for Cortex-A9.
Add a avoidWriteAfterWrite() target hook to identify register classes that
suffer from write-after-write hazards. For those register classes, try to avoid
writing the same register in two consecutive instructions.
This is currently disabled by default. We should not spill to avoid hazards!
The command line flag -avoid-waw-hazard can be used to enable waw avoidance.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129772 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/fp_convert.ll')
| -rw-r--r-- | test/CodeGen/ARM/fp_convert.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 1ef9f7f321..86c06f1ddd 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -5,7 +5,7 @@ define i32 @test1(float %a, float %b) { ; VFP2: test1: -; VFP2: vcvt.s32.f32 s0, s0 +; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} ; NEON: test1: ; NEON: vcvt.s32.f32 d0, d0 entry: @@ -16,7 +16,7 @@ entry: define i32 @test2(float %a, float %b) { ; VFP2: test2: -; VFP2: vcvt.u32.f32 s0, s0 +; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} ; NEON: test2: ; NEON: vcvt.u32.f32 d0, d0 entry: @@ -27,7 +27,7 @@ entry: define float @test3(i32 %a, i32 %b) { ; VFP2: test3: -; VFP2: vcvt.f32.u32 s0, s0 +; VFP2: vcvt.f32.u32 s{{.}}, s{{.}} ; NEON: test3: ; NEON: vcvt.f32.u32 d0, d0 entry: @@ -38,7 +38,7 @@ entry: define float @test4(i32 %a, i32 %b) { ; VFP2: test4: -; VFP2: vcvt.f32.s32 s0, s0 +; VFP2: vcvt.f32.s32 s{{.}}, s{{.}} ; NEON: test4: ; NEON: vcvt.f32.s32 d0, d0 entry: |