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| author | Evan Cheng <evan.cheng@apple.com> | 2010-05-21 00:43:17 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2010-05-21 00:43:17 +0000 |
| commit | f7d87ee1584bffe361b39f8cec7a39131c8c4efc (patch) | |
| tree | c0979fdab1e173425d355e6cb2c7996140818eb0 /test/CodeGen/ARM/reg_sequence.ll | |
| parent | b11ac950d69c7a238de0a22fd23fbfcd994f57ee (diff) | |
| download | llvm-f7d87ee1584bffe361b39f8cec7a39131c8c4efc.tar.gz llvm-f7d87ee1584bffe361b39f8cec7a39131c8c4efc.tar.bz2 llvm-f7d87ee1584bffe361b39f8cec7a39131c8c4efc.tar.xz | |
Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/reg_sequence.ll')
| -rw-r--r-- | test/CodeGen/ARM/reg_sequence.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 1a27d4d939..3ba82ccdfa 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s +; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; Implementing vld / vst as REG_SEQUENCE eliminates the extra vmov's. %struct.int16x8_t = type { <8 x i16> } @@ -45,12 +45,12 @@ define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocaptur entry: ; CHECK: t2: ; CHECK: vld1.16 -; CHECK-NOT: vmov -; CHECK: vmul.i16 ; CHECK: vld1.16 -; CHECK: vst1.16 ; CHECK-NOT: vmov ; CHECK: vmul.i16 +; CHECK: vmul.i16 +; CHECK-NOT: vmov +; CHECK: vst1.16 ; CHECK: vst1.16 %0 = getelementptr inbounds %struct.int16x8_t* %vT0ptr, i32 0, i32 0 ; <<8 x i16>*> [#uses=1] %1 = load <8 x i16>* %0, align 16 ; <<8 x i16>> [#uses=1] @@ -238,8 +238,8 @@ bb14: ; preds = %bb6 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: t9: ; CHECK: vldr.64 -; CHECK-NEXT: vstmia r0, {d0,d1} -; CHECK-NEXT: vmov.i8 d1 +; CHECK: vmov.i8 d1 +; CHECK-NEXT: vstmia r0, {d2,d3} ; CHECK-NEXT: vstmia r0, {d0,d1} %3 = bitcast double 0.000000e+00 to <2 x float> ; <<2 x float>> [#uses=2] %4 = shufflevector <2 x float> %3, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> ; <<4 x float>> [#uses=1] |