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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:03:21 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:03:21 +0000 |
| commit | ffc658b056b7cc0b3f6a2626694b6a4216ed728d (patch) | |
| tree | ebe680a03750316ed3c572177cd1306a4c0fd173 /test/CodeGen/ARM/reg_sequence.ll | |
| parent | 88990248d3bfb2f265fcf27f8a032ac0eb14d09f (diff) | |
| download | llvm-ffc658b056b7cc0b3f6a2626694b6a4216ed728d.tar.gz llvm-ffc658b056b7cc0b3f6a2626694b6a4216ed728d.tar.bz2 llvm-ffc658b056b7cc0b3f6a2626694b6a4216ed728d.tar.xz | |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/reg_sequence.ll')
| -rw-r--r-- | test/CodeGen/ARM/reg_sequence.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 091a003ef9..78b4e7ea84 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -155,7 +155,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ; CHECK: t6: -; CHECK: vldr.64 +; CHECK: vldr ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2] @@ -240,7 +240,7 @@ bb14: ; preds = %bb6 ; PR7157 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; CHECK: t9: -; CHECK: vldr.64 +; CHECK: vldr ; CHECK-NOT: vmov d{{.*}}, d16 ; CHECK: vmov.i32 d17 ; CHECK-NEXT: vstmia r0, {d16, d17} |