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| author | Evan Cheng <evan.cheng@apple.com> | 2009-06-13 09:12:55 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-06-13 09:12:55 +0000 |
| commit | e7d6df73530a98a5cc5f69ddfd17073b464caa57 (patch) | |
| tree | 2ee5d1bb7677ae95573303bdc8a19a2e96866f82 /test/CodeGen/ARM/stm.ll | |
| parent | daf9e02893e7e17ca2267ffd5e994f824adbb624 (diff) | |
| download | llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.tar.gz llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.tar.bz2 llvm-e7d6df73530a98a5cc5f69ddfd17073b464caa57.tar.xz | |
Add a ARM specific pre-allocation pass that re-schedule loads / stores from
consecutive addresses togther. This makes it easier for the post-allocation pass
to form ldm / stm.
This is step 1. We are still missing a lot of ldm / stm opportunities because
of register allocation are not done in the desired order. More enhancements
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73291 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/stm.ll')
| -rw-r--r-- | test/CodeGen/ARM/stm.ll | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/stm.ll b/test/CodeGen/ARM/stm.ll new file mode 100644 index 0000000000..585645b021 --- /dev/null +++ b/test/CodeGen/ARM/stm.ll @@ -0,0 +1,13 @@ +; RUN: llvm-as < %s | llc -mtriple=arm-apple-darwin -mattr=+v6,+vfp2 -arm-pre-alloc-loadstore-opti | grep stm | count 2 + +@"\01LC" = internal constant [32 x i8] c"Boolean Not: %d %d %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[32 x i8]*> [#uses=1] +@"\01LC1" = internal constant [26 x i8] c"Bitwise Not: %d %d %d %d\0A\00", section "__TEXT,__cstring,cstring_literals" ; <[26 x i8]*> [#uses=1] + +declare i32 @printf(i8* nocapture, ...) nounwind + +define i32 @main() nounwind { +entry: + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([26 x i8]* @"\01LC1", i32 0, i32 0), i32 -2, i32 -3, i32 2, i32 -6) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([32 x i8]* @"\01LC", i32 0, i32 0), i32 0, i32 1, i32 0, i32 1, i32 0, i32 1) nounwind ; <i32> [#uses=0] + ret i32 0 +} |