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| author | Bob Wilson <bob.wilson@apple.com> | 2011-02-07 17:43:21 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2011-02-07 17:43:21 +0000 |
| commit | 1c3ef90cab9a563427bdd3c2fcd875c717750562 (patch) | |
| tree | 96e3030f27ad79d3147140f5ae0ecabf8f6b11c0 /test/CodeGen/ARM/vld4.ll | |
| parent | 7de6814405ab02591235f0826b8e6d98fd76c8ba (diff) | |
| download | llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.tar.gz llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.tar.bz2 llvm-1c3ef90cab9a563427bdd3c2fcd875c717750562.tar.xz | |
Add codegen support for using post-increment NEON load/store instructions.
The vld1-lane, vld1-dup and vst1-lane instructions do not yet support using
post-increment versions, but all the rest of the NEON load/store instructions
should be handled now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125014 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vld4.ll')
| -rw-r--r-- | test/CodeGen/ARM/vld4.ll | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index a616a98a25..59a73db318 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -22,6 +22,20 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ret <8 x i8> %tmp4 } +;Check for a post-increment updating load with register increment. +define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { +;CHECK: vld4i8_update: +;CHECK: vld4.8 {d16, d17, d18, d19}, [r2, :128], r1 + %A = load i8** %ptr + %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) + %tmp2 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp1, 2 + %tmp4 = add <8 x i8> %tmp2, %tmp3 + %tmp5 = getelementptr i8* %A, i32 %inc + store i8* %tmp5, i8** %ptr + ret <8 x i8> %tmp4 +} + define <4 x i16> @vld4i16(i16* %A) nounwind { ;CHECK: vld4i16: ;Check the alignment value. Max for this instruction is 256 bits: @@ -94,6 +108,22 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ret <8 x i16> %tmp4 } +;Check for a post-increment updating load. +define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { +;CHECK: vld4Qi16_update: +;CHECK: vld4.16 {d16, d18, d20, d22}, [r1, :64]! +;CHECK: vld4.16 {d17, d19, d21, d23}, [r1, :64]! + %A = load i16** %ptr + %tmp0 = bitcast i16* %A to i8* + %tmp1 = call %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4.v8i16(i8* %tmp0, i32 8) + %tmp2 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 0 + %tmp3 = extractvalue %struct.__neon_int16x8x4_t %tmp1, 2 + %tmp4 = add <8 x i16> %tmp2, %tmp3 + %tmp5 = getelementptr i16* %A, i32 32 + store i16* %tmp5, i16** %ptr + ret <8 x i16> %tmp4 +} + define <4 x i32> @vld4Qi32(i32* %A) nounwind { ;CHECK: vld4Qi32: ;CHECK: vld4.32 |