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| author | Bob Wilson <bob.wilson@apple.com> | 2010-12-17 01:21:12 +0000 |
|---|---|---|
| committer | Bob Wilson <bob.wilson@apple.com> | 2010-12-17 01:21:12 +0000 |
| commit | 495de3b783c239b4b3244a1e739b2a5b82561b1b (patch) | |
| tree | 1a8aaad24bf4130bb12674ee0c1c59050d954feb /test/CodeGen/ARM/vldlane.ll | |
| parent | a1f544b62e5d9eae0311dfb3a0b0e72f25e041d4 (diff) | |
| download | llvm-495de3b783c239b4b3244a1e739b2a5b82561b1b.tar.gz llvm-495de3b783c239b4b3244a1e739b2a5b82561b1b.tar.bz2 llvm-495de3b783c239b4b3244a1e739b2a5b82561b1b.tar.xz | |
Fix crash compiling a QQQQ REG_SEQUENCE for a Neon vld3_lane operation.
Radar 8776599
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122018 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM/vldlane.ll')
| -rw-r--r-- | test/CodeGen/ARM/vldlane.ll | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index fe2a0dc707..c5514a63fd 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -432,3 +432,22 @@ declare %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4lane.v2f32(i8*, <2 x flo declare %struct.__neon_int16x8x4_t @llvm.arm.neon.vld4lane.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32, i32) nounwind readonly declare %struct.__neon_int32x4x4_t @llvm.arm.neon.vld4lane.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32, i32) nounwind readonly declare %struct.__neon_float32x4x4_t @llvm.arm.neon.vld4lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32, i32) nounwind readonly + +; Radar 8776599: If one of the operands to a QQQQ REG_SEQUENCE is a register +; in the QPR_VFP2 regclass, it needs to be copied to a QPR regclass because +; we don't currently have a QQQQ_VFP2 super-regclass. (The "0" for the low +; part of %ins67 is supposed to be loaded by a VLDRS instruction in this test.) +define void @test_qqqq_regsequence_subreg([6 x i64] %b) nounwind { +;CHECK: test_qqqq_regsequence_subreg +;CHECK: vld3.16 + %tmp63 = extractvalue [6 x i64] %b, 5 + %tmp64 = zext i64 %tmp63 to i128 + %tmp65 = shl i128 %tmp64, 64 + %ins67 = or i128 %tmp65, 0 + %tmp78 = bitcast i128 %ins67 to <8 x i16> + %vld3_lane = tail call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* undef, <8 x i16> undef, <8 x i16> undef, <8 x i16> %tmp78, i32 1, i32 2) + call void @llvm.trap() + unreachable +} + +declare void @llvm.trap() nounwind |