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author | Bob Wilson <bob.wilson@apple.com> | 2010-11-01 23:40:51 +0000 |
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committer | Bob Wilson <bob.wilson@apple.com> | 2010-11-01 23:40:51 +0000 |
commit | 665814b6be3e44fdb84bcf1b7e5c933b60fbf280 (patch) | |
tree | 16be1fe85de97fc8105f0847b37a1ac0110ac673 /test/CodeGen/ARM | |
parent | baf061542682e1c5900b86aa7f9561f47509ea1b (diff) | |
download | llvm-665814b6be3e44fdb84bcf1b7e5c933b60fbf280.tar.gz llvm-665814b6be3e44fdb84bcf1b7e5c933b60fbf280.tar.bz2 llvm-665814b6be3e44fdb84bcf1b7e5c933b60fbf280.tar.xz |
Add support for alignment operands on VLD1-lane instructions.
This is another part of the fix for Radar 8599955.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117976 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r-- | test/CodeGen/ARM/vldlane.ll | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index d6ff6b9f29..97ab399043 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -2,27 +2,30 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld1lanei8: +;Check the (default) alignment value. ;CHECK: vld1.8 {d16[3]}, [r0] %tmp1 = load <8 x i8>* %B - %tmp2 = load i8* %A, align 1 + %tmp2 = load i8* %A, align 8 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 3 ret <8 x i8> %tmp3 } define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld1lanei16: -;CHECK: vld1.16 {d16[2]}, [r0] +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.16 {d16[2]}, [r0, :16] %tmp1 = load <4 x i16>* %B - %tmp2 = load i16* %A, align 2 + %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 2 ret <4 x i16> %tmp3 } define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { ;CHECK: vld1lanei32: -;CHECK: vld1.32 {d16[1]}, [r0] +;Check the alignment value. Max for this instruction is 16 bits: +;CHECK: vld1.32 {d16[1]}, [r0, :32] %tmp1 = load <2 x i32>* %B - %tmp2 = load i32* %A, align 4 + %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1 ret <2 x i32> %tmp3 } @@ -31,25 +34,25 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { ;CHECK: vld1laneQi8: ;CHECK: vld1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B - %tmp2 = load i8* %A, align 1 + %tmp2 = load i8* %A, align 8 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 9 ret <16 x i8> %tmp3 } define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld1laneQi16: -;CHECK: vld1.16 {d17[1]}, [r0] +;CHECK: vld1.16 {d17[1]}, [r0, :16] %tmp1 = load <8 x i16>* %B - %tmp2 = load i16* %A, align 2 + %tmp2 = load i16* %A, align 8 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 5 ret <8 x i16> %tmp3 } define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;CHECK: vld1laneQi32: -;CHECK: vld1.32 {d17[1]}, [r0] +;CHECK: vld1.32 {d17[1]}, [r0, :32] %tmp1 = load <4 x i32>* %B - %tmp2 = load i32* %A, align 4 + %tmp2 = load i32* %A, align 8 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 3 ret <4 x i32> %tmp3 } |