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| author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-06-17 15:18:27 +0000 |
|---|---|---|
| committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-06-17 15:18:27 +0000 |
| commit | 1e81966626635c99bcb77d9291b7f185f2159e2b (patch) | |
| tree | 364e927a8a42392926033780cbef2d996489e99d /test/CodeGen/ARM | |
| parent | ba6fc63eb291abb40ddf05ef91642a9cac9a90d1 (diff) | |
| download | llvm-1e81966626635c99bcb77d9291b7f185f2159e2b.tar.gz llvm-1e81966626635c99bcb77d9291b7f185f2159e2b.tar.bz2 llvm-1e81966626635c99bcb77d9291b7f185f2159e2b.tar.xz | |
Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
48 files changed, 141 insertions, 141 deletions
diff --git a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll index e068be74ba..7e9b066984 100644 --- a/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll +++ b/test/CodeGen/ARM/2009-06-22-CoalescerBug.ll @@ -3,7 +3,7 @@ %struct.rtunion = type { i64 } %struct.rtx_def = type { i16, i8, i8, [1 x %struct.rtunion] } -define arm_apcscc void @simplify_unary_real(i8* nocapture %p) nounwind { +define void @simplify_unary_real(i8* nocapture %p) nounwind { entry: %tmp121 = load i64* null, align 4 ; <i64> [#uses=1] %0 = getelementptr %struct.rtx_def* null, i32 0, i32 3, i32 3, i32 0 ; <i64*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll index 17efe00354..812f0188f1 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert.ll @@ -8,11 +8,11 @@ @"\01LC16" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -44,17 +44,17 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %3 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* undef, i8* %3, i32 undef, i32 undef, i32 undef, i32 undef) nounwind %4 = sitofp i32 undef to double ; <double> [#uses=1] %5 = fdiv double %4, 1.000000e+01 ; <double> [#uses=1] - %6 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] + %6 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([29 x i8]* @"\01LC12", i32 0, i32 0), double %5) nounwind ; <i32> [#uses=0] %7 = load i32* @al_len, align 4 ; <i32> [#uses=1] %8 = load i32* @no_mat, align 4 ; <i32> [#uses=1] %9 = load i32* @no_mis, align 4 ; <i32> [#uses=1] %10 = sub i32 %7, %8 ; <i32> [#uses=1] %11 = sub i32 %10, %9 ; <i32> [#uses=1] - %12 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] - %13 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] + %12 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC16", i32 0, i32 0), i32 %11) nounwind ; <i32> [#uses=0] + %13 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 undef) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll index f520be3946..f5fb97c0ef 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert2.ll @@ -6,11 +6,11 @@ @"\01LC15" = external constant [33 x i8], align 1 ; <[33 x i8]*> [#uses=1] @"\01LC17" = external constant [47 x i8], align 1 ; <[47 x i8]*> [#uses=1] -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -41,11 +41,11 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mat, align 4 store i32 0, i32* @no_mis, align 4 %4 = getelementptr i8* %B, i32 %0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind - %5 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] + tail call void @diff(i8* undef, i8* %4, i32 undef, i32 %3, i32 undef, i32 undef) nounwind + %5 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC11", i32 0, i32 0), i32 %tmp13) nounwind ; <i32> [#uses=0] %6 = load i32* @no_mis, align 4 ; <i32> [#uses=1] - %7 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] - %8 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] + %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([33 x i8]* @"\01LC15", i32 0, i32 0), i32 %6) nounwind ; <i32> [#uses=0] + %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([47 x i8]* @"\01LC17", i32 0, i32 0), i32 undef, i32 %1, i32 undef, i32 %2) nounwind ; <i32> [#uses=0] br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll index eee6ff98c6..d7e4c90abb 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert3.ll @@ -2,7 +2,7 @@ @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll index 93c92b1c93..77c133a80f 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert4.ll @@ -6,9 +6,9 @@ @no_mis = external global i32 ; <i32*> [#uses=1] @name1 = external global i8* ; <i8**> [#uses=1] -declare arm_apcscc void @diff(i8*, i8*, i32, i32, i32, i32) nounwind +declare void @diff(i8*, i8*, i32, i32, i32, i32) nounwind -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb @@ -35,7 +35,7 @@ bb11: ; preds = %bb9 store i32 0, i32* @no_mis, align 4 %1 = getelementptr i8* %A, i32 0 ; <i8*> [#uses=1] %2 = getelementptr i8* %B, i32 0 ; <i8*> [#uses=1] - tail call arm_apcscc void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind + tail call void @diff(i8* %1, i8* %2, i32 undef, i32 undef, i32 undef, i32 undef) nounwind br i1 undef, label %bb15, label %bb12 bb12: ; preds = %bb11 diff --git a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll index 277283dc08..16f5d1dc15 100644 --- a/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll +++ b/test/CodeGen/ARM/2009-06-30-RegScavengerAssert5.ll @@ -2,7 +2,7 @@ @XX = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll index 5c0e5fa57b..f0d79ce25c 100644 --- a/test/CodeGen/ARM/2009-07-01-CommuteBug.ll +++ b/test/CodeGen/ARM/2009-07-01-CommuteBug.ll @@ -4,7 +4,7 @@ @II = external global i32* ; <i32**> [#uses=1] @JJ = external global i32* ; <i32**> [#uses=1] -define arm_apcscc void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { +define void @SIM(i8* %A, i8* %B, i32 %M, i32 %N, i32 %K, [256 x i32]* %V, i32 %Q, i32 %R, i32 %nseq) nounwind { entry: br i1 undef, label %bb5, label %bb diff --git a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll index 2b7ccd8615..454fee5c5a 100644 --- a/test/CodeGen/ARM/2009-07-18-RewriterBug.ll +++ b/test/CodeGen/ARM/2009-07-18-RewriterBug.ll @@ -8,7 +8,7 @@ @_2E_str7 = internal constant [21 x i8] c"ERROR: Only 1 point!\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[21 x i8]*> [#uses=1] @llvm.used = appending global [1 x i8*] [i8* bitcast (void (%struct.EDGE_PAIR*, %struct.VERTEX*, %struct.VERTEX*)* @build_delaunay to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0] -define arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { +define void @build_delaunay(%struct.EDGE_PAIR* noalias nocapture sret %agg.result, %struct.VERTEX* %tree, %struct.VERTEX* %extra) nounwind { entry: %delright = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] %delleft = alloca %struct.EDGE_PAIR, align 8 ; <%struct.EDGE_PAIR*> [#uses=3] @@ -29,10 +29,10 @@ bb1.i: ; preds = %bb1.i, %bb br i1 %6, label %get_low.exit, label %bb1.i get_low.exit: ; preds = %bb1.i - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delright, %struct.VERTEX* %2, %struct.VERTEX* %extra) nounwind %7 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %8 = load %struct.VERTEX** %7, align 4 ; <%struct.VERTEX*> [#uses=1] - call arm_apcscc void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind + call void @build_delaunay(%struct.EDGE_PAIR* noalias sret %delleft, %struct.VERTEX* %8, %struct.VERTEX* %tree) nounwind %9 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 0 ; <%struct.edge_rec**> [#uses=1] %10 = load %struct.edge_rec** %9, align 8 ; <%struct.edge_rec*> [#uses=2] %11 = getelementptr %struct.EDGE_PAIR* %delleft, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] @@ -141,7 +141,7 @@ bb5.i: ; preds = %bb3.i %85 = inttoptr i32 %84 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %86 = getelementptr %struct.edge_rec* %ldi_addr.0.i, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] %87 = load %struct.VERTEX** %86, align 4 ; <%struct.VERTEX*> [#uses=1] - %88 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] + %88 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=6] %89 = getelementptr %struct.edge_rec* %88, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %88, %struct.edge_rec** %89, align 4 %90 = getelementptr %struct.edge_rec* %88, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=2] @@ -780,7 +780,7 @@ bb24.i: ; preds = %bb23.i, %bb21.i %592 = and i32 %589, -64 ; <i32> [#uses=1] %593 = or i32 %591, %592 ; <i32> [#uses=1] %594 = inttoptr i32 %593 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %595 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %595 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %596 = getelementptr %struct.edge_rec* %595, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %595, %struct.edge_rec** %596, align 4 %597 = getelementptr %struct.edge_rec* %595, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -882,7 +882,7 @@ bb25.i: ; preds = %bb23.i, %bb22.i %677 = and i32 %674, -64 ; <i32> [#uses=1] %678 = or i32 %676, %677 ; <i32> [#uses=1] %679 = inttoptr i32 %678 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] - %680 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %680 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %681 = getelementptr %struct.edge_rec* %680, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=5] store %struct.edge_rec* %680, %struct.edge_rec** %681, align 4 %682 = getelementptr %struct.edge_rec* %680, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1005,15 +1005,15 @@ bb7: ; preds = %bb %762 = getelementptr %struct.VERTEX* %tree, i32 0, i32 1 ; <%struct.VERTEX**> [#uses=1] %763 = load %struct.VERTEX** %762, align 4 ; <%struct.VERTEX*> [#uses=4] %764 = icmp eq %struct.VERTEX* %763, null ; <i1> [#uses=1] - %765 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] + %765 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=5] %766 = getelementptr %struct.edge_rec* %765, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %765, %struct.edge_rec** %766, align 4 %767 = getelementptr %struct.edge_rec* %765, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=3] br i1 %764, label %bb10, label %bb11 bb8: ; preds = %entry - %768 = call arm_apcscc i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] - call arm_apcscc void @exit(i32 -1) noreturn nounwind + %768 = call i32 @puts(i8* getelementptr ([21 x i8]* @_2E_str7, i32 0, i32 0)) nounwind ; <i32> [#uses=0] + call void @exit(i32 -1) noreturn nounwind unreachable bb10: ; preds = %bb7 @@ -1053,7 +1053,7 @@ bb11: ; preds = %bb7 store %struct.VERTEX* %tree, %struct.VERTEX** %790, align 4 %791 = getelementptr %struct.edge_rec* %785, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=1] store %struct.edge_rec* %783, %struct.edge_rec** %791, align 4 - %792 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %792 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %793 = getelementptr %struct.edge_rec* %792, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=4] store %struct.edge_rec* %792, %struct.edge_rec** %793, align 4 %794 = getelementptr %struct.edge_rec* %792, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1117,7 +1117,7 @@ bb11: ; preds = %bb7 %843 = or i32 %841, %842 ; <i32> [#uses=1] %844 = inttoptr i32 %843 to %struct.edge_rec* ; <%struct.edge_rec*> [#uses=1] %845 = load %struct.VERTEX** %767, align 4 ; <%struct.VERTEX*> [#uses=1] - %846 = call arm_apcscc %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] + %846 = call %struct.edge_rec* @alloc_edge() nounwind ; <%struct.edge_rec*> [#uses=4] %847 = getelementptr %struct.edge_rec* %846, i32 0, i32 1 ; <%struct.edge_rec**> [#uses=7] store %struct.edge_rec* %846, %struct.edge_rec** %847, align 4 %848 = getelementptr %struct.edge_rec* %846, i32 0, i32 0 ; <%struct.VERTEX**> [#uses=1] @@ -1316,8 +1316,8 @@ bb15: ; preds = %bb14, %bb13, %bb11, %bb10, %bb6 ret void } -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc void @exit(i32) noreturn nounwind +declare void @exit(i32) noreturn nounwind -declare arm_apcscc %struct.edge_rec* @alloc_edge() nounwind +declare %struct.edge_rec* @alloc_edge() nounwind diff --git a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll index b4b989bf38..d477ba9835 100644 --- a/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-ScavengerAssert.ll @@ -6,9 +6,9 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -declare arm_apcscc i32 @strlen(i8* nocapture) nounwind readonly +declare i32 @strlen(i8* nocapture) nounwind readonly -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 @@ -86,7 +86,7 @@ bb52: ; preds = %cli_calloc.exit %0 = load i16* undef, align 4 ; <i16> [#uses=1] %1 = icmp eq i16 %0, 0 ; <i1> [#uses=1] %iftmp.20.0 = select i1 %1, i8* %hexsig, i8* null ; <i8*> [#uses=1] - %2 = tail call arm_apcscc i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] + %2 = tail call i32 @strlen(i8* %iftmp.20.0) nounwind readonly ; <i32> [#uses=0] unreachable bb126: ; preds = %entry diff --git a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll index 24f499036c..67616877be 100644 --- a/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll +++ b/test/CodeGen/ARM/2009-07-22-SchedulerAssert.ll @@ -6,7 +6,7 @@ %struct.cli_bm_patt = type { i8*, i8*, i16, i16, i8*, i8*, i8, %struct.cli_bm_patt*, i16 } %struct.cli_matcher = type { i16, i8, i8*, %struct.cli_bm_patt**, i32*, i32, i8, i8, %struct.cli_ac_node*, %struct.cli_ac_node**, %struct.cli_ac_patt**, i32, i32, i32 } -define arm_apcscc i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { +define i32 @cli_ac_addsig(%struct.cli_matcher* nocapture %root, i8* %virname, i8* %hexsig, i32 %sigid, i16 zeroext %parts, i16 zeroext %partno, i16 zeroext %type, i32 %mindist, i32 %maxdist, i8* %offset, i8 zeroext %target) nounwind { entry: br i1 undef, label %bb126, label %bb1 diff --git a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll index e1d19d1ac2..5003fbdedb 100644 --- a/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll +++ b/test/CodeGen/ARM/2009-07-29-VFP3Registers.ll @@ -4,7 +4,7 @@ declare double @llvm.exp.f64(double) nounwind readonly -define arm_apcscc void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { +define void @findratio(double* nocapture %res1, double* nocapture %res2) nounwind { entry: br label %bb diff --git a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll index 2d4e58d636..a656c495f7 100644 --- a/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll +++ b/test/CodeGen/ARM/2009-08-02-RegScavengerAssert-Neon.ll @@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64" target triple = "armv7-apple-darwin9" -define arm_apcscc <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { +define <4 x i32> @scale(<4 x i32> %v, i32 %f) nounwind { entry: %v_addr = alloca <4 x i32> ; <<4 x i32>*> [#uses=2] %f_addr = alloca i32 ; <i32*> [#uses=2] diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll index 84915c4882..c598fe6e2e 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill.ll @@ -7,7 +7,7 @@ target triple = "armv7-apple-darwin9" %struct.tree = type { i32, double, double, %struct.tree*, %struct.tree*, %struct.tree*, %struct.tree* } @g = common global %struct.tree* null -define arm_apcscc %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { +define %struct.tree* @tsp(%struct.tree* %t, i32 %nproc) nounwind { entry: %t.idx51.val.i = load double* null ; <double> [#uses=1] br i1 undef, label %bb4.i, label %bb.i diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll index a21ffc38d0..cc92c26aee 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill2.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.icstruct = type { [3 x i32], i16 } %struct.node = type { i16, double, [3 x double], i32, i32 } -declare arm_apcscc double @floor(double) nounwind readnone +declare double @floor(double) nounwind readnone define void @intcoord(%struct.icstruct* noalias nocapture sret %agg.result, i1 %a, double %b) { entry: @@ -28,7 +28,7 @@ bb7: ; preds = %bb3 br i1 %a, label %bb11, label %bb9 bb9: ; preds = %bb7 - %0 = tail call arm_apcscc double @floor(double %b) nounwind readnone ; <double> [#uses=0] + %0 = tail call double @floor(double %b) nounwind readnone ; <double> [#uses=0] br label %bb11 bb11: ; preds = %bb9, %bb7 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll index e3d8ea60f9..90a4a42531 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill3.ll @@ -9,7 +9,7 @@ target triple = "armv7-apple-darwin9" %struct.Patient = type { i32, i32, i32, %struct.Village* } %struct.Village = type { [4 x %struct.Village*], %struct.Village*, %struct.List, %struct.Hosp, i32, i32 } -define arm_apcscc %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { +define %struct.Village* @alloc_tree(i32 %level, i32 %label, %struct.Village* %back, i1 %p) nounwind { entry: br i1 %p, label %bb8, label %bb1 diff --git a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll index 9123377e71..5cfc68d094 100644 --- a/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll +++ b/test/CodeGen/ARM/2009-08-21-PostRAKill4.ll @@ -8,19 +8,19 @@ target triple = "armv7-apple-darwin9" @.str1 = external constant [31 x i8], align 1 ; <[31 x i8]*> [#uses=1] @.str2 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1] -declare arm_apcscc i32 @getUnknown(i32, ...) nounwind +declare i32 @getUnknown(i32, ...) nounwind declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_end(i8*) nounwind -declare arm_apcscc i32 @printf(i8* nocapture, ...) nounwind +declare i32 @printf(i8* nocapture, ...) nounwind -define arm_apcscc i32 @main() nounwind { +define i32 @main() nounwind { entry: - %0 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] - %1 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] - %2 = tail call arm_apcscc i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] - %3 = tail call arm_apcscc i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] + %0 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 1, i32 1, i32 1, i32 1, i32 1, i32 1) nounwind ; <i32> [#uses=0] + %1 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([31 x i8]* @.str1, i32 0, i32 0), i32 -128, i32 116, i32 116, i32 -3852, i32 -31232, i32 -1708916736) nounwind ; <i32> [#uses=0] + %2 = tail call i32 (i32, ...)* @getUnknown(i32 undef, i32 116, i32 116, i32 -3852, i32 -31232, i32 30556, i32 -1708916736) nounwind ; <i32> [#uses=1] + %3 = tail call i32 (i8*, ...)* @printf(i8* getelementptr ([4 x i8]* @.str2, i32 0, i32 0), i32 %2) nounwind ; <i32> [#uses=0] ret i32 0 } diff --git a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll index c6ef256149..5407013f33 100644 --- a/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-26-ScalarToVector.ll @@ -10,7 +10,7 @@ target triple = "thumbv7-elf" declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone -define arm_apcscc void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { +define void @_ZN6squish10ClusterFit9Compress3EPv(%quuz* %this, i8* %block) { entry: %0 = lshr <4 x i32> zeroinitializer, <i32 31, i32 31, i32 31, i32 31> ; <<4 x i32>> [#uses=1] %1 = shufflevector <4 x i32> %0, <4 x i32> undef, <2 x i32> <i32 2, i32 3> ; <<2 x i32>> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll index bc5bfe9f60..cac8569617 100644 --- a/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll +++ b/test/CodeGen/ARM/2009-08-27-ScalarToVector.ll @@ -8,7 +8,7 @@ target triple = "thumbv7-elf" %quux = type { i32 (...)**, %baz*, i32 } %quuz = type { %quux, i32, %bar, [128 x i8], [16 x %foo], %foo, %foo, %foo } -define arm_apcscc void @aaaa(%quuz* %this, i8* %block) { +define void @aaaa(%quuz* %this, i8* %block) { entry: br i1 undef, label %bb.nph269, label %bb201 diff --git a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll index d5178b4bfb..5bd30ea1f1 100644 --- a/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll +++ b/test/CodeGen/ARM/2009-08-29-ExtractEltf32.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() nounwind { +define void @foo() nounwind { entry: %0 = tail call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> undef, <2 x float> undef) nounwind ; <<2 x float>> [#uses=1] %tmp28 = extractelement <2 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll index 266fce6e0c..4655962978 100644 --- a/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll +++ b/test/CodeGen/ARM/2009-08-29-TooLongSplat.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @aaa() nounwind { +define void @aaa() nounwind { entry: %0 = fmul <4 x float> undef, <float 1.000000e+00, float 1.000000e+01, float 1.000000e+02, float 0x3EB0C6F7A0000000> ; <<4 x float>> [#uses=1] %tmp31 = extractelement <4 x float> %0, i32 0 ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll index c0ad65f81b..397eba410b 100644 --- a/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll +++ b/test/CodeGen/ARM/2009-08-31-LSDA-Name.ll @@ -2,7 +2,7 @@ %struct.A = type { i32* } -define arm_apcscc void @"\01-[MyFunction Name:]"() { +define void @"\01-[MyFunction Name:]"() { entry: %save_filt.1 = alloca i32 ; <i32*> [#uses=2] %save_eptr.0 = alloca i8* ; <i8**> [#uses=2] @@ -10,12 +10,12 @@ entry: %eh_exception = alloca i8* ; <i8**> [#uses=5] %eh_selector = alloca i32 ; <i32*> [#uses=3] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] - call arm_apcscc void @_ZN1AC1Ev(%struct.A* %a) - invoke arm_apcscc void @_Z3barv() + call void @_ZN1AC1Ev(%struct.A* %a) + invoke void @_Z3barv() to label %invcont unwind label %lpad invcont: ; preds = %entry - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind br label %return bb: ; preds = %ppad @@ -23,7 +23,7 @@ bb: ; preds = %ppad store i32 %eh_select, i32* %save_filt.1, align 4 %eh_value = load i8** %eh_exception ; <i8*> [#uses=1] store i8* %eh_value, i8** %save_eptr.0, align 4 - call arm_apcscc void @_ZN1AD1Ev(%struct.A* %a) nounwind + call void @_ZN1AD1Ev(%struct.A* %a) nounwind %0 = load i8** %save_eptr.0, align 4 ; <i8*> [#uses=1] store i8* %0, i8** %eh_exception, align 4 %1 = load i32* %save_filt.1, align 4 ; <i32> [#uses=1] @@ -46,16 +46,16 @@ ppad: ; preds = %lpad Unwind: ; preds = %bb %eh_ptr3 = load i8** %eh_exception ; <i8*> [#uses=1] - call arm_apcscc void @_Unwind_SjLj_Resume(i8* %eh_ptr3) + call void @_Unwind_SjLj_Resume(i8* %eh_ptr3) unreachable } -define linkonce_odr arm_apcscc void @_ZN1AC1Ev(%struct.A* %this) { +define linkonce_odr void @_ZN1AC1Ev(%struct.A* %this) { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] store %struct.A* %this, %struct.A** %this_addr - %0 = call arm_apcscc i8* @_Znwm(i32 4) ; <i8*> [#uses=1] + %0 = call i8* @_Znwm(i32 4) ; <i8*> [#uses=1] %1 = bitcast i8* %0 to i32* ; <i32*> [#uses=1] %2 = load %struct.A** %this_addr, align 4 ; <%struct.A*> [#uses=1] %3 = getelementptr inbounds %struct.A* %2, i32 0, i32 0 ; <i32**> [#uses=1] @@ -66,9 +66,9 @@ return: ; preds = %entry ret void } -declare arm_apcscc i8* @_Znwm(i32) +declare i8* @_Znwm(i32) -define linkonce_odr arm_apcscc void @_ZN1AD1Ev(%struct.A* %this) nounwind { +define linkonce_odr void @_ZN1AD1Ev(%struct.A* %this) nounwind { entry: %this_addr = alloca %struct.A* ; <%struct.A**> [#uses=2] %"alloca point" = bitcast i32 0 to i32 ; <i32> [#uses=0] @@ -77,7 +77,7 @@ entry: %1 = getelementptr inbounds %struct.A* %0, i32 0, i32 0 ; <i32**> [#uses=1] %2 = load i32** %1, align 4 ; <i32*> [#uses=1] %3 = bitcast i32* %2 to i8* ; <i8*> [#uses=1] - call arm_apcscc void @_ZdlPv(i8* %3) nounwind + call void @_ZdlPv(i8* %3) nounwind br label %bb bb: ; preds = %entry @@ -88,9 +88,9 @@ return: ; preds = %bb } ;CHECK: L_LSDA_0: -declare arm_apcscc void @_ZdlPv(i8*) nounwind +declare void @_ZdlPv(i8*) nounwind -declare arm_apcscc void @_Z3barv() +declare void @_Z3barv() declare i8* @llvm.eh.exception() nounwind @@ -98,6 +98,6 @@ declare i32 @llvm.eh.selector.i32(i8*, i8*, ...) nounwind declare i32 @llvm.eh.typeid.for.i32(i8*) nounwind -declare arm_apcscc i32 @__gxx_personality_sj0(...) +declare i32 @__gxx_personality_sj0(...) -declare arm_apcscc void @_Unwind_SjLj_Resume(i8*) +declare void @_Unwind_SjLj_Resume(i8*) diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll index bf91fe099e..06a152d56e 100644 --- a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll @@ -30,11 +30,11 @@ target triple = "thumbv7-apple-darwin9" @.str218 = private constant [6 x i8] c"%7d%c\00", align 1 ; <[6 x i8]*> [#uses=1] @.str319 = private constant [30 x i8] c"Failed to allocate %u bytes.\0A\00", align 1 ; <[30 x i8]*> [#uses=1] -declare arm_apcscc i32 @puts(i8* nocapture) nounwind +declare i32 @puts(i8* nocapture) nounwind -declare arm_apcscc i32 @getchar() nounwind +declare i32 @getchar() nounwind -define internal arm_apcscc i32 @transpose() nounwind readonly { +define internal i32 @transpose() nounwind readonly { ; CHECK: push entry: %0 = load i32* getelementptr inbounds ([128 x i32]* @columns, i32 0, i32 1), align 4 ; <i32> [#uses=1] @@ -101,6 +101,6 @@ bb7: ; preds = %bb5 ret i32 -128 } -declare arm_apcscc noalias i8* @calloc(i32, i32) nounwind +declare noalias i8* @calloc(i32, i32) nounwind declare void @llvm.memset.i64(i8* nocapture, i8, i64, i32) nounwind diff --git a/test/CodeGen/ARM/2009-09-09-AllOnes.ll b/test/CodeGen/ARM/2009-09-09-AllOnes.ll index f654a1664c..8522a779a4 100644 --- a/test/CodeGen/ARM/2009-09-09-AllOnes.ll +++ b/test/CodeGen/ARM/2009-09-09-AllOnes.ll @@ -2,7 +2,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-elf" -define arm_apcscc void @foo() { +define void @foo() { entry: %0 = insertelement <4 x i32> undef, i32 -1, i32 3 store <4 x i32> %0, <4 x i32>* undef, align 16 diff --git a/test/CodeGen/ARM/2009-09-24-spill-align.ll b/test/CodeGen/ARM/2009-09-24-spill-align.ll index 5476d5f796..8bfd02697b 100644 --- a/test/CodeGen/ARM/2009-09-24-spill-align.ll +++ b/test/CodeGen/ARM/2009-09-24-spill-align.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; pr4926 -define arm_apcscc void @test_vget_lanep16() nounwind { +define void @test_vget_lanep16() nounwind { entry: %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1] %out_poly16_t = alloca i16 ; <i16*> [#uses=1] diff --git a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll index a737591bd9..198faebbea 100644 --- a/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll +++ b/test/CodeGen/ARM/2009-12-02-vtrn-undef.ll @@ -6,7 +6,7 @@ target triple = "armv7-apple-darwin10" %struct.int16x8_t = type { <8 x i16> } %struct.int16x8x2_t = type { [2 x %struct.int16x8_t] } -define arm_apcscc void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { +define void @t(%struct.int16x8x2_t* noalias nocapture sret %agg.result, <8 x i16> %tmp.0, %struct.int16x8x2_t* nocapture %dst) nounwind { entry: ;CHECK: vtrn.16 %0 = shufflevector <8 x i16> %tmp.0, <8 x i16> undef, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> diff --git a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll index 71e0b0a36c..89d6a68fca 100644 --- a/test/CodeGen/ARM/2010-04-09-NeonSelect.ll +++ b/test/CodeGen/ARM/2010-04-09-NeonSelect.ll @@ -1,7 +1,7 @@ ; RUN: llc -march=arm -mattr=+neon < %s ; Radar 7770501: Don't crash on SELECT and SELECT_CC with NEON vector values. -define arm_apcscc void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { +define void @vDSP_FFT16_copv(float* nocapture %O, float* nocapture %I, i32 %Direction) nounwind { entry: %.22 = select i1 undef, <4 x float> undef, <4 x float> zeroinitializer ; <<4 x float>> [#uses=1] %0 = fadd <4 x float> undef, %.22 ; <<4 x float>> [#uses=1] diff --git a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll index 4f71b83b94..1354c79755 100644 --- a/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll +++ b/test/CodeGen/ARM/2010-04-13-v2f64SplitArg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 ; Radar 7855014 -define arm_apcscc void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { +define void @test1(i32 %f0, i32 %f1, i32 %f2, <4 x i32> %f3) nounwind { entry: unreachable } diff --git a/test/CodeGen/ARM/2010-04-14-SplitVector.ll b/test/CodeGen/ARM/2010-04-14-SplitVector.ll index 42f98521e3..5d0c3cf74a 100644 --- a/test/CodeGen/ARM/2010-04-14-SplitVector.ll +++ b/test/CodeGen/ARM/2010-04-14-SplitVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=arm1136jf-s ; Radar 7854640 -define arm_apcscc void @test() nounwind { +define void @test() nounwind { bb: br i1 undef, label %bb9, label %bb10 diff --git a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll index ed7bca8510..05581c3f16 100644 --- a/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll +++ b/test/CodeGen/ARM/2010-04-15-ScavengerDebugValue.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64-n32" target triple = "armv4t-apple-darwin10" -define hidden arm_apcscc i32 @__addvsi3(i32 %a, i32 %b) nounwind { +define hidden i32 @__addvsi3(i32 %a, i32 %b) nounwind { entry: tail call void @llvm.dbg.value(metadata !{i32 %b}, i64 0, metadata !0) %0 = add nsw i32 %b, %a, !dbg !9 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll index 1c6577b648..946164321a 100644 --- a/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll +++ b/test/CodeGen/ARM/2010-05-18-LocalAllocCrash.ll @@ -10,7 +10,7 @@ target triple = "armv6-apple-darwin" @.str = external constant [1 x i8] ; <[1 x i8]*> [#uses=1] -define arm_apcscc void @yy(%struct.q* %qq) nounwind { +define void @yy(%struct.q* %qq) nounwind { entry: %vla6 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] %vla10 = alloca i8, i32 undef, align 1 ; <i8*> [#uses=1] @@ -19,18 +19,18 @@ entry: %tmp21 = load i32* undef ; <i32> [#uses=1] %0 = mul i32 1, %tmp21 ; <i32> [#uses=1] %vla22 = alloca i8, i32 %0, align 1 ; <i8*> [#uses=1] - call arm_apcscc void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) + call void (...)* @zz(i8* getelementptr inbounds ([1 x i8]* @.str, i32 0, i32 0), i32 2, i32 1) br i1 undef, label %if.then, label %if.end36 if.then: ; preds = %entry - %call = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] - %call35 = call arm_apcscc i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] + %call = call i32 (...)* @x(%struct.q* undef, i8* undef, i8* %vla6, i8* %vla10, i32 undef) ; <i32> [#uses=0] + %call35 = call i32 (...)* @x(%struct.q* undef, i8* %vla14, i8* %vla18, i8* %vla22, i32 undef) ; <i32> [#uses=0] unreachable if.end36: ; preds = %entry ret void } -declare arm_apcscc void @zz(...) +declare void @zz(...) -declare arm_apcscc i32 @x(...) +declare i32 @x(...) diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 99072283c2..5ad1c09eda 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -4,7 +4,7 @@ %struct.foo = type { i64, i64 } -define arm_apcscc zeroext i8 @t(%struct.foo* %this) noreturn optsize { +define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: ; ARM: t: ; ARM: str r0, [r1], r0 diff --git a/test/CodeGen/ARM/2010-05-21-BuildVector.ll b/test/CodeGen/ARM/2010-05-21-BuildVector.ll index 6b19490203..ce959d1b91 100644 --- a/test/CodeGen/ARM/2010-05-21-BuildVector.ll +++ b/test/CodeGen/ARM/2010-05-21-BuildVector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s ; Radar 7872877 -define arm_apcscc void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { +define void @test(float* %fltp, i32 %packedValue, float* %table) nounwind { entry: %0 = load float* %fltp %1 = insertelement <4 x float> undef, float %0, i32 0 diff --git a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll index 7519ca7bcb..e4f20990be 100644 --- a/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll +++ b/test/CodeGen/ARM/2010-06-11-vmovdrr-bitcast.ll @@ -3,7 +3,7 @@ %struct.__int8x8x2_t = type { [2 x <8 x i8>] } -define arm_apcscc void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { +define void @foo(%struct.__int8x8x2_t* nocapture %a, i8* %b) nounwind { entry: %0 = bitcast %struct.__int8x8x2_t* %a to i128* ; <i128*> [#uses=1] %srcval = load i128* %0, align 8 ; <i128> [#uses=2] diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll index 2c8f2abb97..c4f1814538 100644 --- a/test/CodeGen/ARM/arm-returnaddr.ll +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -3,7 +3,7 @@ ; rdar://8015977 ; rdar://8020118 -define arm_apcscc i8* @rt0(i32 %x) nounwind readnone { +define i8* @rt0(i32 %x) nounwind readnone { entry: ; CHECK: rt0: ; CHECK: mov r0, lr @@ -11,7 +11,7 @@ entry: ret i8* %0 } -define arm_apcscc i8* @rt2() nounwind readnone { +define i8* @rt2() nounwind readnone { entry: ; CHECK: rt2: ; CHECK: ldr r0, [r7] diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index 710994d8d7..f1d6a16f3e 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+vfp3 | FileCheck %s -define arm_apcscc float @t1(float %x) nounwind readnone optsize { +define float @t1(float %x) nounwind readnone optsize { entry: ; CHECK: t1: ; CHECK: vmov.f32 s1, #4.000000e+00 @@ -8,7 +8,7 @@ entry: ret float %0 } -define arm_apcscc double @t2(double %x) nounwind readnone optsize { +define double @t2(double %x) nounwind readnone optsize { entry: ; CHECK: t2: ; CHECK: vmov.f64 d1, #3.000000e+00 @@ -16,7 +16,7 @@ entry: ret double %0 } -define arm_apcscc double @t3(double %x) nounwind readnone optsize { +define double @t3(double %x) nounwind readnone optsize { entry: ; CHECK: t3: ; CHECK: vmov.f64 d1, #-1.300000e+01 @@ -24,7 +24,7 @@ entry: ret double %0 } -define arm_apcscc float @t4(float %x) nounwind readnone optsize { +define float @t4(float %x) nounwind readnone optsize { entry: ; CHECK: t4: ; CHECK: vmov.f32 s1, #-2.400000e+01 diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index f898060581..0aac9d16ec 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -5,7 +5,7 @@ @nextaddr = global i8* null ; <i8**> [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] -define internal arm_apcscc i32 @foo(i32 %i) nounwind { +define internal i32 @foo(i32 %i) nounwind { ; ARM: foo: ; THUMB: foo: ; THUMB2: foo: diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll index f0627728e5..687e138c1b 100644 --- a/test/CodeGen/ARM/inlineasm3.ll +++ b/test/CodeGen/ARM/inlineasm3.ll @@ -3,7 +3,7 @@ ; Radar 7449043 %struct.int32x4_t = type { <4 x i32> } -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: vmov.I64 q15, #0 ; CHECK: vmov.32 d30[0], r0 @@ -16,7 +16,7 @@ entry: ; Radar 7457110 %struct.int32x2_t = type { <4 x i32> } -define arm_apcscc void @t2() nounwind { +define void @t2() nounwind { entry: ; CHECK: vmov d30, d0 ; CHECK: vmov.32 r0, d30[0] diff --git a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll index 3708dc3fdc..e01617a5f0 100644 --- a/test/CodeGen/ARM/lsr-on-unrolled-loops.ll +++ b/test/CodeGen/ARM/lsr-on-unrolled-loops.ll @@ -40,7 +40,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- %22 = type { void (%0*)*, void (%0*, i8***, i32, i8**, i32)* } %23 = type { void (%0*, i32)*, void (%0*, i8**, i8**, i32)*, void (%0*)*, void (%0*)* } -define arm_apcscc void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { +define void @test(%0* nocapture %a0, %11* nocapture %a1, i16* nocapture %a2, i8** nocapture %a3, i32 %a4) nounwind { bb: %t = alloca [64 x float], align 4 %t5 = getelementptr inbounds %0* %a0, i32 0, i32 65 @@ -393,7 +393,7 @@ bb295: %struct.z_stream = type { i8*, i32, i32, i8*, i32, i32, i8*, %struct.internal_state*, i8* (i8*, i32, i32)*, void (i8*, i8*)*, i8*, i32, i32, i32 } %union.anon = type { i16 } -define arm_apcscc i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { +define i32 @longest_match(%struct.internal_state* %s, i32 %cur_match) nounwind optsize { entry: %0 = getelementptr inbounds %struct.internal_state* %s, i32 0, i32 31 ; <i32*> [#uses=1] %1 = load i32* %0, align 4 ; <i32> [#uses=2] diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index 8199d4664f..79ed84f0df 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -8,7 +8,7 @@ %struct.__neon_int16x8x2_t = type { <8 x i16>, <8 x i16> } %struct.__neon_int32x4x2_t = type { <4 x i32>, <4 x i32> } -define arm_apcscc void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { +define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t1: ; CHECK: vld1.16 @@ -41,7 +41,7 @@ entry: ret void } -define arm_apcscc void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { +define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: ; CHECK: t2: ; CHECK: vld1.16 @@ -88,7 +88,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { ret <8 x i8> %tmp4 } -define arm_apcscc void @t4(i32* %in, i32* %out) nounwind { +define void @t4(i32* %in, i32* %out) nounwind { entry: ; CHECK: t4: ; CHECK: vld2.32 @@ -163,7 +163,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp5 } -define arm_apcscc void @t7(i32* %iptr, i32* %optr) nounwind { +define void @t7(i32* %iptr, i32* %optr) nounwind { entry: ; CHECK: t7: ; CHECK: vld2.32 diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index 92c1cf1821..1e780e6a90 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+v6,+vfp2 -stats -info-output-file - | grep "Number of re-materialization" -define arm_apcscc i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { +define i32 @main(i32 %argc, i8** nocapture %argv, double %d1, double %d2) nounwind { entry: br i1 undef, label %smvp.exit, label %bb.i3 @@ -25,7 +25,7 @@ bb142: ; preds = %bb.nph218.bb.nph218 br i1 %14, label %phi1.exit, label %bb.i35 bb.i35: ; preds = %bb142 - %5 = call arm_apcscc double @sin(double %15) nounwind readonly ; <double> [#uses=1] + %5 = call double @sin(double %15) nounwind readonly ; <double> [#uses=1] %6 = fmul double %5, 0x4031740AFA84AD8A ; <double> [#uses=1] %7 = fsub double 1.000000e+00, undef ; <double> [#uses=1] %8 = fdiv double %7, 6.000000e-01 ; <double> [#uses=1] @@ -62,4 +62,4 @@ bb166: ; preds = %bb127 unreachable } -declare arm_apcscc double @sin(double) nounwind readonly +declare double @sin(double) nounwind readonly diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index 07edc91519..6e15fde045 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM ; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 -define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +define i32 @t1(i32 %c) nounwind readnone { entry: ; ARM: t1: ; ARM: mov r1, #101 @@ -17,7 +17,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +define i32 @t2(i32 %c) nounwind readnone { entry: ; ARM: t2: ; ARM: mov r1, #101 @@ -33,7 +33,7 @@ entry: ret i32 %1 } -define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +define i32 @t3(i32 %a) nounwind readnone { entry: ; ARM: t3: ; ARM: mov r0, #0 diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index 03de0c8454..792ef79982 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -9,7 +9,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly -define arm_apcscc void @aaa(%quuz* %this, i8* %block) { +define void @aaa(%quuz* %this, i8* %block) { ; CHECK: aaa: ; CHECK: bic sp, sp, #15 ; CHECK: vst1.64 {{.*}}sp, :128 diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index 763dff3056..b2f6b6e69f 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; rdar://7961298 -define arm_apcscc void @t() nounwind { +define void @t() nounwind { entry: ; CHECK: t: ; CHECK: trap diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index a4494f3705..e2794919d9 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -4,7 +4,7 @@ ; rdar://7113725 -define arm_apcscc void @t(i8* nocapture %a, i8* nocapture %b) nounwind { +define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: ; GENERIC: t: ; GENERIC: ldrb r2 diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index c9a68cabbc..50e4df9f57 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -244,25 +244,25 @@ define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @foo(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 1, i32 1> ret <2 x i64> %0 } -define arm_apcscc <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { +define <2 x i64> @bar(<2 x i64> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x i64> %arg0_int64x1_t, <2 x i64> undef, <2 x i32> <i32 0, i32 0> ret <2 x i64> %0 } -define arm_apcscc <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @baz(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 1, i32 1> ret <2 x double> %0 } -define arm_apcscc <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { +define <2 x double> @qux(<2 x double> %arg0_int64x1_t) nounwind readnone { entry: %0 = shufflevector <2 x double> %arg0_int64x1_t, <2 x double> undef, <2 x i32> <i32 0, i32 0> ret <2 x double> %0 diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index 20d953bfb4..c11a67c6c4 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -9,7 +9,7 @@ define arm_apcscc <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { +define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ;CHECK: test_vextRd: ;CHECK: vext %tmp1 = load <8 x i8>* %A @@ -18,7 +18,7 @@ define arm_apcscc <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { ret <8 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -27,7 +27,7 @@ define arm_apcscc <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ret <16 x i8> %tmp3 } -define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { +define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { ;CHECK: test_vextRq: ;CHECK: vext %tmp1 = load <16 x i8>* %A @@ -36,7 +36,7 @@ define arm_apcscc <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind ret <16 x i8> %tmp3 } -define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ;CHECK: test_vextd16: ;CHECK: vext %tmp1 = load <4 x i16>* %A @@ -45,7 +45,7 @@ define arm_apcscc <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind ret <4 x i16> %tmp3 } -define arm_apcscc <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ;CHECK: test_vextq32: ;CHECK: vext %tmp1 = load <4 x i32>* %A diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index e4368d6d5d..d6bedd56ff 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -136,7 +136,7 @@ define <2 x i64> @v_movQi64() nounwind { ; Check for correct assembler printing for immediate values. %struct.int8x8_t = type { <8 x i8> } -define arm_apcscc void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupn128: ;CHECK: vmov.i8 d0, #0x80 @@ -145,7 +145,7 @@ entry: ret void } -define arm_apcscc void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { +define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: ;CHECK: vdupnneg75: ;CHECK: vmov.i8 d0, #0xB5 diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index f0a04a4416..deed554d84 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev64D8: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A @@ -8,7 +8,7 @@ define arm_apcscc <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev64D16: ;CHECK: vrev64.16 %tmp1 = load <4 x i16>* %A @@ -16,7 +16,7 @@ define arm_apcscc <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { +define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ;CHECK: test_vrev64D32: ;CHECK: vrev64.32 %tmp1 = load <2 x i32>* %A @@ -24,7 +24,7 @@ define arm_apcscc <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { ret <2 x i32> %tmp2 } -define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { +define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ;CHECK: test_vrev64Df: ;CHECK: vrev64.32 %tmp1 = load <2 x float>* %A @@ -32,7 +32,7 @@ define arm_apcscc <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { ret <2 x float> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev64Q8: ;CHECK: vrev64.8 %tmp1 = load <16 x i8>* %A @@ -40,7 +40,7 @@ define arm_apcscc <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev64Q16: ;CHECK: vrev64.16 %tmp1 = load <8 x i16>* %A @@ -48,7 +48,7 @@ define arm_apcscc <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { +define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ;CHECK: test_vrev64Q32: ;CHECK: vrev64.32 %tmp1 = load <4 x i32>* %A @@ -56,7 +56,7 @@ define arm_apcscc <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { ret <4 x i32> %tmp2 } -define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { +define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ;CHECK: test_vrev64Qf: ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %A @@ -64,7 +64,7 @@ define arm_apcscc <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { ret <4 x float> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev32D8: ;CHECK: vrev32.8 %tmp1 = load <8 x i8>* %A @@ -72,7 +72,7 @@ define arm_apcscc <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { +define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ;CHECK: test_vrev32D16: ;CHECK: vrev32.16 %tmp1 = load <4 x i16>* %A @@ -80,7 +80,7 @@ define arm_apcscc <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { ret <4 x i16> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev32Q8: ;CHECK: vrev32.8 %tmp1 = load <16 x i8>* %A @@ -88,7 +88,7 @@ define arm_apcscc <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { ret <16 x i8> %tmp2 } -define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { +define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ;CHECK: test_vrev32Q16: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A @@ -96,7 +96,7 @@ define arm_apcscc <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { ret <8 x i16> %tmp2 } -define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { +define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ;CHECK: test_vrev16D8: ;CHECK: vrev16.8 %tmp1 = load <8 x i8>* %A @@ -104,7 +104,7 @@ define arm_apcscc <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { ret <8 x i8> %tmp2 } -define arm_apcscc <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { +define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ;CHECK: test_vrev16Q8: ;CHECK: vrev16.8 %tmp1 = load <16 x i8>* %A |