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| author | Tim Northover <tnorthover@apple.com> | 2013-10-25 09:30:24 +0000 |
|---|---|---|
| committer | Tim Northover <tnorthover@apple.com> | 2013-10-25 09:30:24 +0000 |
| commit | 214c37d1816b62a25525282817f7088a1e2ed1dc (patch) | |
| tree | 86ca829469e85c4e457480afd50f0cc8de3bdcba /test/CodeGen/ARM | |
| parent | 5a42ae81f742aaab826b7a72cb0a9a7e5a957a07 (diff) | |
| download | llvm-214c37d1816b62a25525282817f7088a1e2ed1dc.tar.gz llvm-214c37d1816b62a25525282817f7088a1e2ed1dc.tar.bz2 llvm-214c37d1816b62a25525282817f7088a1e2ed1dc.tar.xz | |
ARM: don't expand atomicrmw inline on Cortex-M0
There's a barrier instruction so that should still be used, but most actual
atomic operations are going to need a platform decision on the correct
behaviour (either nop if single-threaded or OS-support otherwise).
rdar://problem/15287210
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193399 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
| -rw-r--r-- | test/CodeGen/ARM/atomic-op.ll | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/atomic-op.ll b/test/CodeGen/ARM/atomic-op.ll index fb45b8da8f..9a79c9fd7b 100644 --- a/test/CodeGen/ARM/atomic-op.ll +++ b/test/CodeGen/ARM/atomic-op.ll @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-ios -verify-machineinstrs | FileCheck %s ; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-T1 +; RUN: llc < %s -mtriple=thumbv6-apple-ios -verify-machineinstrs -mcpu=cortex-m0 | FileCheck %s --check-prefix=CHECK-T1 define void @func(i32 %argc, i8** %argv) nounwind { entry: |