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authorTim Northover <tnorthover@apple.com>2013-10-24 10:37:09 +0000
committerTim Northover <tnorthover@apple.com>2013-10-24 10:37:09 +0000
commit6c0138e5fca970b126a76ee9252af462760c99c0 (patch)
treeea30db184bb7ea10ae6276a363ae147ac9bb5e2d /test/CodeGen/ARM
parent3985f6a98d39e306b145b766253d75d4de79cb9e (diff)
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ARM: Use non-VFP softcalls on embedded Darwinish targets
The compiler-rt functions __adddf3vfp and so on exist purely to allow Thumb1 code to make use of VFP instructions by switching back to ARM mode, they make no sense for M-class processors which don't even have an ARM mode. Given that justification, in practice this is a platform ABI decision so the actual check is based on that rather than CPU features. rdar://problem/15302004 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193327 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r--test/CodeGen/ARM/darwin-eabi.ll22
1 files changed, 22 insertions, 0 deletions
diff --git a/test/CodeGen/ARM/darwin-eabi.ll b/test/CodeGen/ARM/darwin-eabi.ll
new file mode 100644
index 0000000000..e0c20373ba
--- /dev/null
+++ b/test/CodeGen/ARM/darwin-eabi.ll
@@ -0,0 +1,22 @@
+; RUN: llc -mtriple=thumbv7m-apple-darwin-eabi -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-M3
+; RUN: llc -mtriple=thumbv7em-apple-darwin-eabi -mcpu=cortex-m4 < %s | FileCheck %s --check-prefix=CHECK-M4
+
+define float @float_op(float %lhs, float %rhs) {
+ %sum = fadd float %lhs, %rhs
+ ret float %sum
+; CHECK-M3-LABEL: float_op:
+; CHECK-M3: blx ___addsf3
+
+; CHECK-M4-LABEL: float_op:
+; CHECK-M4: vadd.f32
+}
+
+define double @double_op(double %lhs, double %rhs) {
+ %sum = fadd double %lhs, %rhs
+ ret double %sum
+; CHECK-M3-LABEL: double_op:
+; CHECK-M3: blx ___adddf3
+
+; CHECK-M4-LABEL: double_op:
+; CHECK-M4: blx ___adddf3
+}