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| author | Stephen Lin <stephenwlin@gmail.com> | 2013-07-14 06:24:09 +0000 |
|---|---|---|
| committer | Stephen Lin <stephenwlin@gmail.com> | 2013-07-14 06:24:09 +0000 |
| commit | 8b2b8a18354546d534b72f912153a3252ab4b857 (patch) | |
| tree | 9e745a19e157915db1f88e171514f4d22041c62a /test/CodeGen/ARM | |
| parent | 6611eaa32f7941dd50a3ffe608f3f4a7665dbe91 (diff) | |
| download | llvm-8b2b8a18354546d534b72f912153a3252ab4b857.tar.gz llvm-8b2b8a18354546d534b72f912153a3252ab4b857.tar.bz2 llvm-8b2b8a18354546d534b72f912153a3252ab4b857.tar.xz | |
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:
find test/CodeGen -name "*.ll" | \
while read NAME; do
echo "$NAME"
if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
TEMP=`mktemp -t temp`
cp $NAME $TEMP
sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
while read FUNC; do
sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
done
sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
mv $TEMP $NAME
fi
done
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
186 files changed, 1720 insertions, 1720 deletions
diff --git a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll index 0bfe331751..e7c0129a77 100644 --- a/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll +++ b/test/CodeGen/ARM/2007-01-19-InfiniteLoop.ll @@ -4,7 +4,7 @@ @dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1] @A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1] -; CHECK: dct_luma_sp: +; CHECK-LABEL: dct_luma_sp: define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) { entry: ; Make sure to use base-updating stores for saving callee-saved registers. diff --git a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll index e1e60e6317..ee99c70ff0 100644 --- a/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll +++ b/test/CodeGen/ARM/2009-08-31-TwoRegShuffle.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s ; pr4843 define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind { -;CHECK: v2regbug: +;CHECK-LABEL: v2regbug: ;CHECK: vzip.16 %tmp1 = load <4 x i16>* %B %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1> diff --git a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll index 0fe3b39a62..e2ff164502 100644 --- a/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll +++ b/test/CodeGen/ARM/2009-09-28-LdStOptiBug.ll @@ -4,7 +4,7 @@ %0 = type { double, double } define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind { -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: bl __aeabi_dadd ; CHECK-NOT: strd ; CHECK: mov diff --git a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll index a8afc20bc1..4fb2be02ce 100644 --- a/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll +++ b/test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll @@ -12,7 +12,7 @@ entry: %3 = fmul float %0, %1 ; <float> [#uses=1] %4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1] %5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1] -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00 %6 = fsub float 1.000000e+00, undef ; <float> [#uses=2] %7 = fsub float %2, undef ; <float> [#uses=1] diff --git a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll index 0ae7f84f3e..35995b77c5 100644 --- a/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll +++ b/test/CodeGen/ARM/2010-05-18-PostIndexBug.ll @@ -6,10 +6,10 @@ define zeroext i8 @t(%struct.foo* %this) noreturn optsize { entry: -; ARM: t: +; ARM-LABEL: t: ; ARM: str r2, [r1], r0 -; THUMB: t: +; THUMB-LABEL: t: ; THUMB-NOT: str r0, [r1], r0 ; THUMB: str r1, [r0] %0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1] diff --git a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll index da4d15771f..4179d8c99d 100644 --- a/test/CodeGen/ARM/2010-11-29-PrologueBug.ll +++ b/test/CodeGen/ARM/2010-11-29-PrologueBug.ll @@ -4,7 +4,7 @@ define i32* @t(i32* %x) nounwind { entry: -; ARM: t: +; ARM-LABEL: t: ; ARM: push ; ARM: mov r7, sp ; ARM: bl _foo @@ -12,7 +12,7 @@ entry: ; ARM: bl _foo ; ARM: pop {r7, pc} -; THUMB2: t: +; THUMB2-LABEL: t: ; THUMB2: push ; THUMB2: mov r7, sp ; THUMB2: blx _foo diff --git a/test/CodeGen/ARM/2010-12-07-PEIBug.ll b/test/CodeGen/ARM/2010-12-07-PEIBug.ll index 4879f4e10b..eef6abd964 100644 --- a/test/CodeGen/ARM/2010-12-07-PEIBug.ll +++ b/test/CodeGen/ARM/2010-12-07-PEIBug.ll @@ -3,7 +3,7 @@ define hidden void @foo() nounwind ssp { entry: -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: mov r7, sp ; CHECK-NEXT: vpush {d8} ; CHECK-NEXT: vpush {d10, d11} diff --git a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll index e84ce0e239..f689d4950e 100644 --- a/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll +++ b/test/CodeGen/ARM/2011-03-15-LdStMultipleBug.ll @@ -9,7 +9,7 @@ @oStruct = external global %struct.Outer, align 4 define void @main() nounwind { -; CHECK: main: +; CHECK-LABEL: main: ; CHECK-NOT: ldrd ; CHECK: mul for.body.lr.ph: diff --git a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll index 0fe88bd0ed..caa0be5657 100644 --- a/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll +++ b/test/CodeGen/ARM/2011-03-23-PeepholeBug.ll @@ -8,7 +8,7 @@ ; rdar://9172742 define i32 @t() nounwind { -; CHECK: t: +; CHECK-LABEL: t: entry: br label %bb2 diff --git a/test/CodeGen/ARM/2011-04-07-schediv.ll b/test/CodeGen/ARM/2011-04-07-schediv.ll index 19f756f513..f3dd3dd581 100644 --- a/test/CodeGen/ARM/2011-04-07-schediv.ll +++ b/test/CodeGen/ARM/2011-04-07-schediv.ll @@ -12,7 +12,7 @@ entry: ; Make sure the scheduler schedules all uses of the preincrement ; induction variable before defining the postincrement value. -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: %bb ; CHECK-NOT: mov bb: ; preds = %entry, %bb diff --git a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll index 568718c911..348ec9ffa0 100644 --- a/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll +++ b/test/CodeGen/ARM/2011-04-11-MachineLICMBug.ll @@ -4,7 +4,7 @@ ; rdar://9266679 define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp { -; CHECK: t: +; CHECK-LABEL: t: entry: br label %for.cond diff --git a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll index 5409f8c608..bc496b99f4 100644 --- a/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll +++ b/test/CodeGen/ARM/2011-11-28-DAGCombineBug.ll @@ -10,7 +10,7 @@ @infoBlock = external global %struct.InformationBlock define hidden void @foo() { -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: ldr.w ; CHECK: ldr.w ; CHECK-NOT: ldm diff --git a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll index 0ff4f510eb..e795ec55fe 100644 --- a/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll +++ b/test/CodeGen/ARM/2012-03-26-FoldImmBug.ll @@ -23,7 +23,7 @@ ; ; rdar://11116189 define i64 @t(i64 %aInput) nounwind { -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: movs [[REG:(r[0-9]+)]], #0 ; CHECK: movt [[REG]], #46540 ; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] diff --git a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll index 2f55204aa4..647ebd6bdf 100644 --- a/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll +++ b/test/CodeGen/ARM/2012-08-23-legalize-vmull.ll @@ -13,7 +13,7 @@ ; v4i8 ; define void @sextload_v4i8_c(<4 x i8>* %v) nounwind { -;CHECK: sextload_v4i8_c: +;CHECK-LABEL: sextload_v4i8_c: entry: %0 = load <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> @@ -26,7 +26,7 @@ entry: ; v2i8 ; define void @sextload_v2i8_c(<2 x i8>* %v) nounwind { -;CHECK: sextload_v2i8_c: +;CHECK-LABEL: sextload_v2i8_c: entry: %0 = load <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> @@ -39,7 +39,7 @@ entry: ; v2i16 ; define void @sextload_v2i16_c(<2 x i16>* %v) nounwind { -;CHECK: sextload_v2i16_c: +;CHECK-LABEL: sextload_v2i16_c: entry: %0 = load <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> @@ -54,7 +54,7 @@ entry: ; v4i8 ; define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind { -;CHECK: sextload_v4i8_v: +;CHECK-LABEL: sextload_v4i8_v: entry: %0 = load <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> @@ -70,7 +70,7 @@ entry: ; v2i8 ; define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind { -;CHECK: sextload_v2i8_v: +;CHECK-LABEL: sextload_v2i8_v: entry: %0 = load <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> @@ -86,7 +86,7 @@ entry: ; v2i16 ; define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind { -;CHECK: sextload_v2i16_v: +;CHECK-LABEL: sextload_v2i16_v: entry: %0 = load <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> @@ -104,7 +104,7 @@ entry: ; v4i8 x v4i16 ; define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind { -;CHECK: sextload_v4i8_vs: +;CHECK-LABEL: sextload_v4i8_vs: entry: %0 = load <4 x i8>* %v, align 8 %v0 = sext <4 x i8> %0 to <4 x i32> @@ -120,7 +120,7 @@ entry: ; v2i8 ; v2i8 x v2i16 define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind { -;CHECK: sextload_v2i8_vs: +;CHECK-LABEL: sextload_v2i8_vs: entry: %0 = load <2 x i8>* %v, align 8 %v0 = sext <2 x i8> %0 to <2 x i64> @@ -136,7 +136,7 @@ entry: ; v2i16 ; v2i16 x v2i32 define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind { -;CHECK: sextload_v2i16_vs: +;CHECK-LABEL: sextload_v2i16_vs: entry: %0 = load <2 x i16>* %v, align 8 %v0 = sext <2 x i16> %0 to <2 x i64> diff --git a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll index e761ffe72c..3bdbb3cf58 100644 --- a/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll +++ b/test/CodeGen/ARM/2012-09-18-ARMv4ISelBug.ll @@ -4,7 +4,7 @@ ; rdar://12300648 define i32 @t(i32 %x) { -; CHECK: t: +; CHECK-LABEL: t: ; CHECK-NOT: movw %tmp = add i32 %x, -65535 ret i32 %tmp diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index 645e68ba15..b8bea1f740 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -23,7 +23,7 @@ entry: ret void } -; CHECK: main: +; CHECK-LABEL: main: ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movt [[BASE]], :upper16:static_val ; ldm is not formed when the coalescer failed to coalesce everything. @@ -53,7 +53,7 @@ entry: ret void } -; CHECK: main_fixed_arg: +; CHECK-LABEL: main_fixed_arg: ; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val ; CHECK: movt [[BASE]], :upper16:static_val ; ldm is not formed when the coalescer failed to coalesce everything. diff --git a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll index f2395107d4..a59533c4a8 100644 --- a/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll +++ b/test/CodeGen/ARM/2012-10-04-LDRB_POST_IMM-Crash.ll @@ -6,7 +6,7 @@ declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val); -; CHECK: main: +; CHECK-LABEL: main: define i32 @main() nounwind { entry: ; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1 diff --git a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll index fcc6a7f7e9..0028eec80f 100644 --- a/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll +++ b/test/CodeGen/ARM/2012-10-18-PR14099-ByvalFrameAddress.ll @@ -5,7 +5,7 @@ declare void @f(%struct.s* %p); -; CHECK: t: +; CHECK-LABEL: t: define void @t(i32 %a, %struct.s* byval %s) nounwind { entry: @@ -20,7 +20,7 @@ entry: ret void } -; CHECK: caller: +; CHECK-LABEL: caller: define void @caller() { ; CHECK: ldm r0, {r1, r2, r3} diff --git a/test/CodeGen/ARM/2013-01-21-PR14992.ll b/test/CodeGen/ARM/2013-01-21-PR14992.ll index 05abdeda0f..014686feee 100644 --- a/test/CodeGen/ARM/2013-01-21-PR14992.ll +++ b/test/CodeGen/ARM/2013-01-21-PR14992.ll @@ -2,8 +2,8 @@ ;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s ;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s -;EXPECTED: foo: -;CHECK: foo: +;EXPECTED-LABEL: foo: +;CHECK-LABEL: foo: define i32 @foo(i32* %a) nounwind optsize { entry: %0 = load i32* %a, align 4 diff --git a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll index 0e3bf23710..135b144030 100644 --- a/test/CodeGen/ARM/2013-02-27-expand-vfma.ll +++ b/test/CodeGen/ARM/2013-02-27-expand-vfma.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4 define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind { -; CHECK: muladd: +; CHECK-LABEL: muladd: ; CHECK: fmaf ; CHECK: fmaf ; CHECK: fmaf @@ -17,7 +17,7 @@ define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounw declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1 define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind { -; CHECK: muladd2: +; CHECK-LABEL: muladd2: ; CHECK: fmaf ; CHECK: fmaf ; CHECK-NOT: fmaf diff --git a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll index 80b9d28a4b..127429bc31 100644 --- a/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll +++ b/test/CodeGen/ARM/2013-04-05-Small-ByVal-Structs-PR15293.ll @@ -1,7 +1,7 @@ ;PR15293: ARM codegen ice - expected larger existing stack allocation ;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s -;CHECK: foo: +;CHECK-LABEL: foo: ;CHECK: sub sp, sp, #8 ;CHECK: push {r11, lr} ;CHECK: str r0, [sp, #8] @@ -11,7 +11,7 @@ ;CHECK: add sp, sp, #8 ;CHECK: mov pc, lr -;CHECK: foo2: +;CHECK-LABEL: foo2: ;CHECK: sub sp, sp, #8 ;CHECK: push {r11, lr} ;CHECK: str r0, [sp, #8] @@ -24,7 +24,7 @@ ;CHECK: add sp, sp, #8 ;CHECK: mov pc, lr -;CHECK: doFoo: +;CHECK-LABEL: doFoo: ;CHECK: push {r11, lr} ;CHECK: ldr r0, ;CHECK: ldr r0, [r0] @@ -33,7 +33,7 @@ ;CHECK: mov pc, lr -;CHECK: doFoo2: +;CHECK-LABEL: doFoo2: ;CHECK: push {r11, lr} ;CHECK: ldr r0, ;CHECK: mov r1, #0 diff --git a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll index 38d515f922..08bf99b31f 100644 --- a/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll +++ b/test/CodeGen/ARM/2013-04-16-AAPCS-C4-vs-VFP.ll @@ -53,11 +53,11 @@ ;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s ; -;CHECK: foo: +;CHECK-LABEL: foo: ;CHECK-NOT: mov r0 ;CHECK-NOT: ldr r0 ;CHECK: bl fooUseI32 -;CHECK: doFoo: +;CHECK-LABEL: doFoo: ;CHECK: movs r0, #43 ;CHECK: bl foo diff --git a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll index de5fd31e2f..0e0537ec5b 100644 --- a/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll +++ b/test/CodeGen/ARM/2013-04-21-AAPCS-VA-C.1.cp.ll @@ -9,7 +9,7 @@ @.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1 -;CHECK: printfn: +;CHECK-LABEL: printfn: define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) { entry: %conv = sext i16 %b to i32 diff --git a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll index abc6e0d111..3f054c64b8 100644 --- a/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll +++ b/test/CodeGen/ARM/2013-05-05-IfConvertBug.ll @@ -2,7 +2,7 @@ ; rdar://13782395 define i32 @t1(i32 %a, i32 %b, i8** %retaddr) { -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: Block address taken ; CHECK-NOT: Address of block that was removed by CodeGen store i8* blockaddress(@t1, %cond_true), i8** %retaddr @@ -19,7 +19,7 @@ cond_false: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) { -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: Block address taken ; CHECK: %cond_true ; CHECK: add @@ -41,7 +41,7 @@ UnifiedReturnBlock: } define hidden fastcc void @t3(i8** %retaddr) { -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: Block address taken ; CHECK-NOT: Address of block that was removed by CodeGen bb: diff --git a/test/CodeGen/ARM/a15-SD-dep.ll b/test/CodeGen/ARM/a15-SD-dep.ll index a52468e5be..df921e005c 100644 --- a/test/CodeGen/ARM/a15-SD-dep.ll +++ b/test/CodeGen/ARM/a15-SD-dep.ll @@ -1,8 +1,8 @@ ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s -; CHECK-ENABLED: t1: -; CHECK-DISABLED: t1: +; CHECK-ENABLED-LABEL: t1: +; CHECK-DISABLED-LABEL: t1: define <2 x float> @t1(float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] @@ -11,8 +11,8 @@ define <2 x float> @t1(float %f) { ret <2 x float> %i2 } -; CHECK-ENABLED: t2: -; CHECK-DISABLED: t2: +; CHECK-ENABLED-LABEL: t2: +; CHECK-DISABLED-LABEL: t2: define <4 x float> @t2(float %g, float %f) { ; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] @@ -21,8 +21,8 @@ define <4 x float> @t2(float %g, float %f) { ret <4 x float> %i2 } -; CHECK-ENABLED: t3: -; CHECK-DISABLED: t3: +; CHECK-ENABLED-LABEL: t3: +; CHECK-DISABLED-LABEL: t3: define arm_aapcs_vfpcc <2 x float> @t3(float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0] @@ -31,8 +31,8 @@ define arm_aapcs_vfpcc <2 x float> @t3(float %f) { ret <2 x float> %i2 } -; CHECK-ENABLED: t4: -; CHECK-DISABLED: t4: +; CHECK-ENABLED-LABEL: t4: +; CHECK-DISABLED-LABEL: t4: define <2 x float> @t4(float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0] ; CHECK-DISABLED-NOT: vdup @@ -45,8 +45,8 @@ b: ret <2 x float> %i2 } -; CHECK-ENABLED: t5: -; CHECK-DISABLED: t5: +; CHECK-ENABLED-LABEL: t5: +; CHECK-DISABLED-LABEL: t5: define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) { ; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0] ; CHECK-ENABLED: vadd.f32 diff --git a/test/CodeGen/ARM/a15-partial-update.ll b/test/CodeGen/ARM/a15-partial-update.ll index 6306790d15..5747253d56 100644 --- a/test/CodeGen/ARM/a15-partial-update.ll +++ b/test/CodeGen/ARM/a15-partial-update.ll @@ -1,6 +1,6 @@ ; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s -; CHECK: t1: +; CHECK-LABEL: t1: define <2 x float> @t1(float* %A, <2 x float> %B) { ; The generated code for this test uses a vld1.32 instruction ; to write the lane 1 of a D register containing the value of @@ -15,7 +15,7 @@ define <2 x float> @t1(float* %A, <2 x float> %B) { ret <2 x float> %tmp3 } -; CHECK: t2: +; CHECK-LABEL: t2: define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) { entry: br label %loop diff --git a/test/CodeGen/ARM/arguments.ll b/test/CodeGen/ARM/arguments.ll index a8b42e63b7..e7fbf9f28e 100644 --- a/test/CodeGen/ARM/arguments.ll +++ b/test/CodeGen/ARM/arguments.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN define i32 @f1(i32 %a, i64 %b) { -; ELF: f1: +; ELF-LABEL: f1: ; ELF: mov r0, r2 -; DARWIN: f1: +; DARWIN-LABEL: f1: ; DARWIN: mov r0, r1 %tmp = call i32 @g1(i64 %b) ret i32 %tmp @@ -12,10 +12,10 @@ define i32 @f1(i32 %a, i64 %b) { ; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi. define i32 @f2() nounwind optsize { -; ELF: f2: +; ELF-LABEL: f2: ; ELF: mov [[REGISTER:(r[0-9]+)]], #128 ; ELF: str [[REGISTER]], [ -; DARWIN: f2: +; DARWIN-LABEL: f2: ; DARWIN: mov r3, #128 entry: %0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1] @@ -26,10 +26,10 @@ entry: ; test that on gnueabi a 64 bit value at this position will cause r3 to go ; unused and the value stored in [sp] -; ELF: f3: +; ELF-LABEL: f3: ; ELF: ldr r0, [sp] ; ELF-NEXT: mov pc, lr -; DARWIN: f3: +; DARWIN-LABEL: f3: ; DARWIN: mov r0, r3 ; DARWIN-NEXT: mov pc, lr define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) { diff --git a/test/CodeGen/ARM/arm-frameaddr.ll b/test/CodeGen/ARM/arm-frameaddr.ll index 2cf1422c66..9c4173ef0c 100644 --- a/test/CodeGen/ARM/arm-frameaddr.ll +++ b/test/CodeGen/ARM/arm-frameaddr.ll @@ -5,10 +5,10 @@ define i8* @t() nounwind { entry: -; DARWIN: t: +; DARWIN-LABEL: t: ; DARWIN: mov r0, r7 -; LINUX: t: +; LINUX-LABEL: t: ; LINUX: mov r0, r11 %0 = call i8* @llvm.frameaddress(i32 0) ret i8* %0 diff --git a/test/CodeGen/ARM/arm-returnaddr.ll b/test/CodeGen/ARM/arm-returnaddr.ll index 1272e8efc2..4266572b07 100644 --- a/test/CodeGen/ARM/arm-returnaddr.ll +++ b/test/CodeGen/ARM/arm-returnaddr.ll @@ -7,7 +7,7 @@ define i8* @rt0(i32 %x) nounwind readnone { entry: -; CHECK: rt0: +; CHECK-LABEL: rt0: ; CHECK: {r7, lr} ; CHECK: mov r0, lr %0 = tail call i8* @llvm.returnaddress(i32 0) @@ -16,7 +16,7 @@ entry: define i8* @rt2() nounwind readnone { entry: -; CHECK: rt2: +; CHECK-LABEL: rt2: ; CHECK: {r7, lr} ; CHECK: ldr r[[R0:[0-9]+]], [r7] ; CHECK: ldr r0, [r0] diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 93664e37e6..8ec829c8f6 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -12,7 +12,7 @@ define i64 @test1(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test1: +; CHECK-THUMB-LABEL: test1: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]] @@ -37,7 +37,7 @@ define i64 @test2(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test2: +; CHECK-THUMB-LABEL: test2: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]] @@ -62,7 +62,7 @@ define i64 @test3(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test3: +; CHECK-THUMB-LABEL: test3: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]] @@ -87,7 +87,7 @@ define i64 @test4(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test4: +; CHECK-THUMB-LABEL: test4: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]] @@ -112,7 +112,7 @@ define i64 @test5(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test5: +; CHECK-THUMB-LABEL: test5: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]] @@ -135,7 +135,7 @@ define i64 @test6(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test6: +; CHECK-THUMB-LABEL: test6: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} @@ -159,7 +159,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test7: +; CHECK-THUMB-LABEL: test7: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: cmp [[REG1]] @@ -188,7 +188,7 @@ define i64 @test8(i64* %ptr) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test8: +; CHECK-THUMB-LABEL: test8: ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: cmp [[REG1]] ; CHECK-THUMB: it eq @@ -214,7 +214,7 @@ define void @test9(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test9: +; CHECK-THUMB-LABEL: test9: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}} @@ -238,7 +238,7 @@ define i64 @test10(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test10: +; CHECK-THUMB-LABEL: test10: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] @@ -266,7 +266,7 @@ define i64 @test11(i64* %ptr, i64 %val) { ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test11: +; CHECK-THUMB-LABEL: test11: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] @@ -293,7 +293,7 @@ define i64 @test12(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test12: +; CHECK-THUMB-LABEL: test12: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] @@ -320,7 +320,7 @@ define i64 @test13(i64* %ptr, i64 %val) { ; CHECK: bne ; CHECK: dmb {{ish$}} -; CHECK-THUMB: test13: +; CHECK-THUMB-LABEL: test13: ; CHECK-THUMB: dmb {{ish$}} ; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]] ; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]] diff --git a/test/CodeGen/ARM/atomic-cmp.ll b/test/CodeGen/ARM/atomic-cmp.ll index 82726daebc..51ada693d0 100644 --- a/test/CodeGen/ARM/atomic-cmp.ll +++ b/test/CodeGen/ARM/atomic-cmp.ll @@ -3,11 +3,11 @@ ; rdar://8964854 define i8 @t(i8* %a, i8 %b, i8 %c) nounwind { -; ARM: t: +; ARM-LABEL: t: ; ARM: ldrexb ; ARM: strexb -; T2: t: +; T2-LABEL: t: ; T2: ldrexb ; T2: strexb %tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic diff --git a/test/CodeGen/ARM/atomicrmw_minmax.ll b/test/CodeGen/ARM/atomicrmw_minmax.ll index 69f1384e12..5befc228e0 100644 --- a/test/CodeGen/ARM/atomicrmw_minmax.ll +++ b/test/CodeGen/ARM/atomicrmw_minmax.ll @@ -1,6 +1,6 @@ ; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s -; CHECK: max: +; CHECK-LABEL: max: define i32 @max(i8 %ctx, i32* %ptr, i32 %val) { ; CHECK: ldrex @@ -10,7 +10,7 @@ define i32 @max(i8 %ctx, i32* %ptr, i32 %val) ret i32 %old } -; CHECK: min: +; CHECK-LABEL: min: define i32 @min(i8 %ctx, i32* %ptr, i32 %val) { ; CHECK: ldrex diff --git a/test/CodeGen/ARM/avoid-cpsr-rmw.ll b/test/CodeGen/ARM/avoid-cpsr-rmw.ll index c14f5302d3..0217a4a8fb 100644 --- a/test/CodeGen/ARM/avoid-cpsr-rmw.ll +++ b/test/CodeGen/ARM/avoid-cpsr-rmw.ll @@ -6,7 +6,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: muls [[REG:(r[0-9]+)]], r3, r2 ; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0 ; CHECK-NEXT: muls r0, [[REG]], [[REG2]] @@ -20,7 +20,7 @@ define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone { ; rdar://10357570 define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind { entry: -; CHECK: t2: +; CHECK-LABEL: t2: %tobool7 = icmp eq i32* %ptr2, null br i1 %tobool7, label %while.end, label %while.body @@ -54,7 +54,7 @@ while.end: ; rdar://12878928 define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize { entry: -; CHECK: t3: +; CHECK-LABEL: t3: %tobool7 = icmp eq i32* %ptr2, null br i1 %tobool7, label %while.end, label %while.body diff --git a/test/CodeGen/ARM/bfc.ll b/test/CodeGen/ARM/bfc.ll index c4a44b4472..3a17d2b8cf 100644 --- a/test/CodeGen/ARM/bfc.ll +++ b/test/CodeGen/ARM/bfc.ll @@ -2,7 +2,7 @@ ; 4278190095 = 0xff00000f define i32 @f1(i32 %a) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: bfc %tmp = and i32 %a, 4278190095 ret i32 %tmp @@ -10,7 +10,7 @@ define i32 @f1(i32 %a) { ; 4286578688 = 0xff800000 define i32 @f2(i32 %a) { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: bfc %tmp = and i32 %a, 4286578688 ret i32 %tmp @@ -18,7 +18,7 @@ define i32 @f2(i32 %a) { ; 4095 = 0x00000fff define i32 @f3(i32 %a) { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: bfc %tmp = and i32 %a, 4095 ret i32 %tmp diff --git a/test/CodeGen/ARM/bfi.ll b/test/CodeGen/ARM/bfi.ll index 84f3813975..72a4678099 100644 --- a/test/CodeGen/ARM/bfi.ll +++ b/test/CodeGen/ARM/bfi.ll @@ -52,7 +52,7 @@ define i32 @f4(i32 %a) nounwind { ; rdar://8458663 define i32 @f5(i32 %a, i32 %b) nounwind { entry: -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK-NOT: bfc ; CHECK: bfi r0, r1, #20, #4 %0 = and i32 %a, -15728641 @@ -65,7 +65,7 @@ entry: ; rdar://9609030 define i32 @f6(i32 %a, i32 %b) nounwind readnone { entry: -; CHECK: f6: +; CHECK-LABEL: f6: ; CHECK-NOT: bic ; CHECK: bfi r0, r1, #8, #9 %and = and i32 %a, -130817 diff --git a/test/CodeGen/ARM/bswap-inline-asm.ll b/test/CodeGen/ARM/bswap-inline-asm.ll index 472213d5f8..31f9d729cf 100644 --- a/test/CodeGen/ARM/bswap-inline-asm.ll +++ b/test/CodeGen/ARM/bswap-inline-asm.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s define i32 @t1(i32 %x) nounwind { -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK-NOT: InlineAsm ; CHECK: rev %asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind diff --git a/test/CodeGen/ARM/call-noret-minsize.ll b/test/CodeGen/ARM/call-noret-minsize.ll index df3c19eca6..e610d29d77 100644 --- a/test/CodeGen/ARM/call-noret-minsize.ll +++ b/test/CodeGen/ARM/call-noret-minsize.ll @@ -4,10 +4,10 @@ define void @t1() noreturn minsize nounwind ssp { entry: -; ARM: t1: +; ARM-LABEL: t1: ; ARM: bl _bar -; SWIFT: t1: +; SWIFT-LABEL: t1: ; SWIFT: bl _bar tail call void @bar() noreturn nounwind unreachable @@ -15,10 +15,10 @@ entry: define void @t2() noreturn minsize nounwind ssp { entry: -; ARM: t2: +; ARM-LABEL: t2: ; ARM: bl _t1 -; SWIFT: t2: +; SWIFT-LABEL: t2: ; SWIFT: bl _t1 tail call void @t1() noreturn nounwind unreachable diff --git a/test/CodeGen/ARM/call-noret.ll b/test/CodeGen/ARM/call-noret.ll index 27062dca38..bb56e8b863 100644 --- a/test/CodeGen/ARM/call-noret.ll +++ b/test/CodeGen/ARM/call-noret.ll @@ -4,11 +4,11 @@ define void @t1() noreturn nounwind ssp { entry: -; ARM: t1: +; ARM-LABEL: t1: ; ARM: mov lr, pc ; ARM: b _bar -; SWIFT: t1: +; SWIFT-LABEL: t1: ; SWIFT: mov lr, pc ; SWIFT: b _bar tail call void @bar() noreturn nounwind @@ -17,11 +17,11 @@ entry: define void @t2() noreturn nounwind ssp { entry: -; ARM: t2: +; ARM-LABEL: t2: ; ARM: mov lr, pc ; ARM: b _t1 -; SWIFT: t2: +; SWIFT-LABEL: t2: ; SWIFT: mov lr, pc ; SWIFT: b _t1 tail call void @t1() noreturn nounwind diff --git a/test/CodeGen/ARM/call-tc.ll b/test/CodeGen/ARM/call-tc.ll index c7e17ea353..d4636021b5 100644 --- a/test/CodeGen/ARM/call-tc.ll +++ b/test/CodeGen/ARM/call-tc.ll @@ -11,16 +11,16 @@ declare void @g(i32, i32, i32, i32) define void @t1() { -; CHECKELF: t1: +; CHECKELF-LABEL: t1: ; CHECKELF: bl g(PLT) call void @g( i32 1, i32 2, i32 3, i32 4 ) ret void } define void @t2() { -; CHECKV6: t2: +; CHECKV6-LABEL: t2: ; CHECKV6: bx r0 -; CHECKT2D: t2: +; CHECKT2D-LABEL: t2: ; CHECKT2D: ldr ; CHECKT2D-NEXT: ldr ; CHECKT2D-NEXT: bx r0 @@ -30,11 +30,11 @@ define void @t2() { } define void @t3() { -; CHECKV6: t3: +; CHECKV6-LABEL: t3: ; CHECKV6: b _t2 -; CHECKELF: t3: +; CHECKELF-LABEL: t3: ; CHECKELF: b t2(PLT) -; CHECKT2D: t3: +; CHECKT2D-LABEL: t3: ; CHECKT2D: b.w _t2 tail call void @t2( ) ; <i32> [#uses=0] @@ -44,9 +44,9 @@ define void @t3() { ; Sibcall optimization of expanded libcalls. rdar://8707777 define double @t4(double %a) nounwind readonly ssp { entry: -; CHECKV6: t4: +; CHECKV6-LABEL: t4: ; CHECKV6: b _sin -; CHECKELF: t4: +; CHECKELF-LABEL: t4: ; CHECKELF: b sin(PLT) %0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1] ret double %0 @@ -54,9 +54,9 @@ entry: define float @t5(float %a) nounwind readonly ssp { entry: -; CHECKV6: t5: +; CHECKV6-LABEL: t5: ; CHECKV6: b _sinf -; CHECKELF: t5: +; CHECKELF-LABEL: t5: ; CHECKELF: b sinf(PLT) %0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1] ret float %0 @@ -68,9 +68,9 @@ declare double @sin(double) nounwind readonly define i32 @t6(i32 %a, i32 %b) nounwind readnone { entry: -; CHECKV6: t6: +; CHECKV6-LABEL: t6: ; CHECKV6: b ___divsi3 -; CHECKELF: t6: +; CHECKELF-LABEL: t6: ; CHECKELF: b __aeabi_idiv(PLT) %0 = sdiv i32 %a, %b ret i32 %0 @@ -82,7 +82,7 @@ declare void @foo() nounwind define void @t7() nounwind { entry: -; CHECKT2D: t7: +; CHECKT2D-LABEL: t7: ; CHECKT2D: blxeq _foo ; CHECKT2D-NEXT: pop.w ; CHECKT2D-NEXT: b.w _foo @@ -101,7 +101,7 @@ bb: ; rdar://11140249 define i32 @t8(i32 %x) nounwind ssp { entry: -; CHECKT2D: t8: +; CHECKT2D-LABEL: t8: ; CHECKT2D-NOT: push %and = and i32 %x, 1 %tobool = icmp eq i32 %and, 0 @@ -147,7 +147,7 @@ declare i32 @c(i32) @x = external global i32, align 4 define i32 @t9() nounwind { -; CHECKT2D: t9: +; CHECKT2D-LABEL: t9: ; CHECKT2D: blx __ZN9MutexLockC1Ev ; CHECKT2D: blx __ZN9MutexLockD1Ev ; CHECKT2D: b.w ___divsi3 @@ -167,7 +167,7 @@ declare %class.MutexLock* @_ZN9MutexLockD1Ev(%class.MutexLock*) unnamed_addr nou ; Correctly preserve the input chain for the tailcall node in the bitcast case, ; otherwise the call to floorf is lost. define float @libcall_tc_test2(float* nocapture %a, float %b) { -; CHECKT2D: libcall_tc_test2: +; CHECKT2D-LABEL: libcall_tc_test2: ; CHECKT2D: blx _floorf ; CHECKT2D: b.w _truncf %1 = load float* %a, align 4 diff --git a/test/CodeGen/ARM/call_nolink.ll b/test/CodeGen/ARM/call_nolink.ll index 5ec7f74a60..48fa3a62ff 100644 --- a/test/CodeGen/ARM/call_nolink.ll +++ b/test/CodeGen/ARM/call_nolink.ll @@ -7,7 +7,7 @@ @numi = external global i32 ; <i32*> [#uses=1] @counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1] -; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i: +; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i: ; CHECK-NOT: bx lr define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() { @@ -56,7 +56,7 @@ define void @PR15520(void ()* %fn) { call void %fn() ret void -; CHECK: PR15520: +; CHECK-LABEL: PR15520: ; CHECK: mov lr, pc ; CHECK: mov pc, r0 } diff --git a/test/CodeGen/ARM/carry.ll b/test/CodeGen/ARM/carry.ll index bf51cd627b..f67987f8eb 100644 --- a/test/CodeGen/ARM/carry.ll +++ b/test/CodeGen/ARM/carry.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1(i64 %a, i64 %b) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: subs r ; CHECK: sbc r entry: @@ -10,7 +10,7 @@ entry: } define i64 @f2(i64 %a, i64 %b) { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: adc r ; CHECK: subs r ; CHECK: sbc r @@ -22,7 +22,7 @@ entry: ; add with live carry define i64 @f3(i32 %al, i32 %bl) { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: adds r ; CHECK: adc r entry: @@ -39,7 +39,7 @@ entry: ; rdar://10073745 define i64 @f4(i64 %x) nounwind readnone { entry: -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: rsbs r ; CHECK: rsc r %0 = sub nsw i64 0, %x @@ -49,7 +49,7 @@ entry: ; rdar://12559385 define i64 @f5(i32 %vi) { entry: -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK: movw [[REG:r[0-9]+]], #36102 ; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] %v0 = zext i32 %vi to i64 diff --git a/test/CodeGen/ARM/code-placement.ll b/test/CodeGen/ARM/code-placement.ll index 487ec690ea..70d85c91c8 100644 --- a/test/CodeGen/ARM/code-placement.ll +++ b/test/CodeGen/ARM/code-placement.ll @@ -7,7 +7,7 @@ define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind { entry: -; CHECK: t1: +; CHECK-LABEL: t1: %0 = icmp eq %struct.list_head* %list, null br i1 %0, label %bb2, label %bb @@ -33,7 +33,7 @@ bb2: ; rdar://8117827 define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: beq LBB1_[[RET:.]] %0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1] br i1 %0, label %bb5, label %bb.nph15 diff --git a/test/CodeGen/ARM/ctz.ll b/test/CodeGen/ARM/ctz.ll index 5ebca53b46..2c7efc7c5d 100644 --- a/test/CodeGen/ARM/ctz.ll +++ b/test/CodeGen/ARM/ctz.ll @@ -3,7 +3,7 @@ declare i32 @llvm.cttz.i32(i32, i1) define i32 @f1(i32 %a) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: rbit ; CHECK: clz %tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true ) diff --git a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll index 18f57ea41c..8950abdef6 100644 --- a/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll +++ b/test/CodeGen/ARM/dagcombine-anyexttozeroext.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s -; CHECK: f: +; CHECK-LABEL: f: define float @f(<4 x i16>* nocapture %in) { ; CHECK: vldr ; CHECK: vmovl.u16 diff --git a/test/CodeGen/ARM/data-in-code-annotations.ll b/test/CodeGen/ARM/data-in-code-annotations.ll index a66a9d1292..da70178225 100644 --- a/test/CodeGen/ARM/data-in-code-annotations.ll +++ b/test/CodeGen/ARM/data-in-code-annotations.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s define double @f1() nounwind { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: .data_region ; CHECK: .long 1413754129 ; CHECK: .long 1074340347 @@ -11,7 +11,7 @@ define double @f1() nounwind { define i32 @f2() { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: .data_region jt32 ; CHECK: .end_data_region diff --git a/test/CodeGen/ARM/divmod.ll b/test/CodeGen/ARM/divmod.ll index 577f8aa7d3..06d617293a 100644 --- a/test/CodeGen/ARM/divmod.ll +++ b/test/CodeGen/ARM/divmod.ll @@ -5,11 +5,11 @@ define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { entry: -; A8: foo: +; A8-LABEL: foo: ; A8: bl ___divmodsi4 ; A8-NOT: bl ___divmodsi4 -; SWIFT: foo: +; SWIFT-LABEL: foo: ; SWIFT: sdiv ; SWIFT: mls ; SWIFT-NOT: bl __divmodsi4 @@ -23,11 +23,11 @@ entry: define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp { entry: -; A8: bar: +; A8-LABEL: bar: ; A8: bl ___udivmodsi4 ; A8-NOT: bl ___udivmodsi4 -; SWIFT: bar: +; SWIFT-LABEL: bar: ; SWIFT: udiv ; SWIFT: mls ; SWIFT-NOT: bl __udivmodsi4 @@ -45,8 +45,8 @@ entry: define void @do_indent(i32 %cols) nounwind { entry: -; A8: do_indent: -; SWIFT: do_indent: +; A8-LABEL: do_indent: +; SWIFT-LABEL: do_indent: %0 = load i32* @flags, align 4 %1 = and i32 %0, 67108864 %2 = icmp eq i32 %1, 0 @@ -77,11 +77,11 @@ declare i8* @__memset_chk(i8*, i32, i32, i32) nounwind ; rdar://11714607 define i32 @howmany(i32 %x, i32 %y) nounwind { entry: -; A8: howmany: +; A8-LABEL: howmany: ; A8: bl ___udivmodsi4 ; A8-NOT: ___udivsi3 -; SWIFT: howmany: +; SWIFT-LABEL: howmany: ; SWIFT: udiv ; SWIFT: mls ; SWIFT-NOT: bl __udivmodsi4 diff --git a/test/CodeGen/ARM/ehabi-filters.ll b/test/CodeGen/ARM/ehabi-filters.ll index 4c92a2975d..cb5291b20e 100644 --- a/test/CodeGen/ARM/ehabi-filters.ll +++ b/test/CodeGen/ARM/ehabi-filters.ll @@ -15,7 +15,7 @@ declare void @__cxa_throw(i8*, i8*, i8*) declare void @__cxa_call_unexpected(i8*) define i32 @main() { -; CHECK: main: +; CHECK-LABEL: main: entry: %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind %0 = bitcast i8* %exception.i to i32* diff --git a/test/CodeGen/ARM/ehabi.ll b/test/CodeGen/ARM/ehabi.ll index b05d4beee8..66446528c3 100644 --- a/test/CodeGen/ARM/ehabi.ll +++ b/test/CodeGen/ARM/ehabi.ll @@ -112,7 +112,7 @@ declare void @__cxa_end_catch() declare void @_ZSt9terminatev() -; CHECK-FP: _Z4testiiiiiddddd: +; CHECK-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-FP: .fnstart ; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} @@ -124,7 +124,7 @@ declare void @_ZSt9terminatev() ; CHECK-FP: .handlerdata ; CHECK-FP: .fnend -; CHECK-FP-ELIM: _Z4testiiiiiddddd: +; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd: ; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} @@ -134,7 +134,7 @@ declare void @_ZSt9terminatev() ; CHECK-FP-ELIM: .handlerdata ; CHECK-FP-ELIM: .fnend -; CHECK-V7-FP: _Z4testiiiiiddddd: +; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd: ; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .save {r4, r11, lr} ; CHECK-V7-FP: push {r4, r11, lr} @@ -148,7 +148,7 @@ declare void @_ZSt9terminatev() ; CHECK-V7-FP: .handlerdata ; CHECK-V7-FP: .fnend -; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd: +; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd: ; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .save {r4, lr} ; CHECK-V7-FP-ELIM: push {r4, lr} @@ -173,7 +173,7 @@ entry: ret void } -; CHECK-FP: test2: +; CHECK-FP-LABEL: test2: ; CHECK-FP: .fnstart ; CHECK-FP: .save {r11, lr} ; CHECK-FP: push {r11, lr} @@ -183,7 +183,7 @@ entry: ; CHECK-FP: mov pc, lr ; CHECK-FP: .fnend -; CHECK-FP-ELIM: test2: +; CHECK-FP-ELIM-LABEL: test2: ; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .save {r11, lr} ; CHECK-FP-ELIM: push {r11, lr} @@ -191,7 +191,7 @@ entry: ; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: .fnend -; CHECK-V7-FP: test2: +; CHECK-V7-FP-LABEL: test2: ; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .save {r11, lr} ; CHECK-V7-FP: push {r11, lr} @@ -200,7 +200,7 @@ entry: ; CHECK-V7-FP: pop {r11, pc} ; CHECK-V7-FP: .fnend -; CHECK-V7-FP-ELIM: test2: +; CHECK-V7-FP-ELIM-LABEL: test2: ; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .save {r11, lr} ; CHECK-V7-FP-ELIM: push {r11, lr} @@ -229,7 +229,7 @@ entry: ret i32 %add6 } -; CHECK-FP: test3: +; CHECK-FP-LABEL: test3: ; CHECK-FP: .fnstart ; CHECK-FP: .save {r4, r5, r11, lr} ; CHECK-FP: push {r4, r5, r11, lr} @@ -239,7 +239,7 @@ entry: ; CHECK-FP: mov pc, lr ; CHECK-FP: .fnend -; CHECK-FP-ELIM: test3: +; CHECK-FP-ELIM-LABEL: test3: ; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: .save {r4, r5, r11, lr} ; CHECK-FP-ELIM: push {r4, r5, r11, lr} @@ -247,7 +247,7 @@ entry: ; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: .fnend -; CHECK-V7-FP: test3: +; CHECK-V7-FP-LABEL: test3: ; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: .save {r4, r5, r11, lr} ; CHECK-V7-FP: push {r4, r5, r11, lr} @@ -256,7 +256,7 @@ entry: ; CHECK-V7-FP: pop {r4, r5, r11, pc} ; CHECK-V7-FP: .fnend -; CHECK-V7-FP-ELIM: test3: +; CHECK-V7-FP-ELIM-LABEL: test3: ; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr} ; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr} @@ -273,25 +273,25 @@ entry: ret void } -; CHECK-FP: test4: +; CHECK-FP-LABEL: test4: ; CHECK-FP: .fnstart ; CHECK-FP: mov pc, lr ; CHECK-FP: .cantunwind ; CHECK-FP: .fnend -; CHECK-FP-ELIM: test4: +; CHECK-FP-ELIM-LABEL: test4: ; CHECK-FP-ELIM: .fnstart ; CHECK-FP-ELIM: mov pc, lr ; CHECK-FP-ELIM: .cantunwind ; CHECK-FP-ELIM: .fnend -; CHECK-V7-FP: test4: +; CHECK-V7-FP-LABEL: test4: ; CHECK-V7-FP: .fnstart ; CHECK-V7-FP: bx lr ; CHECK-V7-FP: .cantunwind ; CHECK-V7-FP: .fnend -; CHECK-V7-FP-ELIM: test4: +; CHECK-V7-FP-ELIM-LABEL: test4: ; CHECK-V7-FP-ELIM: .fnstart ; CHECK-V7-FP-ELIM: bx lr ; CHECK-V7-FP-ELIM: .cantunwind diff --git a/test/CodeGen/ARM/extload-knownzero.ll b/test/CodeGen/ARM/extload-knownzero.ll index 8fd6b6bd77..8ccf58c391 100644 --- a/test/CodeGen/ARM/extload-knownzero.ll +++ b/test/CodeGen/ARM/extload-knownzero.ll @@ -3,7 +3,7 @@ define void @foo(i16* %ptr, i32 %a) nounwind { entry: -; CHECK: foo: +; CHECK-LABEL: foo: %tmp1 = icmp ult i32 %a, 100 br i1 %tmp1, label %bb1, label %bb2 bb1: diff --git a/test/CodeGen/ARM/fast-isel-br-const.ll b/test/CodeGen/ARM/fast-isel-br-const.ll index 293302f572..2e28b08fc8 100644 --- a/test/CodeGen/ARM/fast-isel-br-const.ll +++ b/test/CodeGen/ARM/fast-isel-br-const.ll @@ -4,8 +4,8 @@ define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp { entry: -; THUMB: t1: -; ARM: t1: +; THUMB-LABEL: t1: +; ARM-LABEL: t1: %x = add i32 %a, %b br i1 1, label %if.then, label %if.else ; THUMB-NOT: b {{\.?}}LBB0_1 diff --git a/test/CodeGen/ARM/fast-isel-ext.ll b/test/CodeGen/ARM/fast-isel-ext.ll index 38ce481571..15d0d3ce5f 100644 --- a/test/CodeGen/ARM/fast-isel-ext.ll +++ b/test/CodeGen/ARM/fast-isel-ext.ll @@ -17,54 +17,54 @@ ; zext define i8 @zext_1_8(i1 %a) nounwind ssp { -; v7: zext_1_8: +; v7-LABEL: zext_1_8: ; v7: and r0, r0, #1 -; prev6: zext_1_8: +; prev6-LABEL: zext_1_8: ; prev6: and r0, r0, #1 %r = zext i1 %a to i8 ret i8 %r } define i16 @zext_1_16(i1 %a) nounwind ssp { -; v7: zext_1_16: +; v7-LABEL: zext_1_16: ; v7: and r0, r0, #1 -; prev6: zext_1_16: +; prev6-LABEL: zext_1_16: ; prev6: and r0, r0, #1 %r = zext i1 %a to i16 ret i16 %r } define i32 @zext_1_32(i1 %a) nounwind ssp { -; v7: zext_1_32: +; v7-LABEL: zext_1_32: ; v7: and r0, r0, #1 -; prev6: zext_1_32: +; prev6-LABEL: zext_1_32: ; prev6: and r0, r0, #1 %r = zext i1 %a to i32 ret i32 %r } define i16 @zext_8_16(i8 %a) nounwind ssp { -; v7: zext_8_16: +; v7-LABEL: zext_8_16: ; v7: and r0, r0, #255 -; prev6: zext_8_16: +; prev6-LABEL: zext_8_16: ; prev6: and r0, r0, #255 %r = zext i8 %a to i16 ret i16 %r } define i32 @zext_8_32(i8 %a) nounwind ssp { -; v7: zext_8_32: +; v7-LABEL: zext_8_32: ; v7: and r0, r0, #255 -; prev6: zext_8_32: +; prev6-LABEL: zext_8_32: ; prev6: and r0, r0, #255 %r = zext i8 %a to i32 ret i32 %r } define i32 @zext_16_32(i16 %a) nounwind ssp { -; v7: zext_16_32: +; v7-LABEL: zext_16_32: ; v7: uxth r0, r0 -; prev6: zext_16_32: +; prev6-LABEL: zext_16_32: ; prev6: lsl{{s?}} r0, r0, #16 ; prev6: lsr{{s?}} r0, r0, #16 %r = zext i16 %a to i32 @@ -74,10 +74,10 @@ define i32 @zext_16_32(i16 %a) nounwind ssp { ; sext define i8 @sext_1_8(i1 %a) nounwind ssp { -; v7: sext_1_8: +; v7-LABEL: sext_1_8: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6: sext_1_8: +; prev6-LABEL: sext_1_8: ; prev6: lsl{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i8 @@ -85,10 +85,10 @@ define i8 @sext_1_8(i1 %a) nounwind ssp { } define i16 @sext_1_16(i1 %a) nounwind ssp { -; v7: sext_1_16: +; v7-LABEL: sext_1_16: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6: sext_1_16: +; prev6-LABEL: sext_1_16: ; prev6: lsl{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i16 @@ -96,10 +96,10 @@ define i16 @sext_1_16(i1 %a) nounwind ssp { } define i32 @sext_1_32(i1 %a) nounwind ssp { -; v7: sext_1_32: +; v7-LABEL: sext_1_32: ; v7: lsl{{s?}} r0, r0, #31 ; v7: asr{{s?}} r0, r0, #31 -; prev6: sext_1_32: +; prev6-LABEL: sext_1_32: ; prev6: lsl{{s?}} r0, r0, #31 ; prev6: asr{{s?}} r0, r0, #31 %r = sext i1 %a to i32 @@ -107,9 +107,9 @@ define i32 @sext_1_32(i1 %a) nounwind ssp { } define i16 @sext_8_16(i8 %a) nounwind ssp { -; v7: sext_8_16: +; v7-LABEL: sext_8_16: ; v7: sxtb r0, r0 -; prev6: sext_8_16: +; prev6-LABEL: sext_8_16: ; prev6: lsl{{s?}} r0, r0, #24 ; prev6: asr{{s?}} r0, r0, #24 %r = sext i8 %a to i16 @@ -117,9 +117,9 @@ define i16 @sext_8_16(i8 %a) nounwind ssp { } define i32 @sext_8_32(i8 %a) nounwind ssp { -; v7: sext_8_32: +; v7-LABEL: sext_8_32: ; v7: sxtb r0, r0 -; prev6: sext_8_32: +; prev6-LABEL: sext_8_32: ; prev6: lsl{{s?}} r0, r0, #24 ; prev6: asr{{s?}} r0, r0, #24 %r = sext i8 %a to i32 @@ -127,9 +127,9 @@ define i32 @sext_8_32(i8 %a) nounwind ssp { } define i32 @sext_16_32(i16 %a) nounwind ssp { -; v7: sext_16_32: +; v7-LABEL: sext_16_32: ; v7: sxth r0, r0 -; prev6: sext_16_32: +; prev6-LABEL: sext_16_32: ; prev6: lsl{{s?}} r0, r0, #16 ; prev6: asr{{s?}} r0, r0, #16 %r = sext i16 %a to i32 diff --git a/test/CodeGen/ARM/fast-isel-frameaddr.ll b/test/CodeGen/ARM/fast-isel-frameaddr.ll index 5ae7ad7f14..8542bb5e27 100644 --- a/test/CodeGen/ARM/fast-isel-frameaddr.ll +++ b/test/CodeGen/ARM/fast-isel-frameaddr.ll @@ -5,22 +5,22 @@ define i8* @frameaddr_index0() nounwind { entry: -; DARWIN-ARM: frameaddr_index0: +; DARWIN-ARM-LABEL: frameaddr_index0: ; DARWIN-ARM: push {r7} ; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r0, r7 -; DARWIN-THUMB2: frameaddr_index0: +; DARWIN-THUMB2-LABEL: frameaddr_index0: ; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r0, r7 -; LINUX-ARM: frameaddr_index0: +; LINUX-ARM-LABEL: frameaddr_index0: ; LINUX-ARM: push {r11} ; LINUX-ARM: mov r11, sp ; LINUX-ARM: mov r0, r11 -; LINUX-THUMB2: frameaddr_index0: +; LINUX-THUMB2-LABEL: frameaddr_index0: ; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r0, r7 @@ -31,24 +31,24 @@ entry: define i8* @frameaddr_index1() nounwind { entry: -; DARWIN-ARM: frameaddr_index1: +; DARWIN-ARM-LABEL: frameaddr_index1: ; DARWIN-ARM: push {r7} ; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r0, r7 ; DARWIN-ARM: ldr r0, [r0] -; DARWIN-THUMB2: frameaddr_index1: +; DARWIN-THUMB2-LABEL: frameaddr_index1: ; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r0, r7 ; DARWIN-THUMB2: ldr r0, [r0] -; LINUX-ARM: frameaddr_index1: +; LINUX-ARM-LABEL: frameaddr_index1: ; LINUX-ARM: push {r11} ; LINUX-ARM: mov r11, sp ; LINUX-ARM: ldr r0, [r11] -; LINUX-THUMB2: frameaddr_index1: +; LINUX-THUMB2-LABEL: frameaddr_index1: ; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r0, r7 @@ -60,7 +60,7 @@ entry: define i8* @frameaddr_index3() nounwind { entry: -; DARWIN-ARM: frameaddr_index3: +; DARWIN-ARM-LABEL: frameaddr_index3: ; DARWIN-ARM: push {r7} ; DARWIN-ARM: mov r7, sp ; DARWIN-ARM: mov r0, r7 @@ -68,7 +68,7 @@ entry: ; DARWIN-ARM: ldr r0, [r0] ; DARWIN-ARM: ldr r0, [r0] -; DARWIN-THUMB2: frameaddr_index3: +; DARWIN-THUMB2-LABEL: frameaddr_index3: ; DARWIN-THUMB2: str r7, [sp, #-4]! ; DARWIN-THUMB2: mov r7, sp ; DARWIN-THUMB2: mov r0, r7 @@ -76,14 +76,14 @@ entry: ; DARWIN-THUMB2: ldr r0, [r0] ; DARWIN-THUMB2: ldr r0, [r0] -; LINUX-ARM: frameaddr_index3: +; LINUX-ARM-LABEL: frameaddr_index3: ; LINUX-ARM: push {r11} ; LINUX-ARM: mov r11, sp ; LINUX-ARM: ldr r0, [r11] ; LINUX-ARM: ldr r0, [r0] ; LINUX-ARM: ldr r0, [r0] -; LINUX-THUMB2: frameaddr_index3: +; LINUX-THUMB2-LABEL: frameaddr_index3: ; LINUX-THUMB2: str r7, [sp, #-4]! ; LINUX-THUMB2: mov r7, sp ; LINUX-THUMB2: mov r0, r7 diff --git a/test/CodeGen/ARM/fmacs.ll b/test/CodeGen/ARM/fmacs.ll index b63f609e75..f2486c65d3 100644 --- a/test/CodeGen/ARM/fmacs.ll +++ b/test/CodeGen/ARM/fmacs.ll @@ -6,13 +6,13 @@ define float @t1(float %acc, float %a, float %b) { entry: -; VFP2: t1: +; VFP2-LABEL: t1: ; VFP2: vmla.f32 -; NEON: t1: +; NEON-LABEL: t1: ; NEON: vmla.f32 -; A8: t1: +; A8-LABEL: t1: ; A8: vmul.f32 ; A8: vadd.f32 %0 = fmul float %a, %b @@ -22,13 +22,13 @@ entry: define double @t2(double %acc, double %a, double %b) { entry: -; VFP2: t2: +; VFP2-LABEL: t2: ; VFP2: vmla.f64 -; NEON: t2: +; NEON-LABEL: t2: ; NEON: vmla.f64 -; A8: t2: +; A8-LABEL: t2: ; A8: vmul.f64 ; A8: vadd.f64 %0 = fmul double %a, %b @@ -38,13 +38,13 @@ entry: define float @t3(float %acc, float %a, float %b) { entry: -; VFP2: t3: +; VFP2-LABEL: t3: ; VFP2: vmla.f32 -; NEON: t3: +; NEON-LABEL: t3: ; NEON: vmla.f32 -; A8: t3: +; A8-LABEL: t3: ; A8: vmul.f32 ; A8: vadd.f32 %0 = fmul float %a, %b @@ -56,18 +56,18 @@ entry: ; rdar://8659675 define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) { entry: -; A8: t4: +; A8-LABEL: t4: ; A8: vmul.f32 ; A8: vmul.f32 ; A8: vadd.f32 ; A8: vadd.f32 ; Two vmla with now RAW hazard -; A9: t4: +; A9-LABEL: t4: ; A9: vmla.f32 ; A9: vmla.f32 -; HARD: t4: +; HARD-LABEL: t4: ; HARD: vmla.f32 s0, s1, s2 ; HARD: vmla.f32 s3, s1, s4 %0 = fmul float %a, %b @@ -81,18 +81,18 @@ entry: define float @t5(float %a, float %b, float %c, float %d, float %e) { entry: -; A8: t5: +; A8-LABEL: t5: ; A8: vmul.f32 ; A8: vmul.f32 ; A8: vadd.f32 ; A8: vadd.f32 -; A9: t5: +; A9-LABEL: t5: ; A9: vmla.f32 ; A9: vmul.f32 ; A9: vadd.f32 -; HARD: t5: +; HARD-LABEL: t5: ; HARD: vmla.f32 s4, s0, s1 ; HARD: vmul.f32 s0, s2, s3 ; HARD: vadd.f32 s0, s4, s0 diff --git a/test/CodeGen/ARM/fmscs.ll b/test/CodeGen/ARM/fmscs.ll index a182833a7a..f16ec172cb 100644 --- a/test/CodeGen/ARM/fmscs.ll +++ b/test/CodeGen/ARM/fmscs.ll @@ -4,13 +4,13 @@ define float @t1(float %acc, float %a, float %b) { entry: -; VFP2: t1: +; VFP2-LABEL: t1: ; VFP2: vnmls.f32 -; NEON: t1: +; NEON-LABEL: t1: ; NEON: vnmls.f32 -; A8: t1: +; A8-LABEL: t1: ; A8: vmul.f32 ; A8: vsub.f32 %0 = fmul float %a, %b @@ -20,13 +20,13 @@ entry: define double @t2(double %acc, double %a, double %b) { entry: -; VFP2: t2: +; VFP2-LABEL: t2: ; VFP2: vnmls.f64 -; NEON: t2: +; NEON-LABEL: t2: ; NEON: vnmls.f64 -; A8: t2: +; A8-LABEL: t2: ; A8: vmul.f64 ; A8: vsub.f64 %0 = fmul double %a, %b diff --git a/test/CodeGen/ARM/fnmacs.ll b/test/CodeGen/ARM/fnmacs.ll index 1763d46e06..825feaa045 100644 --- a/test/CodeGen/ARM/fnmacs.ll +++ b/test/CodeGen/ARM/fnmacs.ll @@ -4,13 +4,13 @@ define float @t1(float %acc, float %a, float %b) { entry: -; VFP2: t1: +; VFP2-LABEL: t1: ; VFP2: vmls.f32 -; NEON: t1: +; NEON-LABEL: t1: ; NEON: vmls.f32 -; A8: t1: +; A8-LABEL: t1: ; A8: vmul.f32 ; A8: vsub.f32 %0 = fmul float %a, %b @@ -20,13 +20,13 @@ entry: define double @t2(double %acc, double %a, double %b) { entry: -; VFP2: t2: +; VFP2-LABEL: t2: ; VFP2: vmls.f64 -; NEON: t2: +; NEON-LABEL: t2: ; NEON: vmls.f64 -; A8: t2: +; A8-LABEL: t2: ; A8: vmul.f64 ; A8: vsub.f64 %0 = fmul double %a, %b diff --git a/test/CodeGen/ARM/fnmscs.ll b/test/CodeGen/ARM/fnmscs.ll index c308061734..78ccb6095e 100644 --- a/test/CodeGen/ARM/fnmscs.ll +++ b/test/CodeGen/ARM/fnmscs.ll @@ -7,17 +7,17 @@ define float @t1(float %acc, float %a, float %b) nounwind { entry: -; VFP2: t1: +; VFP2-LABEL: t1: ; VFP2: vnmla.f32 -; NEON: t1: +; NEON-LABEL: t1: ; NEON: vnmla.f32 -; A8U: t1: +; A8U-LABEL: t1: ; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} -; A8: t1: +; A8-LABEL: t1: ; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} %0 = fmul float %a, %b @@ -28,17 +28,17 @@ entry: define float @t2(float %acc, float %a, float %b) nounwind { entry: -; VFP2: t2: +; VFP2-LABEL: t2: ; VFP2: vnmla.f32 -; NEON: t2: +; NEON-LABEL: t2: ; NEON: vnmla.f32 -; A8U: t2: +; A8U-LABEL: t2: ; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} ; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}} -; A8: t2: +; A8-LABEL: t2: ; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}} ; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}} %0 = fmul float %a, %b @@ -49,17 +49,17 @@ entry: define double @t3(double %acc, double %a, double %b) nounwind { entry: -; VFP2: t3: +; VFP2-LABEL: t3: ; VFP2: vnmla.f64 -; NEON: t3: +; NEON-LABEL: t3: ; NEON: vnmla.f64 -; A8U: t3: +; A8U-LABEL: t3: ; A8U: vnmul.f64 d ; A8U: vsub.f64 d -; A8: t3: +; A8-LABEL: t3: ; A8: vnmul.f64 d ; A8: vsub.f64 d %0 = fmul double %a, %b @@ -70,17 +70,17 @@ entry: define double @t4(double %acc, double %a, double %b) nounwind { entry: -; VFP2: t4: +; VFP2-LABEL: t4: ; VFP2: vnmla.f64 -; NEON: t4: +; NEON-LABEL: t4: ; NEON: vnmla.f64 -; A8U: t4: +; A8U-LABEL: t4: ; A8U: vnmul.f64 d ; A8U: vsub.f64 d -; A8: t4: +; A8-LABEL: t4: ; A8: vnmul.f64 d ; A8: vsub.f64 d %0 = fmul double %a, %b diff --git a/test/CodeGen/ARM/fp.ll b/test/CodeGen/ARM/fp.ll index 93601cf9d6..fbf3a4a56a 100644 --- a/test/CodeGen/ARM/fp.ll +++ b/test/CodeGen/ARM/fp.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s define float @f(i32 %a) { -;CHECK: f: +;CHECK-LABEL: f: ;CHECK: vmov ;CHECK-NEXT: vcvt.f32.s32 ;CHECK-NEXT: vmov @@ -11,7 +11,7 @@ entry: } define double @g(i32 %a) { -;CHECK: g: +;CHECK-LABEL: g: ;CHECK: vmov ;CHECK-NEXT: vcvt.f64.s32 ;CHECK-NEXT: vmov @@ -21,7 +21,7 @@ entry: } define double @uint_to_double(i32 %a) { -;CHECK: uint_to_double: +;CHECK-LABEL: uint_to_double: ;CHECK: vmov ;CHECK-NEXT: vcvt.f64.u32 ;CHECK-NEXT: vmov @@ -31,7 +31,7 @@ entry: } define float @uint_to_float(i32 %a) { -;CHECK: uint_to_float: +;CHECK-LABEL: uint_to_float: ;CHECK: vmov ;CHECK-NEXT: vcvt.f32.u32 ;CHECK-NEXT: vmov @@ -41,7 +41,7 @@ entry: } define double @h(double* %v) { -;CHECK: h: +;CHECK-LABEL: h: ;CHECK: vldr ;CHECK-NEXT: vmov entry: @@ -50,20 +50,20 @@ entry: } define float @h2() { -;CHECK: h2: +;CHECK-LABEL: h2: ;CHECK: mov r0, #1065353216 entry: ret float 1.000000e+00 } define double @f2(double %a) { -;CHECK: f2: +;CHECK-LABEL: f2: ;CHECK-NOT: vmov ret double %a } define void @f3() { -;CHECK: f3: +;CHECK-LABEL: f3: ;CHECK-NOT: vmov ;CHECK: f4 entry: diff --git a/test/CodeGen/ARM/fp16.ll b/test/CodeGen/ARM/fp16.ll index 1261ea5021..a5c1aed277 100644 --- a/test/CodeGen/ARM/fp16.ll +++ b/test/CodeGen/ARM/fp16.ll @@ -8,8 +8,8 @@ target triple = "armv7-eabi" @z = common global i16 0 define arm_aapcs_vfpcc void @foo() nounwind { -; CHECK: foo: -; CHECK-FP6: foo: +; CHECK-LABEL: foo: +; CHECK-FP6-LABEL: foo: entry: %0 = load i16* @x, align 2 %1 = load i16* @y, align 2 diff --git a/test/CodeGen/ARM/fparith.ll b/test/CodeGen/ARM/fparith.ll index 40ea33bece..cc880148da 100644 --- a/test/CodeGen/ARM/fparith.ll +++ b/test/CodeGen/ARM/fparith.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s define float @f1(float %a, float %b) { -;CHECK: f1: +;CHECK-LABEL: f1: ;CHECK: vadd.f32 entry: %tmp = fadd float %a, %b ; <float> [#uses=1] @@ -9,7 +9,7 @@ entry: } define double @f2(double %a, double %b) { -;CHECK: f2: +;CHECK-LABEL: f2: ;CHECK: vadd.f64 entry: %tmp = fadd double %a, %b ; <double> [#uses=1] @@ -17,7 +17,7 @@ entry: } define float @f3(float %a, float %b) { -;CHECK: f3: +;CHECK-LABEL: f3: ;CHECK: vmul.f32 entry: %tmp = fmul float %a, %b ; <float> [#uses=1] @@ -25,7 +25,7 @@ entry: } define double @f4(double %a, double %b) { -;CHECK: f4: +;CHECK-LABEL: f4: ;CHECK: vmul.f64 entry: %tmp = fmul double %a, %b ; <double> [#uses=1] @@ -33,7 +33,7 @@ entry: } define float @f5(float %a, float %b) { -;CHECK: f5: +;CHECK-LABEL: f5: ;CHECK: vsub.f32 entry: %tmp = fsub float %a, %b ; <float> [#uses=1] @@ -41,7 +41,7 @@ entry: } define double @f6(double %a, double %b) { -;CHECK: f6: +;CHECK-LABEL: f6: ;CHECK: vsub.f64 entry: %tmp = fsub double %a, %b ; <double> [#uses=1] @@ -49,7 +49,7 @@ entry: } define float @f7(float %a) { -;CHECK: f7: +;CHECK-LABEL: f7: ;CHECK: eor entry: %tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1] @@ -57,7 +57,7 @@ entry: } define double @f8(double %a) { -;CHECK: f8: +;CHECK-LABEL: f8: ;CHECK: vneg.f64 entry: %tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1] @@ -65,7 +65,7 @@ entry: } define float @f9(float %a, float %b) { -;CHECK: f9: +;CHECK-LABEL: f9: ;CHECK: vdiv.f32 entry: %tmp1 = fdiv float %a, %b ; <float> [#uses=1] @@ -73,7 +73,7 @@ entry: } define double @f10(double %a, double %b) { -;CHECK: f10: +;CHECK-LABEL: f10: ;CHECK: vdiv.f64 entry: %tmp1 = fdiv double %a, %b ; <double> [#uses=1] @@ -81,7 +81,7 @@ entry: } define float @f11(float %a) { -;CHECK: f11: +;CHECK-LABEL: f11: ;CHECK: bic entry: %tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1] @@ -91,7 +91,7 @@ entry: declare float @fabsf(float) define double @f12(double %a) { -;CHECK: f12: +;CHECK-LABEL: f12: ;CHECK: vabs.f64 entry: %tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1] diff --git a/test/CodeGen/ARM/fpcmp-opt.ll b/test/CodeGen/ARM/fpcmp-opt.ll index 2d8f7108e0..902dfa2f96 100644 --- a/test/CodeGen/ARM/fpcmp-opt.ll +++ b/test/CodeGen/ARM/fpcmp-opt.ll @@ -5,7 +5,7 @@ ; Disable this optimization unless we know one of them is zero. define arm_apcscc i32 @t1(float* %a, float* %b) nounwind { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: vldr [[S0:s[0-9]+]], ; CHECK: vldr [[S1:s[0-9]+]], ; CHECK: vcmpe.f32 [[S1]], [[S0]] @@ -29,7 +29,7 @@ bb2: ; +0.0 == -0.0 define arm_apcscc i32 @t2(double* %a, double* %b) nounwind { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK-NOT: vldr ; CHECK: ldr [[REG1:(r[0-9]+)]], [r0] ; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4] @@ -55,7 +55,7 @@ bb2: define arm_apcscc i32 @t3(float* %a, float* %b) nounwind { entry: -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK-NOT: vldr ; CHECK: ldr [[REG3:(r[0-9]+)]], [r0] ; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648 diff --git a/test/CodeGen/ARM/fpcmp.ll b/test/CodeGen/ARM/fpcmp.ll index 260ec49cd8..916a1ae495 100644 --- a/test/CodeGen/ARM/fpcmp.ll +++ b/test/CodeGen/ARM/fpcmp.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s define i32 @f1(float %a) { -;CHECK: f1: +;CHECK-LABEL: f1: ;CHECK: vcmpe.f32 ;CHECK: movmi entry: @@ -11,7 +11,7 @@ entry: } define i32 @f2(float %a) { -;CHECK: f2: +;CHECK-LABEL: f2: ;CHECK: vcmpe.f32 ;CHECK: moveq entry: @@ -21,7 +21,7 @@ entry: } define i32 @f3(float %a) { -;CHECK: f3: +;CHECK-LABEL: f3: ;CHECK: vcmpe.f32 ;CHECK: movgt entry: @@ -31,7 +31,7 @@ entry: } define i32 @f4(float %a) { -;CHECK: f4: +;CHECK-LABEL: f4: ;CHECK: vcmpe.f32 ;CHECK: movge entry: @@ -41,7 +41,7 @@ entry: } define i32 @f5(float %a) { -;CHECK: f5: +;CHECK-LABEL: f5: ;CHECK: vcmpe.f32 ;CHECK: movls entry: @@ -51,7 +51,7 @@ entry: } define i32 @f6(float %a) { -;CHECK: f6: +;CHECK-LABEL: f6: ;CHECK: vcmpe.f32 ;CHECK: movne entry: @@ -61,7 +61,7 @@ entry: } define i32 @g1(double %a) { -;CHECK: g1: +;CHECK-LABEL: g1: ;CHECK: vcmpe.f64 ;CHECK: movmi entry: diff --git a/test/CodeGen/ARM/fpcmp_ueq.ll b/test/CodeGen/ARM/fpcmp_ueq.ll index 4a4c5b1c8b..d84c7ae82e 100644 --- a/test/CodeGen/ARM/fpcmp_ueq.ll +++ b/test/CodeGen/ARM/fpcmp_ueq.ll @@ -3,7 +3,7 @@ define i32 @f7(float %a, float %b) { entry: -; CHECK: f7: +; CHECK-LABEL: f7: ; CHECK: vcmpe.f32 ; CHECK: vmrs APSR_nzcv, fpscr ; CHECK: movweq diff --git a/test/CodeGen/ARM/fpconsts.ll b/test/CodeGen/ARM/fpconsts.ll index 638dde9d8a..0679a47ded 100644 --- a/test/CodeGen/ARM/fpconsts.ll +++ b/test/CodeGen/ARM/fpconsts.ll @@ -2,7 +2,7 @@ define float @t1(float %x) nounwind readnone optsize { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: vmov.f32 s{{.*}}, #4.000000e+00 %0 = fadd float %x, 4.000000e+00 ret float %0 @@ -10,7 +10,7 @@ entry: define double @t2(double %x) nounwind readnone optsize { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: vmov.f64 d{{.*}}, #3.000000e+00 %0 = fadd double %x, 3.000000e+00 ret double %0 @@ -18,7 +18,7 @@ entry: define double @t3(double %x) nounwind readnone optsize { entry: -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01 %0 = fmul double %x, -1.300000e+01 ret double %0 @@ -26,7 +26,7 @@ entry: define float @t4(float %x) nounwind readnone optsize { entry: -; CHECK: t4: +; CHECK-LABEL: t4: ; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01 %0 = fmul float %x, -2.400000e+01 ret float %0 diff --git a/test/CodeGen/ARM/fpconv.ll b/test/CodeGen/ARM/fpconv.ll index 1b4c008bb7..326e0628b4 100644 --- a/test/CodeGen/ARM/fpconv.ll +++ b/test/CodeGen/ARM/fpconv.ll @@ -2,9 +2,9 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s define float @f1(double %x) { -;CHECK-VFP: f1: +;CHECK-VFP-LABEL: f1: ;CHECK-VFP: vcvt.f32.f64 -;CHECK: f1: +;CHECK-LABEL: f1: ;CHECK: truncdfsf2 entry: %tmp1 = fptrunc double %x to float ; <float> [#uses=1] @@ -12,9 +12,9 @@ entry: } define double @f2(float %x) { -;CHECK-VFP: f2: +;CHECK-VFP-LABEL: f2: ;CHECK-VFP: vcvt.f64.f32 -;CHECK: f2: +;CHECK-LABEL: f2: ;CHECK: extendsfdf2 entry: %tmp1 = fpext float %x to double ; <double> [#uses=1] @@ -22,9 +22,9 @@ entry: } define i32 @f3(float %x) { -;CHECK-VFP: f3: +;CHECK-VFP-LABEL: f3: ;CHECK-VFP: vcvt.s32.f32 -;CHECK: f3: +;CHECK-LABEL: f3: ;CHECK: fixsfsi entry: %tmp = fptosi float %x to i32 ; <i32> [#uses=1] @@ -32,9 +32,9 @@ entry: } define i32 @f4(float %x) { -;CHECK-VFP: f4: +;CHECK-VFP-LABEL: f4: ;CHECK-VFP: vcvt.u32.f32 -;CHECK: f4: +;CHECK-LABEL: f4: ;CHECK: fixunssfsi entry: %tmp = fptoui float %x to i32 ; <i32> [#uses=1] @@ -42,9 +42,9 @@ entry: } define i32 @f5(double %x) { -;CHECK-VFP: f5: +;CHECK-VFP-LABEL: f5: ;CHECK-VFP: vcvt.s32.f64 -;CHECK: f5: +;CHECK-LABEL: f5: ;CHECK: fixdfsi entry: %tmp = fptosi double %x to i32 ; <i32> [#uses=1] @@ -52,9 +52,9 @@ entry: } define i32 @f6(double %x) { -;CHECK-VFP: f6: +;CHECK-VFP-LABEL: f6: ;CHECK-VFP: vcvt.u32.f64 -;CHECK: f6: +;CHECK-LABEL: f6: ;CHECK: fixunsdfsi entry: %tmp = fptoui double %x to i32 ; <i32> [#uses=1] @@ -62,9 +62,9 @@ entry: } define float @f7(i32 %a) { -;CHECK-VFP: f7: +;CHECK-VFP-LABEL: f7: ;CHECK-VFP: vcvt.f32.s32 -;CHECK: f7: +;CHECK-LABEL: f7: ;CHECK: floatsisf entry: %tmp = sitofp i32 %a to float ; <float> [#uses=1] @@ -72,9 +72,9 @@ entry: } define double @f8(i32 %a) { -;CHECK-VFP: f8: +;CHECK-VFP-LABEL: f8: ;CHECK-VFP: vcvt.f64.s32 -;CHECK: f8: +;CHECK-LABEL: f8: ;CHECK: floatsidf entry: %tmp = sitofp i32 %a to double ; <double> [#uses=1] @@ -82,9 +82,9 @@ entry: } define float @f9(i32 %a) { -;CHECK-VFP: f9: +;CHECK-VFP-LABEL: f9: ;CHECK-VFP: vcvt.f32.u32 -;CHECK: f9: +;CHECK-LABEL: f9: ;CHECK: floatunsisf entry: %tmp = uitofp i32 %a to float ; <float> [#uses=1] @@ -92,9 +92,9 @@ entry: } define double @f10(i32 %a) { -;CHECK-VFP: f10: +;CHECK-VFP-LABEL: f10: ;CHECK-VFP: vcvt.f64.u32 -;CHECK: f10: +;CHECK-LABEL: f10: ;CHECK: floatunsidf entry: %tmp = uitofp i32 %a to double ; <double> [#uses=1] diff --git a/test/CodeGen/ARM/fpmem.ll b/test/CodeGen/ARM/fpmem.ll index 8faa57896a..8fbd1d8058 100644 --- a/test/CodeGen/ARM/fpmem.ll +++ b/test/CodeGen/ARM/fpmem.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s define float @f1(float %a) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: mov r0, #0 ret float 0.000000e+00 } define float @f2(float* %v, float %u) { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: vldr{{.*}}[ %tmp = load float* %v ; <float> [#uses=1] %tmp1 = fadd float %tmp, %u ; <float> [#uses=1] @@ -15,7 +15,7 @@ define float @f2(float* %v, float %u) { } define float @f2offset(float* %v, float %u) { -; CHECK: f2offset: +; CHECK-LABEL: f2offset: ; CHECK: vldr{{.*}}, #4] %addr = getelementptr float* %v, i32 1 %tmp = load float* %addr @@ -24,7 +24,7 @@ define float @f2offset(float* %v, float %u) { } define float @f2noffset(float* %v, float %u) { -; CHECK: f2noffset: +; CHECK-LABEL: f2noffset: ; CHECK: vldr{{.*}}, #-4] %addr = getelementptr float* %v, i32 -1 %tmp = load float* %addr @@ -33,7 +33,7 @@ define float @f2noffset(float* %v, float %u) { } define void @f3(float %a, float %b, float* %v) { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: vstr{{.*}}[ %tmp = fadd float %a, %b ; <float> [#uses=1] store float %tmp, float* %v diff --git a/test/CodeGen/ARM/fptoint.ll b/test/CodeGen/ARM/fptoint.ll index 299cb8f815..740868725e 100644 --- a/test/CodeGen/ARM/fptoint.ll +++ b/test/CodeGen/ARM/fptoint.ll @@ -44,6 +44,6 @@ define void @foo9(double %x) { store i16 %tmp, i16* null ret void } -; CHECK: foo9: +; CHECK-LABEL: foo9: ; CHECK: vmov r0, s0 diff --git a/test/CodeGen/ARM/fusedMAC.ll b/test/CodeGen/ARM/fusedMAC.ll index 303d165de0..e29f291dc2 100644 --- a/test/CodeGen/ARM/fusedMAC.ll +++ b/test/CodeGen/ARM/fusedMAC.ll @@ -2,7 +2,7 @@ ; Check generated fused MAC and MLS. define double @fusedMACTest1(double %d1, double %d2, double %d3) { -;CHECK: fusedMACTest1: +;CHECK-LABEL: fusedMACTest1: ;CHECK: vfma.f64 %1 = fmul double %d1, %d2 %2 = fadd double %1, %d3 @@ -10,7 +10,7 @@ define double @fusedMACTest1(double %d1, double %d2, double %d3) { } define float @fusedMACTest2(float %f1, float %f2, float %f3) { -;CHECK: fusedMACTest2: +;CHECK-LABEL: fusedMACTest2: ;CHECK: vfma.f32 %1 = fmul float %f1, %f2 %2 = fadd float %1, %f3 @@ -18,7 +18,7 @@ define float @fusedMACTest2(float %f1, float %f2, float %f3) { } define double @fusedMACTest3(double %d1, double %d2, double %d3) { -;CHECK: fusedMACTest3: +;CHECK-LABEL: fusedMACTest3: ;CHECK: vfms.f64 %1 = fmul double %d2, %d3 %2 = fsub double %d1, %1 @@ -26,7 +26,7 @@ define double @fusedMACTest3(double %d1, double %d2, double %d3) { } define float @fusedMACTest4(float %f1, float %f2, float %f3) { -;CHECK: fusedMACTest4: +;CHECK-LABEL: fusedMACTest4: ;CHECK: vfms.f32 %1 = fmul float %f2, %f3 %2 = fsub float %f1, %1 @@ -34,7 +34,7 @@ define float @fusedMACTest4(float %f1, float %f2, float %f3) { } define double @fusedMACTest5(double %d1, double %d2, double %d3) { -;CHECK: fusedMACTest5: +;CHECK-LABEL: fusedMACTest5: ;CHECK: vfnma.f64 %1 = fmul double %d1, %d2 %2 = fsub double -0.0, %1 @@ -43,7 +43,7 @@ define double @fusedMACTest5(double %d1, double %d2, double %d3) { } define float @fusedMACTest6(float %f1, float %f2, float %f3) { -;CHECK: fusedMACTest6: +;CHECK-LABEL: fusedMACTest6: ;CHECK: vfnma.f32 %1 = fmul float %f1, %f2 %2 = fsub float -0.0, %1 @@ -52,7 +52,7 @@ define float @fusedMACTest6(float %f1, float %f2, float %f3) { } define double @fusedMACTest7(double %d1, double %d2, double %d3) { -;CHECK: fusedMACTest7: +;CHECK-LABEL: fusedMACTest7: ;CHECK: vfnms.f64 %1 = fmul double %d1, %d2 %2 = fsub double %1, %d3 @@ -60,7 +60,7 @@ define double @fusedMACTest7(double %d1, double %d2, double %d3) { } define float @fusedMACTest8(float %f1, float %f2, float %f3) { -;CHECK: fusedMACTest8: +;CHECK-LABEL: fusedMACTest8: ;CHECK: vfnms.f32 %1 = fmul float %f1, %f2 %2 = fsub float %1, %f3 @@ -68,7 +68,7 @@ define float @fusedMACTest8(float %f1, float %f2, float %f3) { } define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) { -;CHECK: fusedMACTest9: +;CHECK-LABEL: fusedMACTest9: ;CHECK: vfma.f32 %mul = fmul <2 x float> %a, %b %add = fadd <2 x float> %mul, %a @@ -76,7 +76,7 @@ define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) { } define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) { -;CHECK: fusedMACTest10: +;CHECK-LABEL: fusedMACTest10: ;CHECK: vfms.f32 %mul = fmul <2 x float> %a, %b %sub = fsub <2 x float> %a, %mul @@ -84,7 +84,7 @@ define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) { } define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) { -;CHECK: fusedMACTest11: +;CHECK-LABEL: fusedMACTest11: ;CHECK: vfma.f32 %mul = fmul <4 x float> %a, %b %add = fadd <4 x float> %mul, %a @@ -92,7 +92,7 @@ define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) { } define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) { -;CHECK: fusedMACTest12: +;CHECK-LABEL: fusedMACTest12: ;CHECK: vfms.f32 %mul = fmul <4 x float> %a, %b %sub = fsub <4 x float> %a, %mul diff --git a/test/CodeGen/ARM/globals.ll b/test/CodeGen/ARM/globals.ll index eb71149d83..3101500f2c 100644 --- a/test/CodeGen/ARM/globals.ll +++ b/test/CodeGen/ARM/globals.ll @@ -57,7 +57,7 @@ define i32 @test1() { -; LinuxPIC: test1: +; LinuxPIC-LABEL: test1: ; LinuxPIC: ldr r0, .LCPI0_0 ; LinuxPIC: ldr r1, .LCPI0_1 diff --git a/test/CodeGen/ARM/hidden-vis-2.ll b/test/CodeGen/ARM/hidden-vis-2.ll index 8bb2c6e0c9..18d38d4007 100644 --- a/test/CodeGen/ARM/hidden-vis-2.ll +++ b/test/CodeGen/ARM/hidden-vis-2.ll @@ -4,7 +4,7 @@ define i32 @t() nounwind readonly { entry: -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: ldr ; CHECK-NEXT: ldr %0 = load i32* @x, align 4 ; <i32> [#uses=1] diff --git a/test/CodeGen/ARM/hidden-vis.ll b/test/CodeGen/ARM/hidden-vis.ll index 3544ae81a0..ce2ce2c1de 100644 --- a/test/CodeGen/ARM/hidden-vis.ll +++ b/test/CodeGen/ARM/hidden-vis.ll @@ -6,18 +6,18 @@ define weak hidden void @t1() nounwind { ; LINUX: .hidden t1 -; LINUX: t1: +; LINUX-LABEL: t1: ; DARWIN: .private_extern _t1 -; DARWIN: t1: +; DARWIN-LABEL: t1: ret void } define weak void @t2() nounwind { -; LINUX: t2: +; LINUX-LABEL: t2: ; LINUX: .hidden a -; DARWIN: t2: +; DARWIN-LABEL: t2: ; DARWIN: .private_extern _a ret void } diff --git a/test/CodeGen/ARM/ifcvt1.ll b/test/CodeGen/ARM/ifcvt1.ll index fd831442c1..5a55653239 100644 --- a/test/CodeGen/ARM/ifcvt1.ll +++ b/test/CodeGen/ARM/ifcvt1.ll @@ -2,8 +2,8 @@ ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT define i32 @t1(i32 %a, i32 %b) { -; A8: t1: -; SWIFT: t1: +; A8-LABEL: t1: +; SWIFT-LABEL: t1: %tmp2 = icmp eq i32 %a, 0 br i1 %tmp2, label %cond_false, label %cond_true diff --git a/test/CodeGen/ARM/ifcvt10.ll b/test/CodeGen/ARM/ifcvt10.ll index a5082d8365..26c72723b2 100644 --- a/test/CodeGen/ARM/ifcvt10.ll +++ b/test/CodeGen/ARM/ifcvt10.ll @@ -6,7 +6,7 @@ define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind { entry: -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: vpop {d8} ; CHECK-NOT: vpopne ; CHECK: pop {r7, pc} diff --git a/test/CodeGen/ARM/ifcvt11.ll b/test/CodeGen/ARM/ifcvt11.ll index 0f142eef7a..dba8a3f1a6 100644 --- a/test/CodeGen/ARM/ifcvt11.ll +++ b/test/CodeGen/ARM/ifcvt11.ll @@ -6,7 +6,7 @@ %struct.xyz_t = type { double, double, double } define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline { -; CHECK: effie: +; CHECK-LABEL: effie: entry: %0 = icmp sgt i32 %tsets, 0 br i1 %0, label %bb.nph, label %bb6 diff --git a/test/CodeGen/ARM/ifcvt12.ll b/test/CodeGen/ARM/ifcvt12.ll index 77bdca57e5..b61f4e1bb5 100644 --- a/test/CodeGen/ARM/ifcvt12.ll +++ b/test/CodeGen/ARM/ifcvt12.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s define i32 @f1(i32 %a, i32 %b, i32 %c) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: mlsne r0, r0, r1, r2 %tmp1 = icmp eq i32 %a, 0 br i1 %tmp1, label %cond_false, label %cond_true diff --git a/test/CodeGen/ARM/ifcvt2.ll b/test/CodeGen/ARM/ifcvt2.ll index 1bca10a7c6..e34edecf57 100644 --- a/test/CodeGen/ARM/ifcvt2.ll +++ b/test/CodeGen/ARM/ifcvt2.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: bxlt lr %tmp2 = icmp sgt i32 %c, 10 %tmp5 = icmp slt i32 %d, 4 @@ -19,7 +19,7 @@ UnifiedReturnBlock: } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) { -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: bxgt lr ; CHECK: cmp ; CHECK: addge diff --git a/test/CodeGen/ARM/ifcvt3.ll b/test/CodeGen/ARM/ifcvt3.ll index eef4de050b..fa7d61887d 100644 --- a/test/CodeGen/ARM/ifcvt3.ll +++ b/test/CodeGen/ARM/ifcvt3.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2 define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) { -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: cmp r2, #1 ; CHECK: cmpne r2, #7 switch i32 %c, label %cond_next [ diff --git a/test/CodeGen/ARM/ifcvt4.ll b/test/CodeGen/ARM/ifcvt4.ll index d247f14d91..53c789d184 100644 --- a/test/CodeGen/ARM/ifcvt4.ll +++ b/test/CodeGen/ARM/ifcvt4.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; Do not if-convert when branches go to the different loops. -; CHECK: t: +; CHECK-LABEL: t: ; CHECK-NOT: subgt ; CHECK-NOT: suble ; Don't use diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index 5081791bc2..31e3e00c46 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -12,10 +12,10 @@ entry: } define i32 @t1(i32 %a, i32 %b) { -; A8: t1: +; A8-LABEL: t1: ; A8: poplt {r7, pc} -; SWIFT: t1: +; SWIFT-LABEL: t1: ; SWIFT: pop {r7, pc} ; SWIFT: pop {r7, pc} entry: diff --git a/test/CodeGen/ARM/indirectbr-2.ll b/test/CodeGen/ARM/indirectbr-2.ll index 084f520a8e..0c41da6580 100644 --- a/test/CodeGen/ARM/indirectbr-2.ll +++ b/test/CodeGen/ARM/indirectbr-2.ll @@ -8,7 +8,7 @@ ; The indirect branch has the two destinations as successors. The lone PHI ; statement shouldn't be implicitly defined. -; CHECK: func: +; CHECK-LABEL: func: ; CHECK: Ltmp1: @ Block address taken ; CHECK-NOT: @ implicit-def: R0 ; CHECK: @ 4-byte Reload diff --git a/test/CodeGen/ARM/indirectbr.ll b/test/CodeGen/ARM/indirectbr.ll index 341c33f84f..6fed8c492f 100644 --- a/test/CodeGen/ARM/indirectbr.ll +++ b/test/CodeGen/ARM/indirectbr.ll @@ -6,9 +6,9 @@ @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] define internal i32 @foo(i32 %i) nounwind { -; ARM: foo: -; THUMB: foo: -; THUMB2: foo: +; ARM-LABEL: foo: +; THUMB-LABEL: foo: +; THUMB2-LABEL: foo: entry: %0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2] %1 = icmp eq i8* %0, null ; <i1> [#uses=1] diff --git a/test/CodeGen/ARM/inlineasm-64bit.ll b/test/CodeGen/ARM/inlineasm-64bit.ll index ade0154dd9..b23db10632 100644 --- a/test/CodeGen/ARM/inlineasm-64bit.ll +++ b/test/CodeGen/ARM/inlineasm-64bit.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s ; check if regs are passing correctly define void @i64_write(i64* %p, i64 %val) nounwind { -; CHECK: i64_write: +; CHECK-LABEL: i64_write: ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}] ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} %1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind @@ -12,7 +12,7 @@ define void @i64_write(i64* %p, i64 %val) nounwind { ; check if register allocation can reuse the registers define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind { entry: -; CHECK: multi_writes: +; CHECK-LABEL: multi_writes: ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] ; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}] @@ -44,7 +44,7 @@ entry: ; check if callee-saved registers used by inline asm are saved/restored define void @foo(i64* %p, i64 %i) nounwind { -; CHECK:foo: +; CHECK-LABEL:foo: ; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}] ; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} @@ -55,20 +55,20 @@ define void @foo(i64* %p, i64 %i) nounwind { ; return *p; define i64 @ldrd_test(i64* %p) nounwind { -; CHECK: ldrd_test: +; CHECK-LABEL: ldrd_test: %1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind ret i64 %1 } define i64 @QR_test(i64* %p) nounwind { -; CHECK: QR_test: +; CHECK-LABEL: QR_test: ; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} %1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind ret i64 %1 } define i64 @defuse_test(i64 %p) nounwind { -; CHECK: defuse_test: +; CHECK-LABEL: defuse_test: ; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1 %1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind ret i64 %1 @@ -76,7 +76,7 @@ define i64 @defuse_test(i64 %p) nounwind { ; *p = (hi << 32) | lo; define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind { -; CHECK: strd_test: +; CHECK-LABEL: strd_test: ; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} %1 = zext i32 %hi to i64 %2 = shl nuw i64 %1, 32 diff --git a/test/CodeGen/ARM/inlineasm4.ll b/test/CodeGen/ARM/inlineasm4.ll index 9ed4b997a6..4a1bccaf61 100644 --- a/test/CodeGen/ARM/inlineasm4.ll +++ b/test/CodeGen/ARM/inlineasm4.ll @@ -4,7 +4,7 @@ define double @f(double %x) { entry: %0 = tail call double asm "mov ${0:R}, #4\0A", "=&r"() ret double %0 -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: mov r1, #4 } @@ -12,6 +12,6 @@ define double @g(double %x) { entry: %0 = tail call double asm "mov ${0:Q}, #4\0A", "=&r"() ret double %0 -; CHECK: g: +; CHECK-LABEL: g: ; CHECK: mov r0, #4 } diff --git a/test/CodeGen/ARM/ldm.ll b/test/CodeGen/ARM/ldm.ll index db78fd06ab..d5b805c721 100644 --- a/test/CodeGen/ARM/ldm.ll +++ b/test/CodeGen/ARM/ldm.ll @@ -4,9 +4,9 @@ @X = external global [0 x i32] ; <[0 x i32]*> [#uses=5] define i32 @t1() { -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: pop -; V4T: t1: +; V4T-LABEL: t1: ; V4T: pop %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1] @@ -15,9 +15,9 @@ define i32 @t1() { } define i32 @t2() { -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: pop -; V4T: t2: +; V4T-LABEL: t2: ; V4T: pop %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1] %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1] @@ -27,10 +27,10 @@ define i32 @t2() { } define i32 @t3() { -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: ldmib ; CHECK: pop -; V4T: t3: +; V4T-LABEL: t3: ; V4T: ldmib ; V4T: pop ; V4T-NEXT: bx lr diff --git a/test/CodeGen/ARM/ldr.ll b/test/CodeGen/ARM/ldr.ll index 011e61caea..e4c695b87b 100644 --- a/test/CodeGen/ARM/ldr.ll +++ b/test/CodeGen/ARM/ldr.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i32 @f1(i32* %v) { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: ldr r0 entry: %tmp = load i32* %v @@ -9,7 +9,7 @@ entry: } define i32 @f2(i32* %v) { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: ldr r0 entry: %tmp2 = getelementptr i32* %v, i32 1023 @@ -18,7 +18,7 @@ entry: } define i32 @f3(i32* %v) { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: mov ; CHECK: ldr r0 entry: @@ -28,7 +28,7 @@ entry: } define i32 @f4(i32 %base) { -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK-NOT: mvn ; CHECK: ldr r0 entry: @@ -39,7 +39,7 @@ entry: } define i32 @f5(i32 %base, i32 %offset) { -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK: ldr r0 entry: %tmp1 = add i32 %base, %offset @@ -49,7 +49,7 @@ entry: } define i32 @f6(i32 %base, i32 %offset) { -; CHECK: f6: +; CHECK-LABEL: f6: ; CHECK: ldr r0{{.*}}lsl{{.*}} entry: %tmp1 = shl i32 %offset, 2 @@ -60,7 +60,7 @@ entry: } define i32 @f7(i32 %base, i32 %offset) { -; CHECK: f7: +; CHECK-LABEL: f7: ; CHECK: ldr r0{{.*}}lsr{{.*}} entry: %tmp1 = lshr i32 %offset, 2 diff --git a/test/CodeGen/ARM/ldrd.ll b/test/CodeGen/ARM/ldrd.ll index 4abf6e6528..864d18a88a 100644 --- a/test/CodeGen/ARM/ldrd.ll +++ b/test/CodeGen/ARM/ldrd.ll @@ -13,10 +13,10 @@ define i64 @t(i64 %a) nounwind readonly { entry: -; A8: t: +; A8-LABEL: t: ; A8: ldrd r2, r3, [r2] -; M3: t: +; M3-LABEL: t: ; M3-NOT: ldrd %0 = load i64** @b, align 4 diff --git a/test/CodeGen/ARM/ldst-f32-2-i32.ll b/test/CodeGen/ARM/ldst-f32-2-i32.ll index 1c69e15bbb..61c459c743 100644 --- a/test/CodeGen/ARM/ldst-f32-2-i32.ll +++ b/test/CodeGen/ARM/ldst-f32-2-i32.ll @@ -3,7 +3,7 @@ ; rdar://8944252 define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind { -; CHECK: t: +; CHECK-LABEL: t: entry: %src6 = bitcast float* %src to i8* %0 = icmp eq i32 %width, 0 diff --git a/test/CodeGen/ARM/ldstrexd.ll b/test/CodeGen/ARM/ldstrexd.ll index 0c0911a86e..bb60e1e67e 100644 --- a/test/CodeGen/ARM/ldstrexd.ll +++ b/test/CodeGen/ARM/ldstrexd.ll @@ -3,7 +3,7 @@ %0 = type { i32, i32 } -; CHECK: f0: +; CHECK-LABEL: f0: ; CHECK: ldrexd define i64 @f0(i8* %p) nounwind readonly { entry: @@ -17,7 +17,7 @@ entry: ret i64 %4 } -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: strexd define i32 @f1(i8* %ptr, i64 %val) nounwind { entry: diff --git a/test/CodeGen/ARM/load-address-masked.ll b/test/CodeGen/ARM/load-address-masked.ll index 43c98e45d4..65cc31104b 100644 --- a/test/CodeGen/ARM/load-address-masked.ll +++ b/test/CodeGen/ARM/load-address-masked.ll @@ -10,5 +10,5 @@ entry: ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255) } -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: ldrb r0, .LCPI0_0 diff --git a/test/CodeGen/ARM/load_i1_select.ll b/test/CodeGen/ARM/load_i1_select.ll index bdd4081649..7a208ea417 100644 --- a/test/CodeGen/ARM/load_i1_select.ll +++ b/test/CodeGen/ARM/load_i1_select.ll @@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios0.0.0" ; Codegen should only compare one bit of the loaded value. ; rdar://10887484 -; CHECK: foo: +; CHECK-LABEL: foo: ; CHECK: ldrb r[[R0:[0-9]+]], [r0] ; CHECK: tst.w r[[R0]], #1 define void @foo(i8* %call, double* %p) nounwind { diff --git a/test/CodeGen/ARM/long.ll b/test/CodeGen/ARM/long.ll index 0f1c7be6a3..7fffc81797 100644 --- a/test/CodeGen/ARM/long.ll +++ b/test/CodeGen/ARM/long.ll @@ -1,33 +1,33 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i64 @f1() { -; CHECK: f1: +; CHECK-LABEL: f1: entry: ret i64 0 } define i64 @f2() { -; CHECK: f2: +; CHECK-LABEL: f2: entry: ret i64 1 } define i64 @f3() { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: mvn r0, #-2147483648 entry: ret i64 2147483647 } define i64 @f4() { -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: mov r0, #-2147483648 entry: ret i64 2147483648 } define i64 @f5() { -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK: mvn r0, #0 ; CHECK: mvn r1, #-2147483648 entry: @@ -35,7 +35,7 @@ entry: } define i64 @f6(i64 %x, i64 %y) { -; CHECK: f6: +; CHECK-LABEL: f6: ; CHECK: adds ; CHECK: adc entry: @@ -44,7 +44,7 @@ entry: } define void @f7() { -; CHECK: f7: +; CHECK-LABEL: f7: entry: %tmp = call i64 @f8( ) ; <i64> [#uses=0] ret void @@ -53,7 +53,7 @@ entry: declare i64 @f8() define i64 @f9(i64 %a, i64 %b) { -; CHECK: f9: +; CHECK-LABEL: f9: ; CHECK: subs r ; CHECK: sbc entry: @@ -62,7 +62,7 @@ entry: } define i64 @f(i32 %a, i32 %b) { -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: smull entry: %tmp = sext i32 %a to i64 ; <i64> [#uses=1] @@ -72,7 +72,7 @@ entry: } define i64 @g(i32 %a, i32 %b) { -; CHECK: g: +; CHECK-LABEL: g: ; CHECK: umull entry: %tmp = zext i32 %a to i64 ; <i64> [#uses=1] @@ -82,7 +82,7 @@ entry: } define i64 @f10() { -; CHECK: f10: +; CHECK-LABEL: f10: entry: %a = alloca i64, align 8 ; <i64*> [#uses=1] %retval = load i64* %a ; <i64> [#uses=1] diff --git a/test/CodeGen/ARM/longMAC.ll b/test/CodeGen/ARM/longMAC.ll index e4a00e9ac3..2cf91c32bc 100644 --- a/test/CodeGen/ARM/longMAC.ll +++ b/test/CodeGen/ARM/longMAC.ll @@ -2,7 +2,7 @@ ; Check generated signed and unsigned multiply accumulate long. define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) { -;CHECK: MACLongTest1: +;CHECK-LABEL: MACLongTest1: ;CHECK: umlal %conv = zext i32 %a to i64 %conv1 = zext i32 %b to i64 @@ -12,7 +12,7 @@ define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) { } define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) { -;CHECK: MACLongTest2: +;CHECK-LABEL: MACLongTest2: ;CHECK: smlal %conv = sext i32 %a to i64 %conv1 = sext i32 %b to i64 @@ -22,7 +22,7 @@ define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) { } define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) { -;CHECK: MACLongTest3: +;CHECK-LABEL: MACLongTest3: ;CHECK: umlal %conv = zext i32 %b to i64 %conv1 = zext i32 %a to i64 @@ -33,7 +33,7 @@ define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) { } define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) { -;CHECK: MACLongTest4: +;CHECK-LABEL: MACLongTest4: ;CHECK: smlal %conv = sext i32 %b to i64 %conv1 = sext i32 %a to i64 diff --git a/test/CodeGen/ARM/lsr-icmp-imm.ll b/test/CodeGen/ARM/lsr-icmp-imm.ll index 248c4bd1be..103642b8b7 100644 --- a/test/CodeGen/ARM/lsr-icmp-imm.ll +++ b/test/CodeGen/ARM/lsr-icmp-imm.ll @@ -4,7 +4,7 @@ ; LSR should compare against the post-incremented induction variable. ; In this case, the immediate value is -2 which requires a cmn instruction. ; -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: %for.body ; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2 ; CHECK: cmn{{.*}}[[IV]], #2 diff --git a/test/CodeGen/ARM/machine-cse-cmp.ll b/test/CodeGen/ARM/machine-cse-cmp.ll index 03abd762a2..7e4b309fd9 100644 --- a/test/CodeGen/ARM/machine-cse-cmp.ll +++ b/test/CodeGen/ARM/machine-cse-cmp.ll @@ -6,7 +6,7 @@ define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) { entry: -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: cmp ; CHECK: moveq ; CHECK-NOT: cmp @@ -25,7 +25,7 @@ entry: ; rdar://10660865 define void @f2() nounwind ssp { entry: -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: cmp ; CHECK: poplt ; CHECK-NOT: cmp @@ -49,7 +49,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind ; rdar://12462006 define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind { entry: -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK-NOT: sub ; CHECK: cmp ; CHECK: blt diff --git a/test/CodeGen/ARM/machine-licm.ll b/test/CodeGen/ARM/machine-licm.ll index 8656c5bbd7..87aaacfb55 100644 --- a/test/CodeGen/ARM/machine-licm.ll +++ b/test/CodeGen/ARM/machine-licm.ll @@ -12,7 +12,7 @@ define void @t(i32* nocapture %vals, i32 %c) nounwind { entry: -; ARM: t: +; ARM-LABEL: t: ; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0 ; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool. ; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy @@ -23,14 +23,14 @@ entry: ; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]] ; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}] -; MOVT: t: +; MOVT-LABEL: t: ; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8)) ; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8)) ; MOVT: LPC0_0: ; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]] ; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}] -; THUMB: t: +; THUMB-LABEL: t: %0 = icmp eq i32 %c, 0 ; <i1> [#uses=1] br i1 %0, label %return, label %bb.nph diff --git a/test/CodeGen/ARM/memcpy-inline.ll b/test/CodeGen/ARM/memcpy-inline.ll index d846e5cb26..946c63ed40 100644 --- a/test/CodeGen/ARM/memcpy-inline.ll +++ b/test/CodeGen/ARM/memcpy-inline.ll @@ -15,7 +15,7 @@ define i32 @t0() { entry: -; CHECK: t0: +; CHECK-LABEL: t0: ; CHECK: vldr [[REG1:d[0-9]+]], ; CHECK: vstr [[REG1]], call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false) @@ -24,7 +24,7 @@ entry: define void @t1(i8* nocapture %C) nounwind { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] ; CHECK: adds r0, #15 @@ -37,7 +37,7 @@ entry: define void @t2(i8* nocapture %C) nounwind { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32] ; CHECK: str [[REG2]], [r0, #32] ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] @@ -52,7 +52,7 @@ entry: define void @t3(i8* nocapture %C) nounwind { entry: -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] ; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0] ; CHECK: adds r0, #16 @@ -65,7 +65,7 @@ entry: define void @t4(i8* nocapture %C) nounwind { entry: -; CHECK: t4: +; CHECK-LABEL: t4: ; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1] ; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0] tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false) @@ -74,7 +74,7 @@ entry: define void @t5(i8* nocapture %C) nounwind { entry: -; CHECK: t5: +; CHECK-LABEL: t5: ; CHECK: movs [[REG5:r[0-9]+]], #0 ; CHECK: strb [[REG5]], [r0, #6] ; CHECK: movw [[REG6:r[0-9]+]], #21587 @@ -87,7 +87,7 @@ entry: define void @t6() nounwind { entry: -; CHECK: t6: +; CHECK-LABEL: t6: ; CHECK: vld1.8 {[[REG8:d[0-9]+]]}, [r0] ; CHECK: vstr [[REG8]], [r1] ; CHECK: adds r1, #6 diff --git a/test/CodeGen/ARM/memset-inline.ll b/test/CodeGen/ARM/memset-inline.ll index ee8c364338..4e86d05b0a 100644 --- a/test/CodeGen/ARM/memset-inline.ll +++ b/test/CodeGen/ARM/memset-inline.ll @@ -2,7 +2,7 @@ define void @t1(i8* nocapture %c) nounwind optsize { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: movs r1, #0 ; CHECK: str r1, [r0] ; CHECK: str r1, [r0, #4] @@ -13,7 +13,7 @@ entry: define void @t2() nounwind ssp { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: add.w r1, r0, #10 ; CHECK: vmov.i32 {{q[0-9]+}}, #0x0 ; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1] diff --git a/test/CodeGen/ARM/mls.ll b/test/CodeGen/ARM/mls.ll index 066bf98de6..8f0d3a89a3 100644 --- a/test/CodeGen/ARM/mls.ll +++ b/test/CodeGen/ARM/mls.ll @@ -14,15 +14,15 @@ define i32 @f2(i32 %a, i32 %b, i32 %c) { ret i32 %tmp2 } -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: mls r0, r0, r1, r2 -; NO_MULOPS: f1: +; NO_MULOPS-LABEL: f1: ; NO_MULOPS: mul r0, r0, r1 ; NO_MULOPS-NEXT: sub r0, r2, r0 -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: mul r0, r0, r1 ; CHECK-NEXT: sub r0, r0, r2 -; NO_MULOPS: f2: +; NO_MULOPS-LABEL: f2: ; NO_MULOPS: mul r0, r0, r1 ; NO_MULOPS-NEXT: sub r0, r0, r2 diff --git a/test/CodeGen/ARM/movt.ll b/test/CodeGen/ARM/movt.ll index e82aca0e9c..25c1bfe320 100644 --- a/test/CodeGen/ARM/movt.ll +++ b/test/CodeGen/ARM/movt.ll @@ -2,7 +2,7 @@ ; rdar://7317664 define i32 @t(i32 %X) nounwind { -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: movt r0, #65535 entry: %0 = or i32 %X, -65536 @@ -10,7 +10,7 @@ entry: } define i32 @t2(i32 %X) nounwind { -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: movt r0, #65534 entry: %0 = or i32 %X, -131072 diff --git a/test/CodeGen/ARM/mul_const.ll b/test/CodeGen/ARM/mul_const.ll index c50a233546..482d8f2888 100644 --- a/test/CodeGen/ARM/mul_const.ll +++ b/test/CodeGen/ARM/mul_const.ll @@ -2,7 +2,7 @@ define i32 @t9(i32 %v) nounwind readnone { entry: -; CHECK: t9: +; CHECK-LABEL: t9: ; CHECK: add r0, r0, r0, lsl #3 %0 = mul i32 %v, 9 ret i32 %0 @@ -10,7 +10,7 @@ entry: define i32 @t7(i32 %v) nounwind readnone { entry: -; CHECK: t7: +; CHECK-LABEL: t7: ; CHECK: rsb r0, r0, r0, lsl #3 %0 = mul i32 %v, 7 ret i32 %0 @@ -18,7 +18,7 @@ entry: define i32 @t5(i32 %v) nounwind readnone { entry: -; CHECK: t5: +; CHECK-LABEL: t5: ; CHECK: add r0, r0, r0, lsl #2 %0 = mul i32 %v, 5 ret i32 %0 @@ -26,7 +26,7 @@ entry: define i32 @t3(i32 %v) nounwind readnone { entry: -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: add r0, r0, r0, lsl #1 %0 = mul i32 %v, 3 ret i32 %0 @@ -34,7 +34,7 @@ entry: define i32 @t12288(i32 %v) nounwind readnone { entry: -; CHECK: t12288: +; CHECK-LABEL: t12288: ; CHECK: add r0, r0, r0, lsl #1 ; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, 12288 @@ -43,7 +43,7 @@ entry: define i32 @tn9(i32 %v) nounwind readnone { entry: -; CHECK: tn9: +; CHECK-LABEL: tn9: ; CHECK: add r0, r0, r0, lsl #3 ; CHECK: rsb r0, r0, #0 %0 = mul i32 %v, -9 @@ -52,7 +52,7 @@ entry: define i32 @tn7(i32 %v) nounwind readnone { entry: -; CHECK: tn7: +; CHECK-LABEL: tn7: ; CHECK: sub r0, r0, r0, lsl #3 %0 = mul i32 %v, -7 ret i32 %0 @@ -60,7 +60,7 @@ entry: define i32 @tn5(i32 %v) nounwind readnone { entry: -; CHECK: tn5: +; CHECK-LABEL: tn5: ; CHECK: add r0, r0, r0, lsl #2 ; CHECK: rsb r0, r0, #0 %0 = mul i32 %v, -5 @@ -69,7 +69,7 @@ entry: define i32 @tn3(i32 %v) nounwind readnone { entry: -; CHECK: tn3: +; CHECK-LABEL: tn3: ; CHECK: sub r0, r0, r0, lsl #2 %0 = mul i32 %v, -3 ret i32 %0 @@ -77,7 +77,7 @@ entry: define i32 @tn12288(i32 %v) nounwind readnone { entry: -; CHECK: tn12288: +; CHECK-LABEL: tn12288: ; CHECK: sub r0, r0, r0, lsl #2 ; CHECK: lsl{{.*}}#12 %0 = mul i32 %v, -12288 diff --git a/test/CodeGen/ARM/mulhi.ll b/test/CodeGen/ARM/mulhi.ll index 932004c5dd..63705c5027 100644 --- a/test/CodeGen/ARM/mulhi.ll +++ b/test/CodeGen/ARM/mulhi.ll @@ -3,13 +3,13 @@ ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3 define i32 @smulhi(i32 %x, i32 %y) nounwind { -; V6: smulhi: +; V6-LABEL: smulhi: ; V6: smmul -; V4: smulhi: +; V4-LABEL: smulhi: ; V4: smull -; M3: smulhi: +; M3-LABEL: smulhi: ; M3: smull %tmp = sext i32 %x to i64 ; <i64> [#uses=1] %tmp1 = sext i32 %y to i64 ; <i64> [#uses=1] @@ -20,13 +20,13 @@ define i32 @smulhi(i32 %x, i32 %y) nounwind { } define i32 @umulhi(i32 %x, i32 %y) nounwind { -; V6: umulhi: +; V6-LABEL: umulhi: ; V6: umull -; V4: umulhi: +; V4-LABEL: umulhi: ; V4: umull -; M3: umulhi: +; M3-LABEL: umulhi: ; M3: umull %tmp = zext i32 %x to i64 ; <i64> [#uses=1] %tmp1 = zext i32 %y to i64 ; <i64> [#uses=1] @@ -38,13 +38,13 @@ define i32 @umulhi(i32 %x, i32 %y) nounwind { ; rdar://r10152911 define i32 @t3(i32 %a) nounwind { -; V6: t3: +; V6-LABEL: t3: ; V6: smmla -; V4: t3: +; V4-LABEL: t3: ; V4: smull -; M3: t3: +; M3-LABEL: t3: ; M3-NOT: smmla ; M3: smull entry: diff --git a/test/CodeGen/ARM/neon-spfp.ll b/test/CodeGen/ARM/neon-spfp.ll index c00f0d17c9..5385668464 100644 --- a/test/CodeGen/ARM/neon-spfp.ll +++ b/test/CodeGen/ARM/neon-spfp.ll @@ -21,21 +21,21 @@ @.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1 -; CHECK-LINUXA5: main: -; CHECK-LINUXA8: main: -; CHECK-LINUXA9: main: -; CHECK-LINUXA15: main: -; CHECK-LINUXSWIFT: main: -; CHECK-UNSAFEA5: main: -; CHECK-UNSAFEA8: main: -; CHECK-UNSAFEA9: main: -; CHECK-UNSAFEA15: main: -; CHECK-UNSAFESWIFT: main: -; CHECK-DARWINA5: main: -; CHECK-DARWINA8: main: -; CHECK-DARWINA9: main: -; CHECK-DARWINA15: main: -; CHECK-DARWINSWIFT: main: +; CHECK-LINUXA5-LABEL: main: +; CHECK-LINUXA8-LABEL: main: +; CHECK-LINUXA9-LABEL: main: +; CHECK-LINUXA15-LABEL: main: +; CHECK-LINUXSWIFT-LABEL: main: +; CHECK-UNSAFEA5-LABEL: main: +; CHECK-UNSAFEA8-LABEL: main: +; CHECK-UNSAFEA9-LABEL: main: +; CHECK-UNSAFEA15-LABEL: main: +; CHECK-UNSAFESWIFT-LABEL: main: +; CHECK-DARWINA5-LABEL: main: +; CHECK-DARWINA8-LABEL: main: +; CHECK-DARWINA9-LABEL: main: +; CHECK-DARWINA15-LABEL: main: +; CHECK-DARWINSWIFT-LABEL: main: define i32 @main() { entry: br label %for.body diff --git a/test/CodeGen/ARM/neon_minmax.ll b/test/CodeGen/ARM/neon_minmax.ll index 0a7c8b2b6a..2e45919e77 100644 --- a/test/CodeGen/ARM/neon_minmax.ll +++ b/test/CodeGen/ARM/neon_minmax.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s define float @fmin_ole(float %x) nounwind { -;CHECK: fmin_ole: +;CHECK-LABEL: fmin_ole: ;CHECK: vmin.f32 %cond = fcmp ole float 1.0, %x %min1 = select i1 %cond, float 1.0, float %x @@ -9,7 +9,7 @@ define float @fmin_ole(float %x) nounwind { } define float @fmin_ole_zero(float %x) nounwind { -;CHECK: fmin_ole_zero: +;CHECK-LABEL: fmin_ole_zero: ;CHECK-NOT: vmin.f32 %cond = fcmp ole float 0.0, %x %min1 = select i1 %cond, float 0.0, float %x @@ -17,7 +17,7 @@ define float @fmin_ole_zero(float %x) nounwind { } define float @fmin_ult(float %x) nounwind { -;CHECK: fmin_ult: +;CHECK-LABEL: fmin_ult: ;CHECK: vmin.f32 %cond = fcmp ult float %x, 1.0 %min1 = select i1 %cond, float %x, float 1.0 @@ -25,7 +25,7 @@ define float @fmin_ult(float %x) nounwind { } define float @fmax_ogt(float %x) nounwind { -;CHECK: fmax_ogt: +;CHECK-LABEL: fmax_ogt: ;CHECK: vmax.f32 %cond = fcmp ogt float 1.0, %x %max1 = select i1 %cond, float 1.0, float %x @@ -33,7 +33,7 @@ define float @fmax_ogt(float %x) nounwind { } define float @fmax_uge(float %x) nounwind { -;CHECK: fmax_uge: +;CHECK-LABEL: fmax_uge: ;CHECK: vmax.f32 %cond = fcmp uge float %x, 1.0 %max1 = select i1 %cond, float %x, float 1.0 @@ -41,7 +41,7 @@ define float @fmax_uge(float %x) nounwind { } define float @fmax_uge_zero(float %x) nounwind { -;CHECK: fmax_uge_zero: +;CHECK-LABEL: fmax_uge_zero: ;CHECK-NOT: vmax.f32 %cond = fcmp uge float %x, 0.0 %max1 = select i1 %cond, float %x, float 0.0 @@ -49,7 +49,7 @@ define float @fmax_uge_zero(float %x) nounwind { } define float @fmax_olt_reverse(float %x) nounwind { -;CHECK: fmax_olt_reverse: +;CHECK-LABEL: fmax_olt_reverse: ;CHECK: vmax.f32 %cond = fcmp olt float %x, 1.0 %max1 = select i1 %cond, float 1.0, float %x @@ -57,7 +57,7 @@ define float @fmax_olt_reverse(float %x) nounwind { } define float @fmax_ule_reverse(float %x) nounwind { -;CHECK: fmax_ule_reverse: +;CHECK-LABEL: fmax_ule_reverse: ;CHECK: vmax.f32 %cond = fcmp ult float 1.0, %x %max1 = select i1 %cond, float %x, float 1.0 @@ -65,7 +65,7 @@ define float @fmax_ule_reverse(float %x) nounwind { } define float @fmin_oge_reverse(float %x) nounwind { -;CHECK: fmin_oge_reverse: +;CHECK-LABEL: fmin_oge_reverse: ;CHECK: vmin.f32 %cond = fcmp oge float %x, 1.0 %min1 = select i1 %cond, float 1.0, float %x @@ -73,7 +73,7 @@ define float @fmin_oge_reverse(float %x) nounwind { } define float @fmin_ugt_reverse(float %x) nounwind { -;CHECK: fmin_ugt_reverse: +;CHECK-LABEL: fmin_ugt_reverse: ;CHECK: vmin.f32 %cond = fcmp ugt float 1.0, %x %min1 = select i1 %cond, float %x, float 1.0 diff --git a/test/CodeGen/ARM/peephole-bitcast.ll b/test/CodeGen/ARM/peephole-bitcast.ll index e72d51f06d..3c6a187d99 100644 --- a/test/CodeGen/ARM/peephole-bitcast.ll +++ b/test/CodeGen/ARM/peephole-bitcast.ll @@ -10,7 +10,7 @@ define void @t(float %x) nounwind ssp { entry: -; CHECK: t: +; CHECK-LABEL: t: ; CHECK-NOT: vmov ; CHECK: bl %0 = bitcast float %x to i32 diff --git a/test/CodeGen/ARM/popcnt.ll b/test/CodeGen/ARM/popcnt.ll index 0b9c9467c2..bdf793d91b 100644 --- a/test/CodeGen/ARM/popcnt.ll +++ b/test/CodeGen/ARM/popcnt.ll @@ -2,7 +2,7 @@ ; Implement ctpop with vcnt define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { -;CHECK: vcnt8: +;CHECK-LABEL: vcnt8: ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1) @@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { } define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { -;CHECK: vcntQ8: +;CHECK-LABEL: vcntQ8: ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1) @@ -18,7 +18,7 @@ define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { } define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind { -; CHECK: vcnt16: +; CHECK-LABEL: vcnt16: ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} @@ -30,7 +30,7 @@ define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind { } define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind { -; CHECK: vcntQ16: +; CHECK-LABEL: vcntQ16: ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} @@ -42,7 +42,7 @@ define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind { } define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind { -; CHECK: vcnt32: +; CHECK-LABEL: vcnt32: ; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}} ; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}} @@ -57,7 +57,7 @@ define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind { } define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind { -; CHECK: vcntQ32: +; CHECK-LABEL: vcntQ32: ; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}} ; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} @@ -79,7 +79,7 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) nounwind readnone declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { -;CHECK: vclz8: +;CHECK-LABEL: vclz8: ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0) @@ -87,7 +87,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { } define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { -;CHECK: vclz16: +;CHECK-LABEL: vclz16: ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0) @@ -95,7 +95,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { } define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { -;CHECK: vclz32: +;CHECK-LABEL: vclz32: ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0) @@ -103,7 +103,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { } define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { -;CHECK: vclzQ8: +;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0) @@ -111,7 +111,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { } define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { -;CHECK: vclzQ16: +;CHECK-LABEL: vclzQ16: ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0) @@ -119,7 +119,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { } define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { -;CHECK: vclzQ32: +;CHECK-LABEL: vclzQ32: ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0) @@ -135,7 +135,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { -;CHECK: vclss8: +;CHECK-LABEL: vclss8: ;CHECK: vcls.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) @@ -143,7 +143,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { } define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { -;CHECK: vclss16: +;CHECK-LABEL: vclss16: ;CHECK: vcls.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) @@ -151,7 +151,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { } define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { -;CHECK: vclss32: +;CHECK-LABEL: vclss32: ;CHECK: vcls.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) @@ -159,7 +159,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { } define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { -;CHECK: vclsQs8: +;CHECK-LABEL: vclsQs8: ;CHECK: vcls.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) @@ -167,7 +167,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { -;CHECK: vclsQs16: +;CHECK-LABEL: vclsQs16: ;CHECK: vcls.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) @@ -175,7 +175,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { -;CHECK: vclsQs32: +;CHECK-LABEL: vclsQs32: ;CHECK: vcls.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) diff --git a/test/CodeGen/ARM/prefetch.ll b/test/CodeGen/ARM/prefetch.ll index 9c8ff2b409..5badb31148 100644 --- a/test/CodeGen/ARM/prefetch.ll +++ b/test/CodeGen/ARM/prefetch.ll @@ -6,15 +6,15 @@ define void @t1(i8* %ptr) nounwind { entry: -; ARM: t1: +; ARM-LABEL: t1: ; ARM-NOT: pldw [r0] ; ARM: pld [r0] -; ARM-MP: t1: +; ARM-MP-LABEL: t1: ; ARM-MP: pldw [r0] ; ARM-MP: pld [r0] -; THUMB2: t1: +; THUMB2-LABEL: t1: ; THUMB2-NOT: pldw [r0] ; THUMB2: pld [r0] tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 ) @@ -24,10 +24,10 @@ entry: define void @t2(i8* %ptr) nounwind { entry: -; ARM: t2: +; ARM-LABEL: t2: ; ARM: pld [r0, #1023] -; THUMB2: t2: +; THUMB2-LABEL: t2: ; THUMB2: pld [r0, #1023] %tmp = getelementptr i8* %ptr, i32 1023 tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 ) @@ -36,10 +36,10 @@ entry: define void @t3(i32 %base, i32 %offset) nounwind { entry: -; ARM: t3: +; ARM-LABEL: t3: ; ARM: pld [r0, r1, lsr #2] -; THUMB2: t3: +; THUMB2-LABEL: t3: ; THUMB2: lsrs r1, r1, #2 ; THUMB2: pld [r0, r1] %tmp1 = lshr i32 %offset, 2 @@ -51,10 +51,10 @@ entry: define void @t4(i32 %base, i32 %offset) nounwind { entry: -; ARM: t4: +; ARM-LABEL: t4: ; ARM: pld [r0, r1, lsl #2] -; THUMB2: t4: +; THUMB2-LABEL: t4: ; THUMB2: pld [r0, r1, lsl #2] %tmp1 = shl i32 %offset, 2 %tmp2 = add i32 %base, %tmp1 @@ -67,10 +67,10 @@ declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind define void @t5(i8* %ptr) nounwind { entry: -; ARM: t5: +; ARM-LABEL: t5: ; ARM: pli [r0] -; THUMB2: t5: +; THUMB2-LABEL: t5: ; THUMB2: pli [r0] tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 ) ret void diff --git a/test/CodeGen/ARM/private.ll b/test/CodeGen/ARM/private.ll index 94578d82fd..e48c292db4 100644 --- a/test/CodeGen/ARM/private.ll +++ b/test/CodeGen/ARM/private.ll @@ -2,7 +2,7 @@ ; ; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s ; CHECK: .Lfoo: -; CHECK: bar: +; CHECK-LABEL: bar: ; CHECK: bl .Lfoo ; CHECK: .long .Lbaz ; CHECK: .Lbaz: diff --git a/test/CodeGen/ARM/reg_sequence.ll b/test/CodeGen/ARM/reg_sequence.ll index fd2083cf9f..3fe2bb8e38 100644 --- a/test/CodeGen/ARM/reg_sequence.ll +++ b/test/CodeGen/ARM/reg_sequence.ll @@ -11,7 +11,7 @@ define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind { entry: -; CHECK: t1: +; CHECK-LABEL: t1: ; CHECK: vld1.16 ; CHECK-NOT: vmov d ; CHECK: vmovl.s16 @@ -44,7 +44,7 @@ entry: define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind { entry: -; CHECK: t2: +; CHECK-LABEL: t2: ; CHECK: vld1.16 ; CHECK-NOT: vmov ; CHECK: vmul.i16 @@ -73,7 +73,7 @@ entry: } define <8 x i8> @t3(i8* %A, i8* %B) nounwind { -; CHECK: t3: +; CHECK-LABEL: t3: ; CHECK: vld3.8 ; CHECK: vmul.i8 ; CHECK: vmov r @@ -92,7 +92,7 @@ define <8 x i8> @t3(i8* %A, i8* %B) nounwind { define void @t4(i32* %in, i32* %out) nounwind { entry: -; CHECK: t4: +; CHECK-LABEL: t4: ; CHECK: vld2.32 ; CHECK-NOT: vmov ; CHECK: vld2.32 @@ -135,7 +135,7 @@ return2: } define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { -; CHECK: t5: +; CHECK-LABEL: t5: ; CHECK: vld1.32 ; How can FileCheck match Q and D registers? We need a lisp interpreter. ; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}} @@ -153,7 +153,7 @@ define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind { } define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { -; CHECK: t6: +; CHECK-LABEL: t6: ; CHECK: vldr ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]] ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]} @@ -167,7 +167,7 @@ define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind { define void @t7(i32* %iptr, i32* %optr) nounwind { entry: -; CHECK: t7: +; CHECK-LABEL: t7: ; CHECK: vld2.32 ; CHECK: vst2.32 ; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, @@ -189,7 +189,7 @@ entry: ; PR7156 define arm_aapcs_vfpcc i32 @t8() nounwind { -; CHECK: t8: +; CHECK-LABEL: t8: ; CHECK: vrsqrte.f32 q8, q8 bb.nph55.bb.nph55.split_crit_edge: br label %bb3 @@ -238,7 +238,7 @@ bb14: ; preds = %bb6 ; PR7157 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { -; CHECK: t9: +; CHECK-LABEL: t9: ; CHECK: vldr ; CHECK-NOT: vmov d{{.*}}, d16 ; CHECK: vmov.i32 d17 @@ -270,7 +270,7 @@ define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind { ; PR7162 define arm_aapcs_vfpcc i32 @t10() nounwind { entry: -; CHECK: t10: +; CHECK-LABEL: t10: ; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000 ; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]] ; CHECK: vadd.f32 q8, q8, q8 diff --git a/test/CodeGen/ARM/ret_sret_vector.ll b/test/CodeGen/ARM/ret_sret_vector.ll index 9bb3519555..f9c46262b6 100644 --- a/test/CodeGen/ARM/ret_sret_vector.ll +++ b/test/CodeGen/ARM/ret_sret_vector.ll @@ -6,7 +6,7 @@ target triple = "thumbv7-apple-ios3.0.0" define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) { %foo = fadd <4 x double> %a, %b ret <4 x double> %foo -; CHECK: PR14337: +; CHECK-LABEL: PR14337: ; CHECK: vst1.64 ; CHECK: vst1.64 } diff --git a/test/CodeGen/ARM/sbfx.ll b/test/CodeGen/ARM/sbfx.ll index d29693e4cf..36fbd1939c 100644 --- a/test/CodeGen/ARM/sbfx.ll +++ b/test/CodeGen/ARM/sbfx.ll @@ -2,7 +2,7 @@ define i32 @f1(i32 %a) { entry: -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: sbfx r0, r0, #0, #20 %tmp = shl i32 %a, 12 %tmp2 = ashr i32 %tmp, 12 @@ -11,7 +11,7 @@ entry: define i32 @f2(i32 %a) { entry: -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: bfc r0, #20, #12 %tmp = shl i32 %a, 12 %tmp2 = lshr i32 %tmp, 12 @@ -20,7 +20,7 @@ entry: define i32 @f3(i32 %a) { entry: -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: sbfx r0, r0, #5, #3 %tmp = shl i32 %a, 24 %tmp2 = ashr i32 %tmp, 29 @@ -29,7 +29,7 @@ entry: define i32 @f4(i32 %a) { entry: -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: ubfx r0, r0, #5, #3 %tmp = shl i32 %a, 24 %tmp2 = lshr i32 %tmp, 29 @@ -38,7 +38,7 @@ entry: define i32 @f5(i32 %a) { entry: -; CHECK: f5: +; CHECK-LABEL: f5: ; CHECK-NOT: sbfx ; CHECK: bx %tmp = shl i32 %a, 3 diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll index c9ac66acbf..765437af1a 100644 --- a/test/CodeGen/ARM/select-imm.ll +++ b/test/CodeGen/ARM/select-imm.ll @@ -4,16 +4,16 @@ define i32 @t1(i32 %c) nounwind readnone { entry: -; ARM: t1: +; ARM-LABEL: t1: ; ARM: mov [[R1:r[0-9]+]], #101 ; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256 ; ARM: movgt r0, #123 -; ARMT2: t1: +; ARMT2-LABEL: t1: ; ARMT2: movw r0, #357 ; ARMT2: movgt r0, #123 -; THUMB2: t1: +; THUMB2-LABEL: t1: ; THUMB2: movw r0, #357 ; THUMB2: movgt r0, #123 @@ -24,16 +24,16 @@ entry: define i32 @t2(i32 %c) nounwind readnone { entry: -; ARM: t2: +; ARM-LABEL: t2: ; ARM: mov r0, #123 ; ARM: movgt r0, #101 ; ARM: orrgt r0, r0, #256 -; ARMT2: t2: +; ARMT2-LABEL: t2: ; ARMT2: mov r0, #123 ; ARMT2: movwgt r0, #357 -; THUMB2: t2: +; THUMB2-LABEL: t2: ; THUMB2: mov{{(s|\.w)}} r0, #123 ; THUMB2: movwgt r0, #357 @@ -44,15 +44,15 @@ entry: define i32 @t3(i32 %a) nounwind readnone { entry: -; ARM: t3: +; ARM-LABEL: t3: ; ARM: mov r0, #0 ; ARM: moveq r0, #1 -; ARMT2: t3: +; ARMT2-LABEL: t3: ; ARMT2: mov r0, #0 ; ARMT2: moveq r0, #1 -; THUMB2: t3: +; THUMB2-LABEL: t3: ; THUMB2: mov{{(s|\.w)}} r0, #0 ; THUMB2: moveq r0, #1 %0 = icmp eq i32 %a, 160 @@ -62,15 +62,15 @@ entry: define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind { entry: -; ARM: t4: +; ARM-LABEL: t4: ; ARM: ldr ; ARM: mov{{lt|ge}} -; ARMT2: t4: +; ARMT2-LABEL: t4: ; ARMT2: movwlt [[R0:r[0-9]+]], #65365 ; ARMT2: movtlt [[R0]], #65365 -; THUMB2: t4: +; THUMB2-LABEL: t4: ; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290 %0 = icmp slt i32 %a, %b %1 = select i1 %0, i32 4283826005, i32 %x @@ -80,13 +80,13 @@ entry: ; rdar://9758317 define i32 @t5(i32 %a) nounwind { entry: -; ARM: t5: +; ARM-LABEL: t5: ; ARM-NOT: mov ; ARM: cmp r0, #1 ; ARM-NOT: mov ; ARM: movne r0, #0 -; THUMB2: t5: +; THUMB2-LABEL: t5: ; THUMB2-NOT: mov ; THUMB2: cmp r0, #1 ; THUMB2: it ne @@ -98,12 +98,12 @@ entry: define i32 @t6(i32 %a) nounwind { entry: -; ARM: t6: +; ARM-LABEL: t6: ; ARM-NOT: mov ; ARM: cmp r0, #0 ; ARM: movne r0, #1 -; THUMB2: t6: +; THUMB2-LABEL: t6: ; THUMB2-NOT: mov ; THUMB2: cmp r0, #0 ; THUMB2: it ne diff --git a/test/CodeGen/ARM/select.ll b/test/CodeGen/ARM/select.ll index 62708ed53d..d5c3a270a4 100644 --- a/test/CodeGen/ARM/select.ll +++ b/test/CodeGen/ARM/select.ll @@ -3,7 +3,7 @@ ; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON define i32 @f1(i32 %a.s) { -;CHECK: f1: +;CHECK-LABEL: f1: ;CHECK: moveq entry: %tmp = icmp eq i32 %a.s, 4 @@ -12,7 +12,7 @@ entry: } define i32 @f2(i32 %a.s) { -;CHECK: f2: +;CHECK-LABEL: f2: ;CHECK: movgt entry: %tmp = icmp sgt i32 %a.s, 4 @@ -21,7 +21,7 @@ entry: } define i32 @f3(i32 %a.s, i32 %b.s) { -;CHECK: f3: +;CHECK-LABEL: f3: ;CHECK: movlt entry: %tmp = icmp slt i32 %a.s, %b.s @@ -30,7 +30,7 @@ entry: } define i32 @f4(i32 %a.s, i32 %b.s) { -;CHECK: f4: +;CHECK-LABEL: f4: ;CHECK: movle entry: %tmp = icmp sle i32 %a.s, %b.s @@ -39,7 +39,7 @@ entry: } define i32 @f5(i32 %a.u, i32 %b.u) { -;CHECK: f5: +;CHECK-LABEL: f5: ;CHECK: movls entry: %tmp = icmp ule i32 %a.u, %b.u @@ -48,7 +48,7 @@ entry: } define i32 @f6(i32 %a.u, i32 %b.u) { -;CHECK: f6: +;CHECK-LABEL: f6: ;CHECK: movhi entry: %tmp = icmp ugt i32 %a.u, %b.u @@ -57,10 +57,10 @@ entry: } define double @f7(double %a, double %b) { -;CHECK: f7: +;CHECK-LABEL: f7: ;CHECK: movlt ;CHECK: movlt -;CHECK-VFP: f7: +;CHECK-VFP-LABEL: f7: ;CHECK-VFP: vmovmi %tmp = fcmp olt double %a, 1.234e+00 %tmp1 = select i1 %tmp, double -1.000e+00, double %b @@ -94,7 +94,7 @@ define arm_apcscc float @f8(i32 %a) nounwind { ; Glue values can only have a single use, but the following test exposed a ; case where a SELECT was lowered with 2 uses of a comparison, causing the ; scheduler to assert. -; CHECK-VFP: f9: +; CHECK-VFP-LABEL: f9: declare i8* @objc_msgSend(i8*, i8*, ...) define void @f9() optsize { diff --git a/test/CodeGen/ARM/select_xform.ll b/test/CodeGen/ARM/select_xform.ll index 7507808912..e13504a42a 100644 --- a/test/CodeGen/ARM/select_xform.ll +++ b/test/CodeGen/ARM/select_xform.ll @@ -3,11 +3,11 @@ ; rdar://8662825 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { -; ARM: t1: +; ARM-LABEL: t1: ; ARM: suble r1, r1, #-2147483647 ; ARM: mov r0, r1 -; T2: t1: +; T2-LABEL: t1: ; T2: mvn r0, #-2147483648 ; T2: addle r1, r0 ; T2: mov r0, r1 @@ -18,11 +18,11 @@ define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind { } define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { -; ARM: t2: +; ARM-LABEL: t2: ; ARM: suble r1, r1, #10 ; ARM: mov r0, r1 -; T2: t2: +; T2-LABEL: t2: ; T2: suble r1, #10 ; T2: mov r0, r1 %tmp1 = icmp sgt i32 %c, 10 @@ -32,11 +32,11 @@ define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { } define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { -; ARM: t3: +; ARM-LABEL: t3: ; ARM: andge r3, r3, r2 ; ARM: mov r0, r3 -; T2: t3: +; T2-LABEL: t3: ; T2: andge r3, r2 ; T2: mov r0, r3 %cond = icmp slt i32 %a, %b @@ -46,11 +46,11 @@ define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { } define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { -; ARM: t4: +; ARM-LABEL: t4: ; ARM: orrge r3, r3, r2 ; ARM: mov r0, r3 -; T2: t4: +; T2-LABEL: t4: ; T2: orrge r3, r2 ; T2: mov r0, r3 %cond = icmp slt i32 %a, %b @@ -61,11 +61,11 @@ define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind { define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind { entry: -; ARM: t5: +; ARM-LABEL: t5: ; ARM-NOT: moveq ; ARM: orreq r2, r2, #1 -; T2: t5: +; T2-LABEL: t5: ; T2-NOT: moveq ; T2: orreq r2, r2, #1 %tmp1 = icmp eq i32 %a, %b @@ -75,11 +75,11 @@ entry: } define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { -; ARM: t6: +; ARM-LABEL: t6: ; ARM-NOT: movge ; ARM: eorlt r3, r3, r2 -; T2: t6: +; T2-LABEL: t6: ; T2-NOT: movge ; T2: eorlt r3, r2 %cond = icmp slt i32 %a, %b @@ -90,11 +90,11 @@ define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind { entry: -; ARM: t7: +; ARM-LABEL: t7: ; ARM-NOT: lsleq ; ARM: andeq r2, r2, r2, lsl #1 -; T2: t7: +; T2-LABEL: t7: ; T2-NOT: lsleq.w ; T2: andeq.w r2, r2, r2, lsl #1 %tmp1 = shl i32 %c, 1 @@ -106,11 +106,11 @@ entry: ; Fold ORRri into movcc. define i32 @t8(i32 %a, i32 %b) nounwind { -; ARM: t8: +; ARM-LABEL: t8: ; ARM: cmp r0, r1 ; ARM: orrge r0, r1, #1 -; T2: t8: +; T2-LABEL: t8: ; T2: cmp r0, r1 ; T2: orrge r0, r1, #1 %x = or i32 %b, 1 @@ -121,11 +121,11 @@ define i32 @t8(i32 %a, i32 %b) nounwind { ; Fold ANDrr into movcc. define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind { -; ARM: t9: +; ARM-LABEL: t9: ; ARM: cmp r0, r1 ; ARM: andge r0, r1, r2 -; T2: t9: +; T2-LABEL: t9: ; T2: cmp r0, r1 ; T2: andge.w r0, r1, r2 %x = and i32 %b, %c @@ -136,11 +136,11 @@ define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind { ; Fold EORrs into movcc. define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { -; ARM: t10: +; ARM-LABEL: t10: ; ARM: cmp r0, r1 ; ARM: eorge r0, r1, r2, lsl #7 -; T2: t10: +; T2-LABEL: t10: ; T2: cmp r0, r1 ; T2: eorge.w r0, r1, r2, lsl #7 %s = shl i32 %c, 7 @@ -152,11 +152,11 @@ define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind { ; Fold ORRri into movcc, reversing the condition. define i32 @t11(i32 %a, i32 %b) nounwind { -; ARM: t11: +; ARM-LABEL: t11: ; ARM: cmp r0, r1 ; ARM: orrlt r0, r1, #1 -; T2: t11: +; T2-LABEL: t11: ; T2: cmp r0, r1 ; T2: orrlt r0, r1, #1 %x = or i32 %b, 1 @@ -167,11 +167,11 @@ define i32 @t11(i32 %a, i32 %b) nounwind { ; Fold ADDri12 into movcc define i32 @t12(i32 %a, i32 %b) nounwind { -; ARM: t12: +; ARM-LABEL: t12: ; ARM: cmp r0, r1 ; ARM: addge r0, r1, -; T2: t12: +; T2-LABEL: t12: ; T2: cmp r0, r1 ; T2: addwge r0, r1, #3000 %x = add i32 %b, 3000 diff --git a/test/CodeGen/ARM/spill-q.ll b/test/CodeGen/ARM/spill-q.ll index e93cdbc10a..b9246635e4 100644 --- a/test/CodeGen/ARM/spill-q.ll +++ b/test/CodeGen/ARM/spill-q.ll @@ -10,7 +10,7 @@ declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly define void @aaa(%quuz* %this, i8* %block) { -; CHECK: aaa: +; CHECK-LABEL: aaa: ; CHECK: bic {{.*}}, #15 ; CHECK: vst1.64 {{.*}}sp:128 ; CHECK: vld1.64 {{.*}}sp:128 diff --git a/test/CodeGen/ARM/struct_byval.ll b/test/CodeGen/ARM/struct_byval.ll index e9541c2788..012b994853 100644 --- a/test/CodeGen/ARM/struct_byval.ll +++ b/test/CodeGen/ARM/struct_byval.ll @@ -6,7 +6,7 @@ define i32 @f() nounwind ssp { entry: -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: ldr ; CHECK: str ; CHECK-NOT:bne @@ -18,7 +18,7 @@ entry: ; Generate a loop for large struct byval define i32 @g() nounwind ssp { entry: -; CHECK: g: +; CHECK-LABEL: g: ; CHECK: ldr ; CHECK: sub ; CHECK: str @@ -31,7 +31,7 @@ entry: ; Generate a loop using NEON instructions define i32 @h() nounwind ssp { entry: -; CHECK: h: +; CHECK-LABEL: h: ; CHECK: vld1 ; CHECK: sub ; CHECK: vst1 diff --git a/test/CodeGen/ARM/sub-cmp-peephole.ll b/test/CodeGen/ARM/sub-cmp-peephole.ll index 2961b94d2c..1b411e3af1 100644 --- a/test/CodeGen/ARM/sub-cmp-peephole.ll +++ b/test/CodeGen/ARM/sub-cmp-peephole.ll @@ -2,7 +2,7 @@ define i32 @f(i32 %a, i32 %b) nounwind ssp { entry: -; CHECK: f: +; CHECK-LABEL: f: ; CHECK: subs ; CHECK-NOT: cmp %cmp = icmp sgt i32 %a, %b @@ -13,7 +13,7 @@ entry: define i32 @g(i32 %a, i32 %b) nounwind ssp { entry: -; CHECK: g: +; CHECK-LABEL: g: ; CHECK: subs ; CHECK-NOT: cmp %cmp = icmp slt i32 %a, %b @@ -24,7 +24,7 @@ entry: define i32 @h(i32 %a, i32 %b) nounwind ssp { entry: -; CHECK: h: +; CHECK-LABEL: h: ; CHECK: subs ; CHECK-NOT: cmp %cmp = icmp sgt i32 %a, 3 @@ -36,7 +36,7 @@ entry: ; rdar://11725965 define i32 @i(i32 %a, i32 %b) nounwind readnone ssp { entry: -; CHECK: i: +; CHECK-LABEL: i: ; CHECK: subs ; CHECK-NOT: cmp %cmp = icmp ult i32 %a, %b @@ -48,7 +48,7 @@ entry: ; a swapped sub. define i32 @j(i32 %a, i32 %b) nounwind { entry: -; CHECK: j: +; CHECK-LABEL: j: ; CHECK: sub ; CHECK: cmp %cmp = icmp eq i32 %b, %a diff --git a/test/CodeGen/ARM/tail-dup.ll b/test/CodeGen/ARM/tail-dup.ll index eb4d0bab92..d654056eaf 100644 --- a/test/CodeGen/ARM/tail-dup.ll +++ b/test/CodeGen/ARM/tail-dup.ll @@ -2,7 +2,7 @@ ; We should be able to tail-duplicate the basic block containing the indirectbr ; into all of its predecessors. -; CHECK: fn: +; CHECK-LABEL: fn: ; CHECK: mov pc ; CHECK: mov pc ; CHECK: mov pc diff --git a/test/CodeGen/ARM/tail-opts.ll b/test/CodeGen/ARM/tail-opts.ll index 220b0f1737..37e9a4af3b 100644 --- a/test/CodeGen/ARM/tail-opts.ll +++ b/test/CodeGen/ARM/tail-opts.ll @@ -14,7 +14,7 @@ declare i8* @choose(i8*, i8*) ; BranchFolding should tail-duplicate the indirect jump to avoid ; redundant branching. -; CHECK: tail_duplicate_me: +; CHECK-LABEL: tail_duplicate_me: ; CHECK: qux ; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK ; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK diff --git a/test/CodeGen/ARM/test-sharedidx.ll b/test/CodeGen/ARM/test-sharedidx.ll index 93340c300c..9203f166ff 100644 --- a/test/CodeGen/ARM/test-sharedidx.ll +++ b/test/CodeGen/ARM/test-sharedidx.ll @@ -14,7 +14,7 @@ ; rdar://10674430 define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp { entry: -; CHECK: sharedidx: +; CHECK-LABEL: sharedidx: %cmp8 = icmp eq i32 %len, 0 br i1 %cmp8, label %for.end, label %for.body diff --git a/test/CodeGen/ARM/tls-models.ll b/test/CodeGen/ARM/tls-models.ll index a5f3c9005a..ccc9032313 100644 --- a/test/CodeGen/ARM/tls-models.ll +++ b/test/CodeGen/ARM/tls-models.ll @@ -21,9 +21,9 @@ entry: ret i32* @external_gd ; Non-PIC code can use initial-exec, PIC code has to use general dynamic. - ; CHECK-NONPIC: f1: + ; CHECK-NONPIC-LABEL: f1: ; CHECK-NONPIC: external_gd(gottpoff) - ; CHECK-PIC: f1: + ; CHECK-PIC-LABEL: f1: ; CHECK-PIC: external_gd(tlsgd) } @@ -33,9 +33,9 @@ entry: ; Non-PIC code can use local exec, PIC code can use local dynamic, ; but that is not implemented, so falls back to general dynamic. - ; CHECK-NONPIC: f2: + ; CHECK-NONPIC-LABEL: f2: ; CHECK-NONPIC: internal_gd(tpoff) - ; CHECK-PIC: f2: + ; CHECK-PIC-LABEL: f2: ; CHECK-PIC: internal_gd(tlsgd) } @@ -48,9 +48,9 @@ entry: ; Non-PIC code can use initial exec, PIC should use local dynamic, ; but that is not implemented, so falls back to general dynamic. - ; CHECK-NONPIC: f3: + ; CHECK-NONPIC-LABEL: f3: ; CHECK-NONPIC: external_ld(gottpoff) - ; CHECK-PIC: f3: + ; CHECK-PIC-LABEL: f3: ; CHECK-PIC: external_ld(tlsgd) } @@ -60,9 +60,9 @@ entry: ; Non-PIC code can use local exec, PIC code can use local dynamic, ; but that is not implemented, so it falls back to general dynamic. - ; CHECK-NONPIC: f4: + ; CHECK-NONPIC-LABEL: f4: ; CHECK-NONPIC: internal_ld(tpoff) - ; CHECK-PIC: f4: + ; CHECK-PIC-LABEL: f4: ; CHECK-PIC: internal_ld(tlsgd) } @@ -74,9 +74,9 @@ entry: ret i32* @external_ie ; Non-PIC and PIC code will use initial exec as specified. - ; CHECK-NONPIC: f5: + ; CHECK-NONPIC-LABEL: f5: ; CHECK-NONPIC: external_ie(gottpoff) - ; CHECK-PIC: f5: + ; CHECK-PIC-LABEL: f5: ; CHECK-PIC: external_ie(gottpoff) } @@ -85,9 +85,9 @@ entry: ret i32* @internal_ie ; Non-PIC code can use local exec, PIC code use initial exec as specified. - ; CHECK-NONPIC: f6: + ; CHECK-NONPIC-LABEL: f6: ; CHECK-NONPIC: internal_ie(tpoff) - ; CHECK-PIC: f6: + ; CHECK-PIC-LABEL: f6: ; CHECK-PIC: internal_ie(gottpoff) } @@ -99,9 +99,9 @@ entry: ret i32* @external_le ; Non-PIC and PIC code will use local exec as specified. - ; CHECK-NONPIC: f7: + ; CHECK-NONPIC-LABEL: f7: ; CHECK-NONPIC: external_le(tpoff) - ; CHECK-PIC: f7: + ; CHECK-PIC-LABEL: f7: ; CHECK-PIC: external_le(tpoff) } @@ -110,8 +110,8 @@ entry: ret i32* @internal_le ; Non-PIC and PIC code will use local exec as specified. - ; CHECK-NONPIC: f8: + ; CHECK-NONPIC-LABEL: f8: ; CHECK-NONPIC: internal_le(tpoff) - ; CHECK-PIC: f8: + ; CHECK-PIC-LABEL: f8: ; CHECK-PIC: internal_le(tpoff) } diff --git a/test/CodeGen/ARM/tls2.ll b/test/CodeGen/ARM/tls2.ll index 57370c4de1..f048125831 100644 --- a/test/CodeGen/ARM/tls2.ll +++ b/test/CodeGen/ARM/tls2.ll @@ -6,10 +6,10 @@ @i = external thread_local global i32 ; <i32*> [#uses=2] define i32 @f() { -; CHECK-NONPIC: f: +; CHECK-NONPIC-LABEL: f: ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) -; CHECK-PIC: f: +; CHECK-PIC-LABEL: f: ; CHECK-PIC: __tls_get_addr entry: %tmp1 = load i32* @i ; <i32> [#uses=1] @@ -17,10 +17,10 @@ entry: } define i32* @g() { -; CHECK-NONPIC: g: +; CHECK-NONPIC-LABEL: g: ; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}] ; CHECK-NONPIC: i(gottpoff) -; CHECK-PIC: g: +; CHECK-PIC-LABEL: g: ; CHECK-PIC: __tls_get_addr entry: ret i32* @i diff --git a/test/CodeGen/ARM/trap.ll b/test/CodeGen/ARM/trap.ll index a4e3c3c0ef..db88a0354d 100644 --- a/test/CodeGen/ARM/trap.ll +++ b/test/CodeGen/ARM/trap.ll @@ -23,10 +23,10 @@ define void @t() nounwind { entry: -; INSTR: t: +; INSTR-LABEL: t: ; INSTR: trap -; FUNC: t: +; FUNC-LABEL: t: ; FUNC: bl __trap ; ENCODING-NACL: f0 de fe e7 @@ -39,10 +39,10 @@ entry: define void @t2() nounwind { entry: -; INSTR: t2: +; INSTR-LABEL: t2: ; INSTR: trap -; FUNC: t2: +; FUNC-LABEL: t2: ; FUNC: bl __trap ; ENCODING-NACL: f0 de fe e7 diff --git a/test/CodeGen/ARM/twoaddrinstr.ll b/test/CodeGen/ARM/twoaddrinstr.ll index fc2aa1e568..2172f6b9a6 100644 --- a/test/CodeGen/ARM/twoaddrinstr.ll +++ b/test/CodeGen/ARM/twoaddrinstr.ll @@ -3,7 +3,7 @@ define void @PR13378() nounwind { ; This was orriginally a crasher trying to schedule the instructions. -; CHECK: PR13378: +; CHECK-LABEL: PR13378: ; CHECK: vld1.32 ; CHECK-NEXT: vst1.32 ; CHECK-NEXT: vst1.32 diff --git a/test/CodeGen/ARM/unaligned_load_store.ll b/test/CodeGen/ARM/unaligned_load_store.ll index 3064202eb3..e7ff63f8db 100644 --- a/test/CodeGen/ARM/unaligned_load_store.ll +++ b/test/CodeGen/ARM/unaligned_load_store.ll @@ -7,7 +7,7 @@ define void @t(i8* nocapture %a, i8* nocapture %b) nounwind { entry: -; EXPANDED: t: +; EXPANDED-LABEL: t: ; EXPANDED: ldrb [[R2:r[0-9]+]] ; EXPANDED: ldrb [[R3:r[0-9]+]] ; EXPANDED: ldrb [[R12:r[0-9]+]] @@ -17,7 +17,7 @@ entry: ; EXPANDED: strb [[R3]] ; EXPANDED: strb [[R2]] -; UNALIGNED: t: +; UNALIGNED-LABEL: t: ; UNALIGNED: ldr r1 ; UNALIGNED: str r1 @@ -30,13 +30,13 @@ entry: define void @hword(double* %a, double* %b) nounwind { entry: -; EXPANDED: hword: +; EXPANDED-LABEL: hword: ; EXPANDED-NOT: vld1 ; EXPANDED: ldrh ; EXPANDED-NOT: str1 ; EXPANDED: strh -; UNALIGNED: hword: +; UNALIGNED-LABEL: hword: ; UNALIGNED: vld1.16 ; UNALIGNED: vst1.16 %tmp = load double* %a, align 2 @@ -46,13 +46,13 @@ entry: define void @byte(double* %a, double* %b) nounwind { entry: -; EXPANDED: byte: +; EXPANDED-LABEL: byte: ; EXPANDED-NOT: vld1 ; EXPANDED: ldrb ; EXPANDED-NOT: str1 ; EXPANDED: strb -; UNALIGNED: byte: +; UNALIGNED-LABEL: byte: ; UNALIGNED: vld1.8 ; UNALIGNED: vst1.8 %tmp = load double* %a, align 1 @@ -62,11 +62,11 @@ entry: define void @byte_word_ops(i32* %a, i32* %b) nounwind { entry: -; EXPANDED: byte_word_ops: +; EXPANDED-LABEL: byte_word_ops: ; EXPANDED: ldrb ; EXPANDED: strb -; UNALIGNED: byte_word_ops: +; UNALIGNED-LABEL: byte_word_ops: ; UNALIGNED-NOT: ldrb ; UNALIGNED: ldr ; UNALIGNED-NOT: strb diff --git a/test/CodeGen/ARM/unaligned_load_store_vector.ll b/test/CodeGen/ARM/unaligned_load_store_vector.ll index 25ae651793..968a2c7ad0 100644 --- a/test/CodeGen/ARM/unaligned_load_store_vector.ll +++ b/test/CodeGen/ARM/unaligned_load_store_vector.ll @@ -4,7 +4,7 @@ ;SIZE = 64 ;TYPE = <8 x i8> define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v8i8_1: +;CHECK-LABEL: v64_v8i8_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -22,7 +22,7 @@ entry: ;SIZE = 64 ;TYPE = <4 x i16> define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v4i16_1: +;CHECK-LABEL: v64_v4i16_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -40,7 +40,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x i32> define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2i32_1: +;CHECK-LABEL: v64_v2i32_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -58,7 +58,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x float> define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2f32_1: +;CHECK-LABEL: v64_v2f32_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -76,7 +76,7 @@ entry: ;SIZE = 128 ;TYPE = <16 x i8> define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v16i8_1: +;CHECK-LABEL: v128_v16i8_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -94,7 +94,7 @@ entry: ;SIZE = 128 ;TYPE = <8 x i16> define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v8i16_1: +;CHECK-LABEL: v128_v8i16_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -112,7 +112,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x i32> define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4i32_1: +;CHECK-LABEL: v128_v4i32_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -130,7 +130,7 @@ entry: ;SIZE = 128 ;TYPE = <2 x i64> define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v2i64_1: +;CHECK-LABEL: v128_v2i64_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -148,7 +148,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x float> define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4f32_1: +;CHECK-LABEL: v128_v4f32_1: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -166,7 +166,7 @@ entry: ;SIZE = 64 ;TYPE = <8 x i8> define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v8i8_2: +;CHECK-LABEL: v64_v8i8_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -184,7 +184,7 @@ entry: ;SIZE = 64 ;TYPE = <4 x i16> define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v4i16_2: +;CHECK-LABEL: v64_v4i16_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -202,7 +202,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x i32> define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2i32_2: +;CHECK-LABEL: v64_v2i32_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -220,7 +220,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x float> define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2f32_2: +;CHECK-LABEL: v64_v2f32_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -238,7 +238,7 @@ entry: ;SIZE = 128 ;TYPE = <16 x i8> define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v16i8_2: +;CHECK-LABEL: v128_v16i8_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -256,7 +256,7 @@ entry: ;SIZE = 128 ;TYPE = <8 x i16> define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v8i16_2: +;CHECK-LABEL: v128_v8i16_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -274,7 +274,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x i32> define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4i32_2: +;CHECK-LABEL: v128_v4i32_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -292,7 +292,7 @@ entry: ;SIZE = 128 ;TYPE = <2 x i64> define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v2i64_2: +;CHECK-LABEL: v128_v2i64_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -310,7 +310,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x float> define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4f32_2: +;CHECK-LABEL: v128_v4f32_2: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -328,7 +328,7 @@ entry: ;SIZE = 64 ;TYPE = <8 x i8> define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v8i8_4: +;CHECK-LABEL: v64_v8i8_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -346,7 +346,7 @@ entry: ;SIZE = 64 ;TYPE = <4 x i16> define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v4i16_4: +;CHECK-LABEL: v64_v4i16_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -364,7 +364,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x i32> define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2i32_4: +;CHECK-LABEL: v64_v2i32_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -382,7 +382,7 @@ entry: ;SIZE = 64 ;TYPE = <2 x float> define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v64_v2f32_4: +;CHECK-LABEL: v64_v2f32_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -400,7 +400,7 @@ entry: ;SIZE = 128 ;TYPE = <16 x i8> define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v16i8_4: +;CHECK-LABEL: v128_v16i8_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -418,7 +418,7 @@ entry: ;SIZE = 128 ;TYPE = <8 x i16> define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v8i16_4: +;CHECK-LABEL: v128_v8i16_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -436,7 +436,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x i32> define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4i32_4: +;CHECK-LABEL: v128_v4i32_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -454,7 +454,7 @@ entry: ;SIZE = 128 ;TYPE = <2 x i64> define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v2i64_4: +;CHECK-LABEL: v128_v2i64_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 @@ -472,7 +472,7 @@ entry: ;SIZE = 128 ;TYPE = <4 x float> define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind { -;CHECK: v128_v4f32_4: +;CHECK-LABEL: v128_v4f32_4: entry: %po = getelementptr i8* %out, i32 0 %pi = getelementptr i8* %in, i32 0 diff --git a/test/CodeGen/ARM/undef-sext.ll b/test/CodeGen/ARM/undef-sext.ll index 2c28da3b64..c6d76d0017 100644 --- a/test/CodeGen/ARM/undef-sext.ll +++ b/test/CodeGen/ARM/undef-sext.ll @@ -4,7 +4,7 @@ define i32 @t(i32* %a) nounwind { entry: -; CHECK: t: +; CHECK-LABEL: t: ; CHECK: ldr r0, [r0] ; CHECK: bx lr %0 = sext i16 undef to i32 diff --git a/test/CodeGen/ARM/unwind-init.ll b/test/CodeGen/ARM/unwind-init.ll index 11683d5605..1e12f55108 100644 --- a/test/CodeGen/ARM/unwind-init.ll +++ b/test/CodeGen/ARM/unwind-init.ll @@ -11,7 +11,7 @@ define void @calls_unwind_init() { ret void } -; CHECK: calls_unwind_init: +; CHECK-LABEL: calls_unwind_init: ; CHECK: push {r4, r5, r6, r7, r8, r9, r10, r11, lr} ; CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15} ; CHECK: vpop {d8, d9, d10, d11, d12, d13, d14, d15} diff --git a/test/CodeGen/ARM/v1-constant-fold.ll b/test/CodeGen/ARM/v1-constant-fold.ll index b86d5db29c..eb49a81ab7 100644 --- a/test/CodeGen/ARM/v1-constant-fold.ll +++ b/test/CodeGen/ARM/v1-constant-fold.ll @@ -2,7 +2,7 @@ ; PR15611. Check that we don't crash when constant folding v1i32 types. -; CHECK: foo: +; CHECK-LABEL: foo: define void @foo(i32 %arg) { bb: %tmp = insertelement <4 x i32> undef, i32 %arg, i32 0 diff --git a/test/CodeGen/ARM/vaba.ll b/test/CodeGen/ARM/vaba.ll index 4fe1c43479..97139e9b6c 100644 --- a/test/CodeGen/ARM/vaba.ll +++ b/test/CodeGen/ARM/vaba.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vabas8: +;CHECK-LABEL: vabas8: ;CHECK: vaba.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vabas16: +;CHECK-LABEL: vabas16: ;CHECK: vaba.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -23,7 +23,7 @@ define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vabas32: +;CHECK-LABEL: vabas32: ;CHECK: vaba.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -34,7 +34,7 @@ define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vabau8: +;CHECK-LABEL: vabau8: ;CHECK: vaba.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -45,7 +45,7 @@ define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vabau16: +;CHECK-LABEL: vabau16: ;CHECK: vaba.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -56,7 +56,7 @@ define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vabau32: +;CHECK-LABEL: vabau32: ;CHECK: vaba.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -67,7 +67,7 @@ define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { -;CHECK: vabaQs8: +;CHECK-LABEL: vabaQs8: ;CHECK: vaba.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -78,7 +78,7 @@ define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind } define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: vabaQs16: +;CHECK-LABEL: vabaQs16: ;CHECK: vaba.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -89,7 +89,7 @@ define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind } define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: vabaQs32: +;CHECK-LABEL: vabaQs32: ;CHECK: vaba.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind } define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { -;CHECK: vabaQu8: +;CHECK-LABEL: vabaQu8: ;CHECK: vaba.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -111,7 +111,7 @@ define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind } define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: vabaQu16: +;CHECK-LABEL: vabaQu16: ;CHECK: vaba.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -122,7 +122,7 @@ define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind } define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: vabaQu32: +;CHECK-LABEL: vabaQu32: ;CHECK: vaba.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -149,7 +149,7 @@ declare <8 x i16> @llvm.arm.neon.vabdu.v8i16(<8 x i16>, <8 x i16>) nounwind read declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vabals8: +;CHECK-LABEL: vabals8: ;CHECK: vabal.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -161,7 +161,7 @@ define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vabals16: +;CHECK-LABEL: vabals16: ;CHECK: vabal.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -173,7 +173,7 @@ define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vabals32: +;CHECK-LABEL: vabals32: ;CHECK: vabal.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -185,7 +185,7 @@ define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vabalu8: +;CHECK-LABEL: vabalu8: ;CHECK: vabal.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -197,7 +197,7 @@ define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vabalu16: +;CHECK-LABEL: vabalu16: ;CHECK: vabal.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -209,7 +209,7 @@ define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vabalu32: +;CHECK-LABEL: vabalu32: ;CHECK: vabal.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vabd.ll b/test/CodeGen/ARM/vabd.ll index 9ec734fa76..2eb6d935de 100644 --- a/test/CodeGen/ARM/vabd.ll +++ b/test/CodeGen/ARM/vabd.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vabds8: +;CHECK-LABEL: vabds8: ;CHECK: vabd.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vabds16: +;CHECK-LABEL: vabds16: ;CHECK: vabd.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vabds32: +;CHECK-LABEL: vabds32: ;CHECK: vabd.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vabdu8: +;CHECK-LABEL: vabdu8: ;CHECK: vabd.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vabdu16: +;CHECK-LABEL: vabdu16: ;CHECK: vabd.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vabdu32: +;CHECK-LABEL: vabdu32: ;CHECK: vabd.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vabdf32: +;CHECK-LABEL: vabdf32: ;CHECK: vabd.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -64,7 +64,7 @@ define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vabdQs8: +;CHECK-LABEL: vabdQs8: ;CHECK: vabd.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -73,7 +73,7 @@ define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vabdQs16: +;CHECK-LABEL: vabdQs16: ;CHECK: vabd.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -82,7 +82,7 @@ define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vabdQs32: +;CHECK-LABEL: vabdQs32: ;CHECK: vabd.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -91,7 +91,7 @@ define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vabdQu8: +;CHECK-LABEL: vabdQu8: ;CHECK: vabd.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -100,7 +100,7 @@ define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vabdQu16: +;CHECK-LABEL: vabdQu16: ;CHECK: vabd.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -109,7 +109,7 @@ define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vabdQu32: +;CHECK-LABEL: vabdQu32: ;CHECK: vabd.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -118,7 +118,7 @@ define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vabdQf32: +;CHECK-LABEL: vabdQf32: ;CHECK: vabd.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind read declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vabdls8: +;CHECK-LABEL: vabdls8: ;CHECK: vabdl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -157,7 +157,7 @@ define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vabdls16: +;CHECK-LABEL: vabdls16: ;CHECK: vabdl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -167,7 +167,7 @@ define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vabdls32: +;CHECK-LABEL: vabdls32: ;CHECK: vabdl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -177,7 +177,7 @@ define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vabdlu8: +;CHECK-LABEL: vabdlu8: ;CHECK: vabdl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -187,7 +187,7 @@ define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vabdlu16: +;CHECK-LABEL: vabdlu16: ;CHECK: vabdl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -197,7 +197,7 @@ define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vabdlu32: +;CHECK-LABEL: vabdlu32: ;CHECK: vabdl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vabs.ll b/test/CodeGen/ARM/vabs.ll index 18ba61f81e..96dd38ec2e 100644 --- a/test/CodeGen/ARM/vabs.ll +++ b/test/CodeGen/ARM/vabs.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { -;CHECK: vabss8: +;CHECK-LABEL: vabss8: ;CHECK: vabs.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1) @@ -9,7 +9,7 @@ define <8 x i8> @vabss8(<8 x i8>* %A) nounwind { } define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { -;CHECK: vabss16: +;CHECK-LABEL: vabss16: ;CHECK: vabs.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1) @@ -17,7 +17,7 @@ define <4 x i16> @vabss16(<4 x i16>* %A) nounwind { } define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { -;CHECK: vabss32: +;CHECK-LABEL: vabss32: ;CHECK: vabs.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1) @@ -25,7 +25,7 @@ define <2 x i32> @vabss32(<2 x i32>* %A) nounwind { } define <2 x float> @vabsf32(<2 x float>* %A) nounwind { -;CHECK: vabsf32: +;CHECK-LABEL: vabsf32: ;CHECK: vabs.f32 %tmp1 = load <2 x float>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1) @@ -33,7 +33,7 @@ define <2 x float> @vabsf32(<2 x float>* %A) nounwind { } define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { -;CHECK: vabsQs8: +;CHECK-LABEL: vabsQs8: ;CHECK: vabs.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1) @@ -41,7 +41,7 @@ define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { -;CHECK: vabsQs16: +;CHECK-LABEL: vabsQs16: ;CHECK: vabs.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1) @@ -49,7 +49,7 @@ define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { -;CHECK: vabsQs32: +;CHECK-LABEL: vabsQs32: ;CHECK: vabs.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1) @@ -57,7 +57,7 @@ define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind { } define <4 x float> @vabsQf32(<4 x float>* %A) nounwind { -;CHECK: vabsQf32: +;CHECK-LABEL: vabsQf32: ;CHECK: vabs.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1) @@ -75,7 +75,7 @@ declare <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32>) nounwind readnone declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { -;CHECK: vqabss8: +;CHECK-LABEL: vqabss8: ;CHECK: vqabs.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1) @@ -83,7 +83,7 @@ define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind { } define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { -;CHECK: vqabss16: +;CHECK-LABEL: vqabss16: ;CHECK: vqabs.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1) @@ -91,7 +91,7 @@ define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind { } define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { -;CHECK: vqabss32: +;CHECK-LABEL: vqabss32: ;CHECK: vqabs.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1) @@ -99,7 +99,7 @@ define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind { } define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { -;CHECK: vqabsQs8: +;CHECK-LABEL: vqabsQs8: ;CHECK: vqabs.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1) @@ -107,7 +107,7 @@ define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { -;CHECK: vqabsQs16: +;CHECK-LABEL: vqabsQs16: ;CHECK: vqabs.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1) @@ -115,7 +115,7 @@ define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind { -;CHECK: vqabsQs32: +;CHECK-LABEL: vqabsQs32: ;CHECK: vqabs.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1) diff --git a/test/CodeGen/ARM/vadd.ll b/test/CodeGen/ARM/vadd.ll index a830e968ff..a1ad37b5f8 100644 --- a/test/CodeGen/ARM/vadd.ll +++ b/test/CodeGen/ARM/vadd.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vaddi8: +;CHECK-LABEL: vaddi8: ;CHECK: vadd.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vaddi16: +;CHECK-LABEL: vaddi16: ;CHECK: vadd.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vaddi32: +;CHECK-LABEL: vaddi32: ;CHECK: vadd.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vaddi64: +;CHECK-LABEL: vaddi64: ;CHECK: vadd.i64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vaddf32: +;CHECK-LABEL: vaddf32: ;CHECK: vadd.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -46,7 +46,7 @@ define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vaddQi8: +;CHECK-LABEL: vaddQi8: ;CHECK: vadd.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -55,7 +55,7 @@ define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vaddQi16: +;CHECK-LABEL: vaddQi16: ;CHECK: vadd.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -64,7 +64,7 @@ define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vaddQi32: +;CHECK-LABEL: vaddQi32: ;CHECK: vadd.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -73,7 +73,7 @@ define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vaddQi64: +;CHECK-LABEL: vaddQi64: ;CHECK: vadd.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -82,7 +82,7 @@ define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vaddQf32: +;CHECK-LABEL: vaddQf32: ;CHECK: vadd.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -91,7 +91,7 @@ define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vaddhni16: +;CHECK-LABEL: vaddhni16: ;CHECK: vaddhn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -100,7 +100,7 @@ define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vaddhni32: +;CHECK-LABEL: vaddhni32: ;CHECK: vaddhn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -109,7 +109,7 @@ define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vaddhni64: +;CHECK-LABEL: vaddhni64: ;CHECK: vaddhn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vraddhni16: +;CHECK-LABEL: vraddhni16: ;CHECK: vraddhn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -131,7 +131,7 @@ define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vraddhni32: +;CHECK-LABEL: vraddhni32: ;CHECK: vraddhn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -140,7 +140,7 @@ define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vraddhni64: +;CHECK-LABEL: vraddhni64: ;CHECK: vraddhn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vraddhn.v4i16(<4 x i32>, <4 x i32>) nounwind re declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vaddls8: +;CHECK-LABEL: vaddls8: ;CHECK: vaddl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -164,7 +164,7 @@ define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vaddls16: +;CHECK-LABEL: vaddls16: ;CHECK: vaddl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -175,7 +175,7 @@ define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vaddls32: +;CHECK-LABEL: vaddls32: ;CHECK: vaddl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -186,7 +186,7 @@ define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vaddlu8: +;CHECK-LABEL: vaddlu8: ;CHECK: vaddl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -197,7 +197,7 @@ define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vaddlu16: +;CHECK-LABEL: vaddlu16: ;CHECK: vaddl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -208,7 +208,7 @@ define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vaddlu32: +;CHECK-LABEL: vaddlu32: ;CHECK: vaddl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -219,7 +219,7 @@ define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vaddws8: +;CHECK-LABEL: vaddws8: ;CHECK: vaddw.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -229,7 +229,7 @@ define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vaddws16: +;CHECK-LABEL: vaddws16: ;CHECK: vaddw.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -239,7 +239,7 @@ define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vaddws32: +;CHECK-LABEL: vaddws32: ;CHECK: vaddw.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -249,7 +249,7 @@ define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vaddwu8: +;CHECK-LABEL: vaddwu8: ;CHECK: vaddw.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -259,7 +259,7 @@ define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vaddwu16: +;CHECK-LABEL: vaddwu16: ;CHECK: vaddw.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -269,7 +269,7 @@ define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vaddwu32: +;CHECK-LABEL: vaddwu32: ;CHECK: vaddw.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vbits.ll b/test/CodeGen/ARM/vbits.ll index 51f9bdf971..7b48441958 100644 --- a/test/CodeGen/ARM/vbits.ll +++ b/test/CodeGen/ARM/vbits.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: v_andi8: +;CHECK-LABEL: v_andi8: ;CHECK: vand %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: v_andi16: +;CHECK-LABEL: v_andi16: ;CHECK: vand %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: v_andi32: +;CHECK-LABEL: v_andi32: ;CHECK: vand %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: v_andi64: +;CHECK-LABEL: v_andi64: ;CHECK: vand %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: v_andQi8: +;CHECK-LABEL: v_andQi8: ;CHECK: vand %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -46,7 +46,7 @@ define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: v_andQi16: +;CHECK-LABEL: v_andQi16: ;CHECK: vand %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -55,7 +55,7 @@ define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: v_andQi32: +;CHECK-LABEL: v_andQi32: ;CHECK: vand %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -64,7 +64,7 @@ define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: v_andQi64: +;CHECK-LABEL: v_andQi64: ;CHECK: vand %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -73,7 +73,7 @@ define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: v_bici8: +;CHECK-LABEL: v_bici8: ;CHECK: vbic %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -83,7 +83,7 @@ define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: v_bici16: +;CHECK-LABEL: v_bici16: ;CHECK: vbic %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -93,7 +93,7 @@ define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: v_bici32: +;CHECK-LABEL: v_bici32: ;CHECK: vbic %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -103,7 +103,7 @@ define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: v_bici64: +;CHECK-LABEL: v_bici64: ;CHECK: vbic %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -113,7 +113,7 @@ define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: v_bicQi8: +;CHECK-LABEL: v_bicQi8: ;CHECK: vbic %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -123,7 +123,7 @@ define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: v_bicQi16: +;CHECK-LABEL: v_bicQi16: ;CHECK: vbic %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -133,7 +133,7 @@ define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: v_bicQi32: +;CHECK-LABEL: v_bicQi32: ;CHECK: vbic %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -143,7 +143,7 @@ define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: v_bicQi64: +;CHECK-LABEL: v_bicQi64: ;CHECK: vbic %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -153,7 +153,7 @@ define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: v_eori8: +;CHECK-LABEL: v_eori8: ;CHECK: veor %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -162,7 +162,7 @@ define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: v_eori16: +;CHECK-LABEL: v_eori16: ;CHECK: veor %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -171,7 +171,7 @@ define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: v_eori32: +;CHECK-LABEL: v_eori32: ;CHECK: veor %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -180,7 +180,7 @@ define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: v_eori64: +;CHECK-LABEL: v_eori64: ;CHECK: veor %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -189,7 +189,7 @@ define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: v_eorQi8: +;CHECK-LABEL: v_eorQi8: ;CHECK: veor %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -198,7 +198,7 @@ define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: v_eorQi16: +;CHECK-LABEL: v_eorQi16: ;CHECK: veor %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -207,7 +207,7 @@ define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: v_eorQi32: +;CHECK-LABEL: v_eorQi32: ;CHECK: veor %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -216,7 +216,7 @@ define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: v_eorQi64: +;CHECK-LABEL: v_eorQi64: ;CHECK: veor %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -225,7 +225,7 @@ define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { -;CHECK: v_mvni8: +;CHECK-LABEL: v_mvni8: ;CHECK: vmvn %tmp1 = load <8 x i8>* %A %tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > @@ -233,7 +233,7 @@ define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind { } define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { -;CHECK: v_mvni16: +;CHECK-LABEL: v_mvni16: ;CHECK: vmvn %tmp1 = load <4 x i16>* %A %tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 > @@ -241,7 +241,7 @@ define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind { } define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { -;CHECK: v_mvni32: +;CHECK-LABEL: v_mvni32: ;CHECK: vmvn %tmp1 = load <2 x i32>* %A %tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 > @@ -249,7 +249,7 @@ define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind { } define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { -;CHECK: v_mvni64: +;CHECK-LABEL: v_mvni64: ;CHECK: vmvn %tmp1 = load <1 x i64>* %A %tmp2 = xor <1 x i64> %tmp1, < i64 -1 > @@ -257,7 +257,7 @@ define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind { } define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { -;CHECK: v_mvnQi8: +;CHECK-LABEL: v_mvnQi8: ;CHECK: vmvn %tmp1 = load <16 x i8>* %A %tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > @@ -265,7 +265,7 @@ define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind { } define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { -;CHECK: v_mvnQi16: +;CHECK-LABEL: v_mvnQi16: ;CHECK: vmvn %tmp1 = load <8 x i16>* %A %tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > @@ -273,7 +273,7 @@ define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind { } define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { -;CHECK: v_mvnQi32: +;CHECK-LABEL: v_mvnQi32: ;CHECK: vmvn %tmp1 = load <4 x i32>* %A %tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 > @@ -281,7 +281,7 @@ define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind { } define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { -;CHECK: v_mvnQi64: +;CHECK-LABEL: v_mvnQi64: ;CHECK: vmvn %tmp1 = load <2 x i64>* %A %tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 > @@ -289,7 +289,7 @@ define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind { } define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: v_orri8: +;CHECK-LABEL: v_orri8: ;CHECK: vorr %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -298,7 +298,7 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: v_orri16: +;CHECK-LABEL: v_orri16: ;CHECK: vorr %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -307,7 +307,7 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: v_orri32: +;CHECK-LABEL: v_orri32: ;CHECK: vorr %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -316,7 +316,7 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: v_orri64: +;CHECK-LABEL: v_orri64: ;CHECK: vorr %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -325,7 +325,7 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: v_orrQi8: +;CHECK-LABEL: v_orrQi8: ;CHECK: vorr %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -334,7 +334,7 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: v_orrQi16: +;CHECK-LABEL: v_orrQi16: ;CHECK: vorr %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -343,7 +343,7 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: v_orrQi32: +;CHECK-LABEL: v_orrQi32: ;CHECK: vorr %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -352,7 +352,7 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: v_orrQi64: +;CHECK-LABEL: v_orrQi64: ;CHECK: vorr %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -361,7 +361,7 @@ define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: v_orni8: +;CHECK-LABEL: v_orni8: ;CHECK: vorn %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -371,7 +371,7 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: v_orni16: +;CHECK-LABEL: v_orni16: ;CHECK: vorn %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -381,7 +381,7 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: v_orni32: +;CHECK-LABEL: v_orni32: ;CHECK: vorn %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -391,7 +391,7 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: v_orni64: +;CHECK-LABEL: v_orni64: ;CHECK: vorn %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -401,7 +401,7 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: v_ornQi8: +;CHECK-LABEL: v_ornQi8: ;CHECK: vorn %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -411,7 +411,7 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: v_ornQi16: +;CHECK-LABEL: v_ornQi16: ;CHECK: vorn %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -421,7 +421,7 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: v_ornQi32: +;CHECK-LABEL: v_ornQi32: ;CHECK: vorn %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -431,7 +431,7 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: v_ornQi64: +;CHECK-LABEL: v_ornQi64: ;CHECK: vorn %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -441,7 +441,7 @@ define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vtsti8: +;CHECK-LABEL: vtsti8: ;CHECK: vtst.8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -452,7 +452,7 @@ define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vtsti16: +;CHECK-LABEL: vtsti16: ;CHECK: vtst.16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -463,7 +463,7 @@ define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vtsti32: +;CHECK-LABEL: vtsti32: ;CHECK: vtst.32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -474,7 +474,7 @@ define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vtstQi8: +;CHECK-LABEL: vtstQi8: ;CHECK: vtst.8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -485,7 +485,7 @@ define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vtstQi16: +;CHECK-LABEL: vtstQi16: ;CHECK: vtst.16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -496,7 +496,7 @@ define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vtstQi32: +;CHECK-LABEL: vtstQi32: ;CHECK: vtst.32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -507,7 +507,7 @@ define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind { -; CHECK: v_orrimm: +; CHECK-LABEL: v_orrimm: ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vorr @@ -527,7 +527,7 @@ define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind { } define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { -; CHECK: v_bicimm: +; CHECK-LABEL: v_bicimm: ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vbic @@ -537,7 +537,7 @@ define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind { } define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind { -; CHECK: v_bicimmQ: +; CHECK-LABEL: v_bicimmQ: ; CHECK-NOT: vmov ; CHECK-NOT: vmvn ; CHECK: vbic diff --git a/test/CodeGen/ARM/vbsl-constant.ll b/test/CodeGen/ARM/vbsl-constant.ll index ffda0a51bd..5e033fe2a6 100644 --- a/test/CodeGen/ARM/vbsl-constant.ll +++ b/test/CodeGen/ARM/vbsl-constant.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: v_bsli8: +;CHECK-LABEL: v_bsli8: ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl @@ -15,7 +15,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: v_bsli16: +;CHECK-LABEL: v_bsli16: ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl @@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: v_bsli32: +;CHECK-LABEL: v_bsli32: ;CHECK: vldr ;CHECK: vldr ;CHECK: vbsl @@ -43,7 +43,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { -;CHECK: v_bsli64: +;CHECK-LABEL: v_bsli64: ;CHECK: vldr ;CHECK: vldr ;CHECK: vldr @@ -58,7 +58,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind } define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { -;CHECK: v_bslQi8: +;CHECK-LABEL: v_bslQi8: ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl @@ -72,7 +72,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind } define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: v_bslQi16: +;CHECK-LABEL: v_bslQi16: ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl @@ -86,7 +86,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin } define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: v_bslQi32: +;CHECK-LABEL: v_bslQi32: ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vbsl @@ -100,7 +100,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin } define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { -;CHECK: v_bslQi64: +;CHECK-LABEL: v_bslQi64: ;CHECK: vld1.32 ;CHECK: vld1.32 ;CHECK: vld1.64 diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll index 56e40ebc9a..1e53e51f8b 100644 --- a/test/CodeGen/ARM/vbsl.ll +++ b/test/CodeGen/ARM/vbsl.ll @@ -3,7 +3,7 @@ ; rdar://12471808 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: v_bsli8: +;CHECK-LABEL: v_bsli8: ;CHECK: vbsl %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -16,7 +16,7 @@ define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: v_bsli16: +;CHECK-LABEL: v_bsli16: ;CHECK: vbsl %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -29,7 +29,7 @@ define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: v_bsli32: +;CHECK-LABEL: v_bsli32: ;CHECK: vbsl %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -42,7 +42,7 @@ define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind { -;CHECK: v_bsli64: +;CHECK-LABEL: v_bsli64: ;CHECK: vbsl %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -55,7 +55,7 @@ define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind } define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind { -;CHECK: v_bslQi8: +;CHECK-LABEL: v_bslQi8: ;CHECK: vbsl %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -68,7 +68,7 @@ define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind } define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: v_bslQi16: +;CHECK-LABEL: v_bslQi16: ;CHECK: vbsl %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -81,7 +81,7 @@ define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwin } define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: v_bslQi32: +;CHECK-LABEL: v_bslQi32: ;CHECK: vbsl %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -94,7 +94,7 @@ define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwin } define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind { -;CHECK: v_bslQi64: +;CHECK-LABEL: v_bslQi64: ;CHECK: vbsl %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -107,56 +107,56 @@ define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwin } define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp { -; CHECK: f1: +; CHECK-LABEL: f1: ; CHECK: vbsl %vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind ret <8 x i8> %vbsl.i } define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp { -; CHECK: f2: +; CHECK-LABEL: f2: ; CHECK: vbsl %vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind ret <4 x i16> %vbsl3.i } define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp { -; CHECK: f3: +; CHECK-LABEL: f3: ; CHECK: vbsl %vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind ret <2 x i32> %vbsl3.i } define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp { -; CHECK: f4: +; CHECK-LABEL: f4: ; CHECK: vbsl %vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind ret <2 x float> %vbsl4.i } define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp { -; CHECK: g1: +; CHECK-LABEL: g1: ; CHECK: vbsl %vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind ret <16 x i8> %vbsl.i } define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp { -; CHECK: g2: +; CHECK-LABEL: g2: ; CHECK: vbsl %vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind ret <8 x i16> %vbsl3.i } define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp { -; CHECK: g3: +; CHECK-LABEL: g3: ; CHECK: vbsl %vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind ret <4 x i32> %vbsl3.i } define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp { -; CHECK: g4: +; CHECK-LABEL: g4: ; CHECK: vbsl %vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind ret <4 x float> %vbsl4.i diff --git a/test/CodeGen/ARM/vceq.ll b/test/CodeGen/ARM/vceq.ll index 051c349a06..0a1f2ebe4f 100644 --- a/test/CodeGen/ARM/vceq.ll +++ b/test/CodeGen/ARM/vceq.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vceqi8: +;CHECK-LABEL: vceqi8: ;CHECK: vceq.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -11,7 +11,7 @@ define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vceqi16: +;CHECK-LABEL: vceqi16: ;CHECK: vceq.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -21,7 +21,7 @@ define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vceqi32: +;CHECK-LABEL: vceqi32: ;CHECK: vceq.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -31,7 +31,7 @@ define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vceqf32: +;CHECK-LABEL: vceqf32: ;CHECK: vceq.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -41,7 +41,7 @@ define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vceqQi8: +;CHECK-LABEL: vceqQi8: ;CHECK: vceq.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -51,7 +51,7 @@ define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vceqQi16: +;CHECK-LABEL: vceqQi16: ;CHECK: vceq.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -61,7 +61,7 @@ define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vceqQi32: +;CHECK-LABEL: vceqQi32: ;CHECK: vceq.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -71,7 +71,7 @@ define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vceqQf32: +;CHECK-LABEL: vceqQf32: ;CHECK: vceq.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -81,7 +81,7 @@ define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind { -;CHECK: vceqi8Z: +;CHECK-LABEL: vceqi8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vceq.i8 diff --git a/test/CodeGen/ARM/vcge.ll b/test/CodeGen/ARM/vcge.ll index bf5f0b9efb..13c895c188 100644 --- a/test/CodeGen/ARM/vcge.ll +++ b/test/CodeGen/ARM/vcge.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcges8: +;CHECK-LABEL: vcges8: ;CHECK: vcge.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -11,7 +11,7 @@ define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcges16: +;CHECK-LABEL: vcges16: ;CHECK: vcge.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -21,7 +21,7 @@ define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcges32: +;CHECK-LABEL: vcges32: ;CHECK: vcge.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -31,7 +31,7 @@ define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcgeu8: +;CHECK-LABEL: vcgeu8: ;CHECK: vcge.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -41,7 +41,7 @@ define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcgeu16: +;CHECK-LABEL: vcgeu16: ;CHECK: vcge.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -51,7 +51,7 @@ define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcgeu32: +;CHECK-LABEL: vcgeu32: ;CHECK: vcge.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -61,7 +61,7 @@ define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcgef32: +;CHECK-LABEL: vcgef32: ;CHECK: vcge.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -71,7 +71,7 @@ define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgeQs8: +;CHECK-LABEL: vcgeQs8: ;CHECK: vcge.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -81,7 +81,7 @@ define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgeQs16: +;CHECK-LABEL: vcgeQs16: ;CHECK: vcge.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgeQs32: +;CHECK-LABEL: vcgeQs32: ;CHECK: vcge.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -101,7 +101,7 @@ define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgeQu8: +;CHECK-LABEL: vcgeQu8: ;CHECK: vcge.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -111,7 +111,7 @@ define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgeQu16: +;CHECK-LABEL: vcgeQu16: ;CHECK: vcge.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -121,7 +121,7 @@ define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgeQu32: +;CHECK-LABEL: vcgeQu32: ;CHECK: vcge.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -131,7 +131,7 @@ define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vcgeQf32: +;CHECK-LABEL: vcgeQf32: ;CHECK: vcge.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -141,7 +141,7 @@ define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vacgef32: +;CHECK-LABEL: vacgef32: ;CHECK: vacge.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -150,7 +150,7 @@ define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vacgeQf32: +;CHECK-LABEL: vacgeQf32: ;CHECK: vacge.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -162,7 +162,7 @@ declare <2 x i32> @llvm.arm.neon.vacged(<2 x float>, <2 x float>) nounwind readn declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { -;CHECK: vcgei8Z: +;CHECK-LABEL: vcgei8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcge.s8 @@ -173,7 +173,7 @@ define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind { } define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind { -;CHECK: vclei8Z: +;CHECK-LABEL: vclei8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcle.s8 diff --git a/test/CodeGen/ARM/vcgt.ll b/test/CodeGen/ARM/vcgt.ll index 2243bac91f..056866fe99 100644 --- a/test/CodeGen/ARM/vcgt.ll +++ b/test/CodeGen/ARM/vcgt.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcgts8: +;CHECK-LABEL: vcgts8: ;CHECK: vcgt.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcgts16: +;CHECK-LABEL: vcgts16: ;CHECK: vcgt.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -22,7 +22,7 @@ define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcgts32: +;CHECK-LABEL: vcgts32: ;CHECK: vcgt.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -32,7 +32,7 @@ define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcgtu8: +;CHECK-LABEL: vcgtu8: ;CHECK: vcgt.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -42,7 +42,7 @@ define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcgtu16: +;CHECK-LABEL: vcgtu16: ;CHECK: vcgt.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -52,7 +52,7 @@ define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcgtu32: +;CHECK-LABEL: vcgtu32: ;CHECK: vcgt.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -62,7 +62,7 @@ define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcgtf32: +;CHECK-LABEL: vcgtf32: ;CHECK: vcgt.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -72,7 +72,7 @@ define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgtQs8: +;CHECK-LABEL: vcgtQs8: ;CHECK: vcgt.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgtQs16: +;CHECK-LABEL: vcgtQs16: ;CHECK: vcgt.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -92,7 +92,7 @@ define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgtQs32: +;CHECK-LABEL: vcgtQs32: ;CHECK: vcgt.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -102,7 +102,7 @@ define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcgtQu8: +;CHECK-LABEL: vcgtQu8: ;CHECK: vcgt.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -112,7 +112,7 @@ define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcgtQu16: +;CHECK-LABEL: vcgtQu16: ;CHECK: vcgt.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -122,7 +122,7 @@ define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcgtQu32: +;CHECK-LABEL: vcgtQu32: ;CHECK: vcgt.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -132,7 +132,7 @@ define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vcgtQf32: +;CHECK-LABEL: vcgtQf32: ;CHECK: vcgt.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -142,7 +142,7 @@ define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vacgtf32: +;CHECK-LABEL: vacgtf32: ;CHECK: vacgt.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -151,7 +151,7 @@ define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vacgtQf32: +;CHECK-LABEL: vacgtQf32: ;CHECK: vacgt.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -161,7 +161,7 @@ define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind { ; rdar://7923010 define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vcgt_zext: +;CHECK-LABEL: vcgt_zext: ;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1 ;CHECK: vcgt.f32 [[Q1:q[0-9]+]] ;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]] @@ -176,7 +176,7 @@ declare <2 x i32> @llvm.arm.neon.vacgtd(<2 x float>, <2 x float>) nounwind readn declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { -;CHECK: vcgti8Z: +;CHECK-LABEL: vcgti8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vcgt.s8 @@ -187,7 +187,7 @@ define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind { } define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind { -;CHECK: vclti8Z: +;CHECK-LABEL: vclti8Z: ;CHECK-NOT: vmov ;CHECK-NOT: vmvn ;CHECK: vclt.s8 diff --git a/test/CodeGen/ARM/vcnt.ll b/test/CodeGen/ARM/vcnt.ll index 9f55c24b40..0b53979983 100644 --- a/test/CodeGen/ARM/vcnt.ll +++ b/test/CodeGen/ARM/vcnt.ll @@ -2,7 +2,7 @@ ; NB: this tests vcnt, vclz, and vcls define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { -;CHECK: vcnt8: +;CHECK-LABEL: vcnt8: ;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1) @@ -10,7 +10,7 @@ define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind { } define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind { -;CHECK: vcntQ8: +;CHECK-LABEL: vcntQ8: ;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1) @@ -21,7 +21,7 @@ declare <8 x i8> @llvm.ctpop.v8i8(<8 x i8>) nounwind readnone declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { -;CHECK: vclz8: +;CHECK-LABEL: vclz8: ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0) @@ -29,7 +29,7 @@ define <8 x i8> @vclz8(<8 x i8>* %A) nounwind { } define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { -;CHECK: vclz16: +;CHECK-LABEL: vclz16: ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0) @@ -37,7 +37,7 @@ define <4 x i16> @vclz16(<4 x i16>* %A) nounwind { } define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { -;CHECK: vclz32: +;CHECK-LABEL: vclz32: ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}} %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0) @@ -45,7 +45,7 @@ define <2 x i32> @vclz32(<2 x i32>* %A) nounwind { } define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { -;CHECK: vclzQ8: +;CHECK-LABEL: vclzQ8: ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0) @@ -53,7 +53,7 @@ define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind { } define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { -;CHECK: vclzQ16: +;CHECK-LABEL: vclzQ16: ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0) @@ -61,7 +61,7 @@ define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind { } define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind { -;CHECK: vclzQ32: +;CHECK-LABEL: vclzQ32: ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}} %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0) @@ -77,7 +77,7 @@ declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16>, i1) nounwind readnone declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { -;CHECK: vclss8: +;CHECK-LABEL: vclss8: ;CHECK: vcls.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1) @@ -85,7 +85,7 @@ define <8 x i8> @vclss8(<8 x i8>* %A) nounwind { } define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { -;CHECK: vclss16: +;CHECK-LABEL: vclss16: ;CHECK: vcls.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1) @@ -93,7 +93,7 @@ define <4 x i16> @vclss16(<4 x i16>* %A) nounwind { } define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { -;CHECK: vclss32: +;CHECK-LABEL: vclss32: ;CHECK: vcls.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1) @@ -101,7 +101,7 @@ define <2 x i32> @vclss32(<2 x i32>* %A) nounwind { } define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { -;CHECK: vclsQs8: +;CHECK-LABEL: vclsQs8: ;CHECK: vcls.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1) @@ -109,7 +109,7 @@ define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { -;CHECK: vclsQs16: +;CHECK-LABEL: vclsQs16: ;CHECK: vcls.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1) @@ -117,7 +117,7 @@ define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind { -;CHECK: vclsQs32: +;CHECK-LABEL: vclsQs32: ;CHECK: vcls.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1) diff --git a/test/CodeGen/ARM/vcvt-cost.ll b/test/CodeGen/ARM/vcvt-cost.ll index 0d45c40b88..5e56a5b34c 100644 --- a/test/CodeGen/ARM/vcvt-cost.ll +++ b/test/CodeGen/ARM/vcvt-cost.ll @@ -4,7 +4,7 @@ ; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST %T0_5 = type <8 x i8> %T1_5 = type <8 x i32> -; CHECK: func_cvt5: +; CHECK-LABEL: func_cvt5: define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { ; CHECK: vmovl.s8 ; CHECK: vmovl.s16 @@ -20,7 +20,7 @@ define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) { ;; is improved the cost needs to change. %TA0_5 = type <8 x i8> %TA1_5 = type <8 x i32> -; CHECK: func_cvt1: +; CHECK-LABEL: func_cvt1: define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { ; CHECK: vmovl.u8 ; CHECK: vmovl.u16 @@ -35,7 +35,7 @@ define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) { %T0_51 = type <8 x i32> %T1_51 = type <8 x i8> -; CHECK: func_cvt51: +; CHECK-LABEL: func_cvt51: define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { ; CHECK: vmovn.i32 ; CHECK: vmovn.i32 @@ -50,7 +50,7 @@ define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) { %TT0_5 = type <16 x i8> %TT1_5 = type <16 x i32> -; CHECK: func_cvt52: +; CHECK-LABEL: func_cvt52: define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { ; CHECK: vmovl.s16 ; CHECK: vmovl.s16 @@ -67,7 +67,7 @@ define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) { ;; is improved the cost needs to change. %TTA0_5 = type <16 x i8> %TTA1_5 = type <16 x i32> -; CHECK: func_cvt12: +; CHECK-LABEL: func_cvt12: define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { ; CHECK: vmovl.u16 ; CHECK: vmovl.u16 @@ -83,7 +83,7 @@ define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) { %TT0_51 = type <16 x i32> %TT1_51 = type <16 x i8> -; CHECK: func_cvt512: +; CHECK-LABEL: func_cvt512: define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { ; CHECK: vmovn.i32 ; CHECK: vmovn.i32 @@ -99,7 +99,7 @@ define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) { ret void } -; CHECK: sext_v4i16_v4i64: +; CHECK-LABEL: sext_v4i16_v4i64: define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ; CHECK: vmovl.s32 ; CHECK: vmovl.s32 @@ -111,7 +111,7 @@ define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ret void } -; CHECK: zext_v4i16_v4i64: +; CHECK-LABEL: zext_v4i16_v4i64: define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ; CHECK: vmovl.u32 ; CHECK: vmovl.u32 @@ -123,7 +123,7 @@ define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) { ret void } -; CHECK: sext_v8i16_v8i64: +; CHECK-LABEL: sext_v8i16_v8i64: define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { ; CHECK: vmovl.s32 ; CHECK: vmovl.s32 @@ -137,7 +137,7 @@ define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { ret void } -; CHECK: zext_v8i16_v8i64: +; CHECK-LABEL: zext_v8i16_v8i64: define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) { ; CHECK: vmovl.u32 ; CHECK: vmovl.u32 diff --git a/test/CodeGen/ARM/vcvt.ll b/test/CodeGen/ARM/vcvt.ll index 9b315b1a48..4f17dc5594 100644 --- a/test/CodeGen/ARM/vcvt.ll +++ b/test/CodeGen/ARM/vcvt.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { -;CHECK: vcvt_f32tos32: +;CHECK-LABEL: vcvt_f32tos32: ;CHECK: vcvt.s32.f32 %tmp1 = load <2 x float>* %A %tmp2 = fptosi <2 x float> %tmp1 to <2 x i32> @@ -9,7 +9,7 @@ define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind { } define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { -;CHECK: vcvt_f32tou32: +;CHECK-LABEL: vcvt_f32tou32: ;CHECK: vcvt.u32.f32 %tmp1 = load <2 x float>* %A %tmp2 = fptoui <2 x float> %tmp1 to <2 x i32> @@ -17,7 +17,7 @@ define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind { } define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { -;CHECK: vcvt_s32tof32: +;CHECK-LABEL: vcvt_s32tof32: ;CHECK: vcvt.f32.s32 %tmp1 = load <2 x i32>* %A %tmp2 = sitofp <2 x i32> %tmp1 to <2 x float> @@ -25,7 +25,7 @@ define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind { } define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { -;CHECK: vcvt_u32tof32: +;CHECK-LABEL: vcvt_u32tof32: ;CHECK: vcvt.f32.u32 %tmp1 = load <2 x i32>* %A %tmp2 = uitofp <2 x i32> %tmp1 to <2 x float> @@ -33,7 +33,7 @@ define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind { } define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { -;CHECK: vcvtQ_f32tos32: +;CHECK-LABEL: vcvtQ_f32tos32: ;CHECK: vcvt.s32.f32 %tmp1 = load <4 x float>* %A %tmp2 = fptosi <4 x float> %tmp1 to <4 x i32> @@ -41,7 +41,7 @@ define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind { } define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { -;CHECK: vcvtQ_f32tou32: +;CHECK-LABEL: vcvtQ_f32tou32: ;CHECK: vcvt.u32.f32 %tmp1 = load <4 x float>* %A %tmp2 = fptoui <4 x float> %tmp1 to <4 x i32> @@ -49,7 +49,7 @@ define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind { } define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { -;CHECK: vcvtQ_s32tof32: +;CHECK-LABEL: vcvtQ_s32tof32: ;CHECK: vcvt.f32.s32 %tmp1 = load <4 x i32>* %A %tmp2 = sitofp <4 x i32> %tmp1 to <4 x float> @@ -57,7 +57,7 @@ define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind { } define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { -;CHECK: vcvtQ_u32tof32: +;CHECK-LABEL: vcvtQ_u32tof32: ;CHECK: vcvt.f32.u32 %tmp1 = load <4 x i32>* %A %tmp2 = uitofp <4 x i32> %tmp1 to <4 x float> @@ -65,7 +65,7 @@ define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind { } define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { -;CHECK: vcvt_n_f32tos32: +;CHECK-LABEL: vcvt_n_f32tos32: ;CHECK: vcvt.s32.f32 %tmp1 = load <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1) @@ -73,7 +73,7 @@ define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind { } define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { -;CHECK: vcvt_n_f32tou32: +;CHECK-LABEL: vcvt_n_f32tou32: ;CHECK: vcvt.u32.f32 %tmp1 = load <2 x float>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1) @@ -81,7 +81,7 @@ define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind { } define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { -;CHECK: vcvt_n_s32tof32: +;CHECK-LABEL: vcvt_n_s32tof32: ;CHECK: vcvt.f32.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) @@ -89,7 +89,7 @@ define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind { } define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind { -;CHECK: vcvt_n_u32tof32: +;CHECK-LABEL: vcvt_n_u32tof32: ;CHECK: vcvt.f32.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1) @@ -102,7 +102,7 @@ declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwi declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { -;CHECK: vcvtQ_n_f32tos32: +;CHECK-LABEL: vcvtQ_n_f32tos32: ;CHECK: vcvt.s32.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1) @@ -110,7 +110,7 @@ define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind { } define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { -;CHECK: vcvtQ_n_f32tou32: +;CHECK-LABEL: vcvtQ_n_f32tou32: ;CHECK: vcvt.u32.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1) @@ -118,7 +118,7 @@ define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind { } define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { -;CHECK: vcvtQ_n_s32tof32: +;CHECK-LABEL: vcvtQ_n_s32tof32: ;CHECK: vcvt.f32.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) @@ -126,7 +126,7 @@ define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind { } define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind { -;CHECK: vcvtQ_n_u32tof32: +;CHECK-LABEL: vcvtQ_n_u32tof32: ;CHECK: vcvt.f32.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1) @@ -139,7 +139,7 @@ declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwi declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { -;CHECK: vcvt_f16tof32: +;CHECK-LABEL: vcvt_f16tof32: ;CHECK: vcvt.f32.f16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1) @@ -147,7 +147,7 @@ define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind { } define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind { -;CHECK: vcvt_f32tof16: +;CHECK-LABEL: vcvt_f32tof16: ;CHECK: vcvt.f16.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1) @@ -159,7 +159,7 @@ declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone define <4 x i16> @fix_float_to_i16(<4 x float> %in) { -; CHECK: fix_float_to_i16: +; CHECK-LABEL: fix_float_to_i16: ; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1 ; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]] @@ -169,7 +169,7 @@ define <4 x i16> @fix_float_to_i16(<4 x float> %in) { } define <2 x i64> @fix_float_to_i64(<2 x float> %in) { -; CHECK: fix_float_to_i64: +; CHECK-LABEL: fix_float_to_i64: ; CHECK: bl ; CHECK: bl @@ -179,7 +179,7 @@ define <2 x i64> @fix_float_to_i64(<2 x float> %in) { } define <4 x i16> @fix_double_to_i16(<4 x double> %in) { -; CHECK: fix_double_to_i16: +; CHECK-LABEL: fix_double_to_i16: ; CHECK: vcvt.s32.f64 ; CHECK: vcvt.s32.f64 @@ -189,7 +189,7 @@ define <4 x i16> @fix_double_to_i16(<4 x double> %in) { } define <2 x i64> @fix_double_to_i64(<2 x double> %in) { -; CHECK: fix_double_to_i64: +; CHECK-LABEL: fix_double_to_i64: ; CHECK: bl ; CHECK: bl %scale = fmul <2 x double> %in, <double 2.0, double 2.0> diff --git a/test/CodeGen/ARM/vdiv_combine.ll b/test/CodeGen/ARM/vdiv_combine.ll index 3b43be46b4..96807f7280 100644 --- a/test/CodeGen/ARM/vdiv_combine.ll +++ b/test/CodeGen/ARM/vdiv_combine.ll @@ -97,7 +97,7 @@ entry: declare void @foo_float32x4_t(<4 x float>) define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) { -; CHECK: fix_unsigned_i16_to_float: +; CHECK-LABEL: fix_unsigned_i16_to_float: ; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}} ; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1 @@ -107,7 +107,7 @@ define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) { } define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) { -; CHECK: fix_signed_i16_to_float: +; CHECK-LABEL: fix_signed_i16_to_float: ; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}} ; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1 @@ -117,7 +117,7 @@ define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) { } define <2 x float> @fix_i64_to_float(<2 x i64> %in) { -; CHECK: fix_i64_to_float: +; CHECK-LABEL: fix_i64_to_float: ; CHECK: bl ; CHECK: bl @@ -127,7 +127,7 @@ define <2 x float> @fix_i64_to_float(<2 x i64> %in) { } define <2 x double> @fix_i64_to_double(<2 x i64> %in) { -; CHECK: fix_i64_to_double: +; CHECK-LABEL: fix_i64_to_double: ; CHECK: bl ; CHECK: bl diff --git a/test/CodeGen/ARM/vdup.ll b/test/CodeGen/ARM/vdup.ll index 2cf94d63ca..8805ef7fb8 100644 --- a/test/CodeGen/ARM/vdup.ll +++ b/test/CodeGen/ARM/vdup.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_dup8(i8 %A) nounwind { -;CHECK: v_dup8: +;CHECK-LABEL: v_dup8: ;CHECK: vdup.8 %tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0 %tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1 @@ -15,7 +15,7 @@ define <8 x i8> @v_dup8(i8 %A) nounwind { } define <4 x i16> @v_dup16(i16 %A) nounwind { -;CHECK: v_dup16: +;CHECK-LABEL: v_dup16: ;CHECK: vdup.16 %tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0 %tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1 @@ -25,7 +25,7 @@ define <4 x i16> @v_dup16(i16 %A) nounwind { } define <2 x i32> @v_dup32(i32 %A) nounwind { -;CHECK: v_dup32: +;CHECK-LABEL: v_dup32: ;CHECK: vdup.32 %tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0 %tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1 @@ -33,7 +33,7 @@ define <2 x i32> @v_dup32(i32 %A) nounwind { } define <2 x float> @v_dupfloat(float %A) nounwind { -;CHECK: v_dupfloat: +;CHECK-LABEL: v_dupfloat: ;CHECK: vdup.32 %tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0 %tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1 @@ -41,7 +41,7 @@ define <2 x float> @v_dupfloat(float %A) nounwind { } define <16 x i8> @v_dupQ8(i8 %A) nounwind { -;CHECK: v_dupQ8: +;CHECK-LABEL: v_dupQ8: ;CHECK: vdup.8 %tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0 %tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1 @@ -63,7 +63,7 @@ define <16 x i8> @v_dupQ8(i8 %A) nounwind { } define <8 x i16> @v_dupQ16(i16 %A) nounwind { -;CHECK: v_dupQ16: +;CHECK-LABEL: v_dupQ16: ;CHECK: vdup.16 %tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0 %tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1 @@ -77,7 +77,7 @@ define <8 x i16> @v_dupQ16(i16 %A) nounwind { } define <4 x i32> @v_dupQ32(i32 %A) nounwind { -;CHECK: v_dupQ32: +;CHECK-LABEL: v_dupQ32: ;CHECK: vdup.32 %tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0 %tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1 @@ -87,7 +87,7 @@ define <4 x i32> @v_dupQ32(i32 %A) nounwind { } define <4 x float> @v_dupQfloat(float %A) nounwind { -;CHECK: v_dupQfloat: +;CHECK-LABEL: v_dupQfloat: ;CHECK: vdup.32 %tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0 %tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1 @@ -99,7 +99,7 @@ define <4 x float> @v_dupQfloat(float %A) nounwind { ; Check to make sure it works with shuffles, too. define <8 x i8> @v_shuffledup8(i8 %A) nounwind { -;CHECK: v_shuffledup8: +;CHECK-LABEL: v_shuffledup8: ;CHECK: vdup.8 %tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0 %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer @@ -107,7 +107,7 @@ define <8 x i8> @v_shuffledup8(i8 %A) nounwind { } define <4 x i16> @v_shuffledup16(i16 %A) nounwind { -;CHECK: v_shuffledup16: +;CHECK-LABEL: v_shuffledup16: ;CHECK: vdup.16 %tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0 %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer @@ -115,7 +115,7 @@ define <4 x i16> @v_shuffledup16(i16 %A) nounwind { } define <2 x i32> @v_shuffledup32(i32 %A) nounwind { -;CHECK: v_shuffledup32: +;CHECK-LABEL: v_shuffledup32: ;CHECK: vdup.32 %tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0 %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer @@ -123,7 +123,7 @@ define <2 x i32> @v_shuffledup32(i32 %A) nounwind { } define <2 x float> @v_shuffledupfloat(float %A) nounwind { -;CHECK: v_shuffledupfloat: +;CHECK-LABEL: v_shuffledupfloat: ;CHECK: vdup.32 %tmp1 = insertelement <2 x float> undef, float %A, i32 0 %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer @@ -131,7 +131,7 @@ define <2 x float> @v_shuffledupfloat(float %A) nounwind { } define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind { -;CHECK: v_shuffledupQ8: +;CHECK-LABEL: v_shuffledupQ8: ;CHECK: vdup.8 %tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0 %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer @@ -139,7 +139,7 @@ define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind { } define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind { -;CHECK: v_shuffledupQ16: +;CHECK-LABEL: v_shuffledupQ16: ;CHECK: vdup.16 %tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0 %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer @@ -147,7 +147,7 @@ define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind { } define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind { -;CHECK: v_shuffledupQ32: +;CHECK-LABEL: v_shuffledupQ32: ;CHECK: vdup.32 %tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0 %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer @@ -155,7 +155,7 @@ define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind { } define <4 x float> @v_shuffledupQfloat(float %A) nounwind { -;CHECK: v_shuffledupQfloat: +;CHECK-LABEL: v_shuffledupQfloat: ;CHECK: vdup.32 %tmp1 = insertelement <4 x float> undef, float %A, i32 0 %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer @@ -163,7 +163,7 @@ define <4 x float> @v_shuffledupQfloat(float %A) nounwind { } define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { -;CHECK: vduplane8: +;CHECK-LABEL: vduplane8: ;CHECK: vdup.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > @@ -171,7 +171,7 @@ define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind { } define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { -;CHECK: vduplane16: +;CHECK-LABEL: vduplane16: ;CHECK: vdup.16 %tmp1 = load <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > @@ -179,7 +179,7 @@ define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind { } define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { -;CHECK: vduplane32: +;CHECK-LABEL: vduplane32: ;CHECK: vdup.32 %tmp1 = load <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > @@ -187,7 +187,7 @@ define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind { } define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { -;CHECK: vduplanefloat: +;CHECK-LABEL: vduplanefloat: ;CHECK: vdup.32 %tmp1 = load <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 > @@ -195,7 +195,7 @@ define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind { } define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { -;CHECK: vduplaneQ8: +;CHECK-LABEL: vduplaneQ8: ;CHECK: vdup.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > @@ -203,7 +203,7 @@ define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind { } define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { -;CHECK: vduplaneQ16: +;CHECK-LABEL: vduplaneQ16: ;CHECK: vdup.16 %tmp1 = load <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 > @@ -211,7 +211,7 @@ define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind { } define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { -;CHECK: vduplaneQ32: +;CHECK-LABEL: vduplaneQ32: ;CHECK: vdup.32 %tmp1 = load <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > @@ -219,7 +219,7 @@ define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind { } define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind { -;CHECK: vduplaneQfloat: +;CHECK-LABEL: vduplaneQfloat: ;CHECK: vdup.32 %tmp1 = load <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 > @@ -251,7 +251,7 @@ entry: } ; Radar 7373643 -;CHECK: redundantVdup: +;CHECK-LABEL: redundantVdup: ;CHECK: vmov.i8 ;CHECK-NOT: vdup.8 ;CHECK: vstr @@ -297,7 +297,7 @@ define <4 x i32> @tduplane(<4 x i32> %invec) { } define <2 x float> @check_f32(<4 x float> %v) nounwind { -;CHECK: check_f32: +;CHECK-LABEL: check_f32: ;CHECK: vdup.32 {{.*}}, d{{..}}[1] %x = extractelement <4 x float> %v, i32 3 %1 = insertelement <2 x float> undef, float %x, i32 0 @@ -306,7 +306,7 @@ define <2 x float> @check_f32(<4 x float> %v) nounwind { } define <2 x i32> @check_i32(<4 x i32> %v) nounwind { -;CHECK: check_i32: +;CHECK-LABEL: check_i32: ;CHECK: vdup.32 {{.*}}, d{{..}}[1] %x = extractelement <4 x i32> %v, i32 3 %1 = insertelement <2 x i32> undef, i32 %x, i32 0 @@ -315,7 +315,7 @@ define <2 x i32> @check_i32(<4 x i32> %v) nounwind { } define <4 x i16> @check_i16(<8 x i16> %v) nounwind { -;CHECK: check_i16: +;CHECK-LABEL: check_i16: ;CHECK: vdup.16 {{.*}}, d{{..}}[3] %x = extractelement <8 x i16> %v, i32 3 %1 = insertelement <4 x i16> undef, i16 %x, i32 0 @@ -324,7 +324,7 @@ define <4 x i16> @check_i16(<8 x i16> %v) nounwind { } define <8 x i8> @check_i8(<16 x i8> %v) nounwind { -;CHECK: check_i8: +;CHECK-LABEL: check_i8: ;CHECK: vdup.8 {{.*}}, d{{..}}[3] %x = extractelement <16 x i8> %v, i32 3 %1 = insertelement <8 x i8> undef, i8 %x, i32 0 diff --git a/test/CodeGen/ARM/vector-extend-narrow.ll b/test/CodeGen/ARM/vector-extend-narrow.ll index 22af797621..f3218969c7 100644 --- a/test/CodeGen/ARM/vector-extend-narrow.ll +++ b/test/CodeGen/ARM/vector-extend-narrow.ll @@ -1,6 +1,6 @@ ; RUN: llc -mtriple armv7 %s -o - | FileCheck %s -; CHECK: f: +; CHECK-LABEL: f: define float @f(<4 x i16>* nocapture %in) { ; CHECK: vldr ; CHECK: vmovl.u16 @@ -18,7 +18,7 @@ define float @f(<4 x i16>* nocapture %in) { ret float %7 } -; CHECK: g: +; CHECK-LABEL: g: define float @g(<4 x i8>* nocapture %in) { ; Note: vld1 here is reasonably important. Mixing VFP and NEON ; instructions is bad on some cores @@ -39,7 +39,7 @@ define float @g(<4 x i8>* nocapture %in) { ret float %7 } -; CHECK: h: +; CHECK-LABEL: h: define <4 x i8> @h(<4 x float> %v) { ; CHECK: vcvt.{{[us]}}32.f32 ; CHECK: vmovn.i32 @@ -47,7 +47,7 @@ define <4 x i8> @h(<4 x float> %v) { ret <4 x i8> %1 } -; CHECK: i: +; CHECK-LABEL: i: define <4 x i8> @i(<4 x i8>* %x) { ; Note: vld1 here is reasonably important. Mixing VFP and NEON ; instructions is bad on some cores @@ -62,7 +62,7 @@ define <4 x i8> @i(<4 x i8>* %x) { %2 = sdiv <4 x i8> zeroinitializer, %1 ret <4 x i8> %2 } -; CHECK: j: +; CHECK-LABEL: j: define <4 x i32> @j(<4 x i8>* %in) nounwind { ; CHECK: vld1 ; CHECK: vmovl.u8 diff --git a/test/CodeGen/ARM/vfcmp.ll b/test/CodeGen/ARM/vfcmp.ll index 6946d02637..a23db7be76 100644 --- a/test/CodeGen/ARM/vfcmp.ll +++ b/test/CodeGen/ARM/vfcmp.ll @@ -4,7 +4,7 @@ ; une is implemented with VCEQ/VMVN define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcunef32: +;CHECK-LABEL: vcunef32: ;CHECK: vceq.f32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x float>* %A @@ -16,7 +16,7 @@ define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind { ; olt is implemented with VCGT define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcoltf32: +;CHECK-LABEL: vcoltf32: ;CHECK: vcgt.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -27,7 +27,7 @@ define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ole is implemented with VCGE define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcolef32: +;CHECK-LABEL: vcolef32: ;CHECK: vcge.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -38,7 +38,7 @@ define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind { ; uge is implemented with VCGT/VMVN define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcugef32: +;CHECK-LABEL: vcugef32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x float>* %A @@ -50,7 +50,7 @@ define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ule is implemented with VCGT/VMVN define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vculef32: +;CHECK-LABEL: vculef32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x float>* %A @@ -62,7 +62,7 @@ define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ugt is implemented with VCGE/VMVN define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcugtf32: +;CHECK-LABEL: vcugtf32: ;CHECK: vcge.f32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x float>* %A @@ -74,7 +74,7 @@ define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ult is implemented with VCGE/VMVN define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcultf32: +;CHECK-LABEL: vcultf32: ;CHECK: vcge.f32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x float>* %A @@ -86,7 +86,7 @@ define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ueq is implemented with VCGT/VCGT/VORR/VMVN define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcueqf32: +;CHECK-LABEL: vcueqf32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr @@ -100,7 +100,7 @@ define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind { ; one is implemented with VCGT/VCGT/VORR define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vconef32: +;CHECK-LABEL: vconef32: ;CHECK: vcgt.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr @@ -113,7 +113,7 @@ define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind { ; uno is implemented with VCGT/VCGE/VORR/VMVN define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcunof32: +;CHECK-LABEL: vcunof32: ;CHECK: vcge.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr @@ -127,7 +127,7 @@ define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind { ; ord is implemented with VCGT/VCGE/VORR define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vcordf32: +;CHECK-LABEL: vcordf32: ;CHECK: vcge.f32 ;CHECK-NEXT: vcgt.f32 ;CHECK-NEXT: vorr diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index 806ec95df0..2518ee2278 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- target triple = "thumbv7-elf" define i32 @vget_lanes8(<8 x i8>* %A) nounwind { -;CHECK: vget_lanes8: +;CHECK-LABEL: vget_lanes8: ;CHECK: vmov.s8 %tmp1 = load <8 x i8>* %A %tmp2 = extractelement <8 x i8> %tmp1, i32 1 @@ -12,7 +12,7 @@ define i32 @vget_lanes8(<8 x i8>* %A) nounwind { } define i32 @vget_lanes16(<4 x i16>* %A) nounwind { -;CHECK: vget_lanes16: +;CHECK-LABEL: vget_lanes16: ;CHECK: vmov.s16 %tmp1 = load <4 x i16>* %A %tmp2 = extractelement <4 x i16> %tmp1, i32 1 @@ -21,7 +21,7 @@ define i32 @vget_lanes16(<4 x i16>* %A) nounwind { } define i32 @vget_laneu8(<8 x i8>* %A) nounwind { -;CHECK: vget_laneu8: +;CHECK-LABEL: vget_laneu8: ;CHECK: vmov.u8 %tmp1 = load <8 x i8>* %A %tmp2 = extractelement <8 x i8> %tmp1, i32 1 @@ -30,7 +30,7 @@ define i32 @vget_laneu8(<8 x i8>* %A) nounwind { } define i32 @vget_laneu16(<4 x i16>* %A) nounwind { -;CHECK: vget_laneu16: +;CHECK-LABEL: vget_laneu16: ;CHECK: vmov.u16 %tmp1 = load <4 x i16>* %A %tmp2 = extractelement <4 x i16> %tmp1, i32 1 @@ -40,7 +40,7 @@ define i32 @vget_laneu16(<4 x i16>* %A) nounwind { ; Do a vector add to keep the extraction from being done directly from memory. define i32 @vget_lanei32(<2 x i32>* %A) nounwind { -;CHECK: vget_lanei32: +;CHECK-LABEL: vget_lanei32: ;CHECK: vmov.32 %tmp1 = load <2 x i32>* %A %tmp2 = add <2 x i32> %tmp1, %tmp1 @@ -49,7 +49,7 @@ define i32 @vget_lanei32(<2 x i32>* %A) nounwind { } define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind { -;CHECK: vgetQ_lanes8: +;CHECK-LABEL: vgetQ_lanes8: ;CHECK: vmov.s8 %tmp1 = load <16 x i8>* %A %tmp2 = extractelement <16 x i8> %tmp1, i32 1 @@ -58,7 +58,7 @@ define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind { } define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind { -;CHECK: vgetQ_lanes16: +;CHECK-LABEL: vgetQ_lanes16: ;CHECK: vmov.s16 %tmp1 = load <8 x i16>* %A %tmp2 = extractelement <8 x i16> %tmp1, i32 1 @@ -67,7 +67,7 @@ define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind { } define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind { -;CHECK: vgetQ_laneu8: +;CHECK-LABEL: vgetQ_laneu8: ;CHECK: vmov.u8 %tmp1 = load <16 x i8>* %A %tmp2 = extractelement <16 x i8> %tmp1, i32 1 @@ -76,7 +76,7 @@ define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind { } define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind { -;CHECK: vgetQ_laneu16: +;CHECK-LABEL: vgetQ_laneu16: ;CHECK: vmov.u16 %tmp1 = load <8 x i16>* %A %tmp2 = extractelement <8 x i16> %tmp1, i32 1 @@ -86,7 +86,7 @@ define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind { ; Do a vector add to keep the extraction from being done directly from memory. define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind { -;CHECK: vgetQ_lanei32: +;CHECK-LABEL: vgetQ_lanei32: ;CHECK: vmov.32 %tmp1 = load <4 x i32>* %A %tmp2 = add <4 x i32> %tmp1, %tmp1 @@ -159,7 +159,7 @@ return: ; preds = %entry } define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind { -;CHECK: vset_lane8: +;CHECK-LABEL: vset_lane8: ;CHECK: vmov.8 %tmp1 = load <8 x i8>* %A %tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1 @@ -167,7 +167,7 @@ define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind { } define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind { -;CHECK: vset_lane16: +;CHECK-LABEL: vset_lane16: ;CHECK: vmov.16 %tmp1 = load <4 x i16>* %A %tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1 @@ -175,7 +175,7 @@ define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind { } define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind { -;CHECK: vset_lane32: +;CHECK-LABEL: vset_lane32: ;CHECK: vmov.32 %tmp1 = load <2 x i32>* %A %tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1 @@ -183,7 +183,7 @@ define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind { } define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind { -;CHECK: vsetQ_lane8: +;CHECK-LABEL: vsetQ_lane8: ;CHECK: vmov.8 %tmp1 = load <16 x i8>* %A %tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1 @@ -191,7 +191,7 @@ define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind { } define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind { -;CHECK: vsetQ_lane16: +;CHECK-LABEL: vsetQ_lane16: ;CHECK: vmov.16 %tmp1 = load <8 x i16>* %A %tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1 @@ -199,7 +199,7 @@ define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind { } define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { -;CHECK: vsetQ_lane32: +;CHECK-LABEL: vsetQ_lane32: ;CHECK: vmov.32 d{{.*}}[1], r1 %tmp1 = load <4 x i32>* %A %tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1 diff --git a/test/CodeGen/ARM/vhadd.ll b/test/CodeGen/ARM/vhadd.ll index 379e062838..9c2ed579c9 100644 --- a/test/CodeGen/ARM/vhadd.ll +++ b/test/CodeGen/ARM/vhadd.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vhadds8: +;CHECK-LABEL: vhadds8: ;CHECK: vhadd.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vhadds16: +;CHECK-LABEL: vhadds16: ;CHECK: vhadd.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vhadds32: +;CHECK-LABEL: vhadds32: ;CHECK: vhadd.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vhaddu8: +;CHECK-LABEL: vhaddu8: ;CHECK: vhadd.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vhaddu16: +;CHECK-LABEL: vhaddu16: ;CHECK: vhadd.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vhaddu32: +;CHECK-LABEL: vhaddu32: ;CHECK: vhadd.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vhaddQs8: +;CHECK-LABEL: vhaddQs8: ;CHECK: vhadd.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -64,7 +64,7 @@ define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vhaddQs16: +;CHECK-LABEL: vhaddQs16: ;CHECK: vhadd.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -73,7 +73,7 @@ define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vhaddQs32: +;CHECK-LABEL: vhaddQs32: ;CHECK: vhadd.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -82,7 +82,7 @@ define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vhaddQu8: +;CHECK-LABEL: vhaddQu8: ;CHECK: vhadd.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -91,7 +91,7 @@ define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vhaddQu16: +;CHECK-LABEL: vhaddQu16: ;CHECK: vhadd.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -100,7 +100,7 @@ define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vhaddQu32: +;CHECK-LABEL: vhaddQu32: ;CHECK: vhadd.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -125,7 +125,7 @@ declare <8 x i16> @llvm.arm.neon.vhaddu.v8i16(<8 x i16>, <8 x i16>) nounwind rea declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrhadds8: +;CHECK-LABEL: vrhadds8: ;CHECK: vrhadd.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -134,7 +134,7 @@ define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrhadds16: +;CHECK-LABEL: vrhadds16: ;CHECK: vrhadd.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -143,7 +143,7 @@ define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrhadds32: +;CHECK-LABEL: vrhadds32: ;CHECK: vrhadd.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -152,7 +152,7 @@ define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrhaddu8: +;CHECK-LABEL: vrhaddu8: ;CHECK: vrhadd.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -161,7 +161,7 @@ define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrhaddu16: +;CHECK-LABEL: vrhaddu16: ;CHECK: vrhadd.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -170,7 +170,7 @@ define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrhaddu32: +;CHECK-LABEL: vrhaddu32: ;CHECK: vrhadd.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -179,7 +179,7 @@ define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrhaddQs8: +;CHECK-LABEL: vrhaddQs8: ;CHECK: vrhadd.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -188,7 +188,7 @@ define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrhaddQs16: +;CHECK-LABEL: vrhaddQs16: ;CHECK: vrhadd.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -197,7 +197,7 @@ define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrhaddQs32: +;CHECK-LABEL: vrhaddQs32: ;CHECK: vrhadd.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -206,7 +206,7 @@ define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrhaddQu8: +;CHECK-LABEL: vrhaddQu8: ;CHECK: vrhadd.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -215,7 +215,7 @@ define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrhaddQu16: +;CHECK-LABEL: vrhaddQu16: ;CHECK: vrhadd.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -224,7 +224,7 @@ define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrhaddQu32: +;CHECK-LABEL: vrhaddQu32: ;CHECK: vrhadd.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B diff --git a/test/CodeGen/ARM/vhsub.ll b/test/CodeGen/ARM/vhsub.ll index 0f0d0279a5..4bc2e87ab5 100644 --- a/test/CodeGen/ARM/vhsub.ll +++ b/test/CodeGen/ARM/vhsub.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vhsubs8: +;CHECK-LABEL: vhsubs8: ;CHECK: vhsub.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vhsubs16: +;CHECK-LABEL: vhsubs16: ;CHECK: vhsub.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vhsubs32: +;CHECK-LABEL: vhsubs32: ;CHECK: vhsub.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vhsubu8: +;CHECK-LABEL: vhsubu8: ;CHECK: vhsub.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vhsubu16: +;CHECK-LABEL: vhsubu16: ;CHECK: vhsub.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vhsubu32: +;CHECK-LABEL: vhsubu32: ;CHECK: vhsub.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vhsubQs8: +;CHECK-LABEL: vhsubQs8: ;CHECK: vhsub.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -64,7 +64,7 @@ define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vhsubQs16: +;CHECK-LABEL: vhsubQs16: ;CHECK: vhsub.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -73,7 +73,7 @@ define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vhsubQs32: +;CHECK-LABEL: vhsubQs32: ;CHECK: vhsub.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -82,7 +82,7 @@ define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vhsubQu8: +;CHECK-LABEL: vhsubQu8: ;CHECK: vhsub.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -91,7 +91,7 @@ define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vhsubQu16: +;CHECK-LABEL: vhsubQu16: ;CHECK: vhsub.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -100,7 +100,7 @@ define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vhsubQu32: +;CHECK-LABEL: vhsubQu32: ;CHECK: vhsub.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B diff --git a/test/CodeGen/ARM/vicmp.ll b/test/CodeGen/ARM/vicmp.ll index 2d8cb893bd..0a8f103102 100644 --- a/test/CodeGen/ARM/vicmp.ll +++ b/test/CodeGen/ARM/vicmp.ll @@ -7,7 +7,7 @@ ; the other operations. define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vcnei8: +;CHECK-LABEL: vcnei8: ;CHECK: vceq.i8 ;CHECK-NEXT: vmvn %tmp1 = load <8 x i8>* %A @@ -18,7 +18,7 @@ define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcnei16: +;CHECK-LABEL: vcnei16: ;CHECK: vceq.i16 ;CHECK-NEXT: vmvn %tmp1 = load <4 x i16>* %A @@ -29,7 +29,7 @@ define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vcnei32: +;CHECK-LABEL: vcnei32: ;CHECK: vceq.i32 ;CHECK-NEXT: vmvn %tmp1 = load <2 x i32>* %A @@ -40,7 +40,7 @@ define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcneQi8: +;CHECK-LABEL: vcneQi8: ;CHECK: vceq.i8 ;CHECK-NEXT: vmvn %tmp1 = load <16 x i8>* %A @@ -51,7 +51,7 @@ define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vcneQi16: +;CHECK-LABEL: vcneQi16: ;CHECK: vceq.i16 ;CHECK-NEXT: vmvn %tmp1 = load <8 x i16>* %A @@ -62,7 +62,7 @@ define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcneQi32: +;CHECK-LABEL: vcneQi32: ;CHECK: vceq.i32 ;CHECK-NEXT: vmvn %tmp1 = load <4 x i32>* %A @@ -73,7 +73,7 @@ define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vcltQs8: +;CHECK-LABEL: vcltQs8: ;CHECK: vcgt.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -83,7 +83,7 @@ define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcles16: +;CHECK-LABEL: vcles16: ;CHECK: vcge.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -93,7 +93,7 @@ define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vcltu16: +;CHECK-LABEL: vcltu16: ;CHECK: vcgt.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -103,7 +103,7 @@ define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vcleQu32: +;CHECK-LABEL: vcleQu32: ;CHECK: vcge.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B diff --git a/test/CodeGen/ARM/vld1.ll b/test/CodeGen/ARM/vld1.ll index 994f05dacb..444d0d5b5e 100644 --- a/test/CodeGen/ARM/vld1.ll +++ b/test/CodeGen/ARM/vld1.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vld1i8(i8* %A) nounwind { -;CHECK: vld1i8: +;CHECK-LABEL: vld1i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld1.8 {d16}, [r0:64] %tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16) @@ -10,7 +10,7 @@ define <8 x i8> @vld1i8(i8* %A) nounwind { } define <4 x i16> @vld1i16(i16* %A) nounwind { -;CHECK: vld1i16: +;CHECK-LABEL: vld1i16: ;CHECK: vld1.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1) @@ -19,7 +19,7 @@ define <4 x i16> @vld1i16(i16* %A) nounwind { ;Check for a post-increment updating load. define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { -;CHECK: vld1i16_update: +;CHECK-LABEL: vld1i16_update: ;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]! %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* @@ -30,7 +30,7 @@ define <4 x i16> @vld1i16_update(i16** %ptr) nounwind { } define <2 x i32> @vld1i32(i32* %A) nounwind { -;CHECK: vld1i32: +;CHECK-LABEL: vld1i32: ;CHECK: vld1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1) @@ -39,7 +39,7 @@ define <2 x i32> @vld1i32(i32* %A) nounwind { ;Check for a post-increment updating load with register increment. define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { -;CHECK: vld1i32_update: +;CHECK-LABEL: vld1i32_update: ;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* @@ -50,7 +50,7 @@ define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind { } define <2 x float> @vld1f(float* %A) nounwind { -;CHECK: vld1f: +;CHECK-LABEL: vld1f: ;CHECK: vld1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1) @@ -58,7 +58,7 @@ define <2 x float> @vld1f(float* %A) nounwind { } define <1 x i64> @vld1i64(i64* %A) nounwind { -;CHECK: vld1i64: +;CHECK-LABEL: vld1i64: ;CHECK: vld1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1) @@ -66,7 +66,7 @@ define <1 x i64> @vld1i64(i64* %A) nounwind { } define <16 x i8> @vld1Qi8(i8* %A) nounwind { -;CHECK: vld1Qi8: +;CHECK-LABEL: vld1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.8 {d16, d17}, [r0:64] %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) @@ -75,7 +75,7 @@ define <16 x i8> @vld1Qi8(i8* %A) nounwind { ;Check for a post-increment updating load. define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { -;CHECK: vld1Qi8_update: +;CHECK-LABEL: vld1Qi8_update: ;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]! %A = load i8** %ptr %tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8) @@ -85,7 +85,7 @@ define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind { } define <8 x i16> @vld1Qi16(i16* %A) nounwind { -;CHECK: vld1Qi16: +;CHECK-LABEL: vld1Qi16: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -94,7 +94,7 @@ define <8 x i16> @vld1Qi16(i16* %A) nounwind { } define <4 x i32> @vld1Qi32(i32* %A) nounwind { -;CHECK: vld1Qi32: +;CHECK-LABEL: vld1Qi32: ;CHECK: vld1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1) @@ -102,7 +102,7 @@ define <4 x i32> @vld1Qi32(i32* %A) nounwind { } define <4 x float> @vld1Qf(float* %A) nounwind { -;CHECK: vld1Qf: +;CHECK-LABEL: vld1Qf: ;CHECK: vld1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1) @@ -110,7 +110,7 @@ define <4 x float> @vld1Qf(float* %A) nounwind { } define <2 x i64> @vld1Qi64(i64* %A) nounwind { -;CHECK: vld1Qi64: +;CHECK-LABEL: vld1Qi64: ;CHECK: vld1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1) diff --git a/test/CodeGen/ARM/vld2.ll b/test/CodeGen/ARM/vld2.ll index caa016e929..fddafeab91 100644 --- a/test/CodeGen/ARM/vld2.ll +++ b/test/CodeGen/ARM/vld2.ll @@ -12,7 +12,7 @@ %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> } define <8 x i8> @vld2i8(i8* %A) nounwind { -;CHECK: vld2i8: +;CHECK-LABEL: vld2i8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld2.8 {d16, d17}, [r0:64] %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8) @@ -23,7 +23,7 @@ define <8 x i8> @vld2i8(i8* %A) nounwind { } define <4 x i16> @vld2i16(i16* %A) nounwind { -;CHECK: vld2i16: +;CHECK-LABEL: vld2i16: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -35,7 +35,7 @@ define <4 x i16> @vld2i16(i16* %A) nounwind { } define <2 x i32> @vld2i32(i32* %A) nounwind { -;CHECK: vld2i32: +;CHECK-LABEL: vld2i32: ;CHECK: vld2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1) @@ -46,7 +46,7 @@ define <2 x i32> @vld2i32(i32* %A) nounwind { } define <2 x float> @vld2f(float* %A) nounwind { -;CHECK: vld2f: +;CHECK-LABEL: vld2f: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1) @@ -58,7 +58,7 @@ define <2 x float> @vld2f(float* %A) nounwind { ;Check for a post-increment updating load. define <2 x float> @vld2f_update(float** %ptr) nounwind { -;CHECK: vld2f_update: +;CHECK-LABEL: vld2f_update: ;CHECK: vld2.32 {d16, d17}, [r1]! %A = load float** %ptr %tmp0 = bitcast float* %A to i8* @@ -72,7 +72,7 @@ define <2 x float> @vld2f_update(float** %ptr) nounwind { } define <1 x i64> @vld2i64(i64* %A) nounwind { -;CHECK: vld2i64: +;CHECK-LABEL: vld2i64: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vld1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* @@ -84,7 +84,7 @@ define <1 x i64> @vld2i64(i64* %A) nounwind { } define <16 x i8> @vld2Qi8(i8* %A) nounwind { -;CHECK: vld2Qi8: +;CHECK-LABEL: vld2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8) @@ -96,7 +96,7 @@ define <16 x i8> @vld2Qi8(i8* %A) nounwind { ;Check for a post-increment updating load with register increment. define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { -;CHECK: vld2Qi8_update: +;CHECK-LABEL: vld2Qi8_update: ;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8** %ptr %tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16) @@ -109,7 +109,7 @@ define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind { } define <8 x i16> @vld2Qi16(i16* %A) nounwind { -;CHECK: vld2Qi16: +;CHECK-LABEL: vld2Qi16: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -121,7 +121,7 @@ define <8 x i16> @vld2Qi16(i16* %A) nounwind { } define <4 x i32> @vld2Qi32(i32* %A) nounwind { -;CHECK: vld2Qi32: +;CHECK-LABEL: vld2Qi32: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* @@ -133,7 +133,7 @@ define <4 x i32> @vld2Qi32(i32* %A) nounwind { } define <4 x float> @vld2Qf(float* %A) nounwind { -;CHECK: vld2Qf: +;CHECK-LABEL: vld2Qf: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1) diff --git a/test/CodeGen/ARM/vld3.ll b/test/CodeGen/ARM/vld3.ll index ad63e1f716..400541fb90 100644 --- a/test/CodeGen/ARM/vld3.ll +++ b/test/CodeGen/ARM/vld3.ll @@ -13,7 +13,7 @@ %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> } define <8 x i8> @vld3i8(i8* %A) nounwind { -;CHECK: vld3i8: +;CHECK-LABEL: vld3i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld3.8 {d16, d17, d18}, [r0:64] %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32) @@ -24,7 +24,7 @@ define <8 x i8> @vld3i8(i8* %A) nounwind { } define <4 x i16> @vld3i16(i16* %A) nounwind { -;CHECK: vld3i16: +;CHECK-LABEL: vld3i16: ;CHECK: vld3.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1) @@ -36,7 +36,7 @@ define <4 x i16> @vld3i16(i16* %A) nounwind { ;Check for a post-increment updating load with register increment. define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { -;CHECK: vld3i16_update: +;CHECK-LABEL: vld3i16_update: ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* @@ -50,7 +50,7 @@ define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind { } define <2 x i32> @vld3i32(i32* %A) nounwind { -;CHECK: vld3i32: +;CHECK-LABEL: vld3i32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1) @@ -61,7 +61,7 @@ define <2 x i32> @vld3i32(i32* %A) nounwind { } define <2 x float> @vld3f(float* %A) nounwind { -;CHECK: vld3f: +;CHECK-LABEL: vld3f: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1) @@ -72,7 +72,7 @@ define <2 x float> @vld3f(float* %A) nounwind { } define <1 x i64> @vld3i64(i64* %A) nounwind { -;CHECK: vld3i64: +;CHECK-LABEL: vld3i64: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld1.64 {d16, d17, d18}, [r0:64] %tmp0 = bitcast i64* %A to i8* @@ -84,7 +84,7 @@ define <1 x i64> @vld3i64(i64* %A) nounwind { } define <16 x i8> @vld3Qi8(i8* %A) nounwind { -;CHECK: vld3Qi8: +;CHECK-LABEL: vld3Qi8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld3.8 {d16, d18, d20}, [r0:64]! ;CHECK: vld3.8 {d17, d19, d21}, [r0:64] @@ -96,7 +96,7 @@ define <16 x i8> @vld3Qi8(i8* %A) nounwind { } define <8 x i16> @vld3Qi16(i16* %A) nounwind { -;CHECK: vld3Qi16: +;CHECK-LABEL: vld3Qi16: ;CHECK: vld3.16 ;CHECK: vld3.16 %tmp0 = bitcast i16* %A to i8* @@ -108,7 +108,7 @@ define <8 x i16> @vld3Qi16(i16* %A) nounwind { } define <4 x i32> @vld3Qi32(i32* %A) nounwind { -;CHECK: vld3Qi32: +;CHECK-LABEL: vld3Qi32: ;CHECK: vld3.32 ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* @@ -121,7 +121,7 @@ define <4 x i32> @vld3Qi32(i32* %A) nounwind { ;Check for a post-increment updating load. define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { -;CHECK: vld3Qi32_update: +;CHECK-LABEL: vld3Qi32_update: ;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]! ;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]! %A = load i32** %ptr @@ -136,7 +136,7 @@ define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind { } define <4 x float> @vld3Qf(float* %A) nounwind { -;CHECK: vld3Qf: +;CHECK-LABEL: vld3Qf: ;CHECK: vld3.32 ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* diff --git a/test/CodeGen/ARM/vld4.ll b/test/CodeGen/ARM/vld4.ll index 9ee5fe46ee..f7376b503a 100644 --- a/test/CodeGen/ARM/vld4.ll +++ b/test/CodeGen/ARM/vld4.ll @@ -12,7 +12,7 @@ %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> } define <8 x i8> @vld4i8(i8* %A) nounwind { -;CHECK: vld4i8: +;CHECK-LABEL: vld4i8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8) @@ -24,7 +24,7 @@ define <8 x i8> @vld4i8(i8* %A) nounwind { ;Check for a post-increment updating load with register increment. define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { -;CHECK: vld4i8_update: +;CHECK-LABEL: vld4i8_update: ;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1 %A = load i8** %ptr %tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16) @@ -37,7 +37,7 @@ define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind { } define <4 x i16> @vld4i16(i16* %A) nounwind { -;CHECK: vld4i16: +;CHECK-LABEL: vld4i16: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -49,7 +49,7 @@ define <4 x i16> @vld4i16(i16* %A) nounwind { } define <2 x i32> @vld4i32(i32* %A) nounwind { -;CHECK: vld4i32: +;CHECK-LABEL: vld4i32: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* @@ -61,7 +61,7 @@ define <2 x i32> @vld4i32(i32* %A) nounwind { } define <2 x float> @vld4f(float* %A) nounwind { -;CHECK: vld4f: +;CHECK-LABEL: vld4f: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1) @@ -72,7 +72,7 @@ define <2 x float> @vld4f(float* %A) nounwind { } define <1 x i64> @vld4i64(i64* %A) nounwind { -;CHECK: vld4i64: +;CHECK-LABEL: vld4i64: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* @@ -84,7 +84,7 @@ define <1 x i64> @vld4i64(i64* %A) nounwind { } define <16 x i8> @vld4Qi8(i8* %A) nounwind { -;CHECK: vld4Qi8: +;CHECK-LABEL: vld4Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]! ;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256] @@ -96,7 +96,7 @@ define <16 x i8> @vld4Qi8(i8* %A) nounwind { } define <8 x i16> @vld4Qi16(i16* %A) nounwind { -;CHECK: vld4Qi16: +;CHECK-LABEL: vld4Qi16: ;Check for no alignment specifier. ;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]! ;CHECK: vld4.16 {d17, d19, d21, d23}, [r0] @@ -110,7 +110,7 @@ define <8 x i16> @vld4Qi16(i16* %A) nounwind { ;Check for a post-increment updating load. define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { -;CHECK: vld4Qi16_update: +;CHECK-LABEL: vld4Qi16_update: ;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]! ;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]! %A = load i16** %ptr @@ -125,7 +125,7 @@ define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind { } define <4 x i32> @vld4Qi32(i32* %A) nounwind { -;CHECK: vld4Qi32: +;CHECK-LABEL: vld4Qi32: ;CHECK: vld4.32 ;CHECK: vld4.32 %tmp0 = bitcast i32* %A to i8* @@ -137,7 +137,7 @@ define <4 x i32> @vld4Qi32(i32* %A) nounwind { } define <4 x float> @vld4Qf(float* %A) nounwind { -;CHECK: vld4Qf: +;CHECK-LABEL: vld4Qf: ;CHECK: vld4.32 ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* diff --git a/test/CodeGen/ARM/vlddup.ll b/test/CodeGen/ARM/vlddup.ll index 7c7319c090..5509f3e0a0 100644 --- a/test/CodeGen/ARM/vlddup.ll +++ b/test/CodeGen/ARM/vlddup.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vld1dupi8(i8* %A) nounwind { -;CHECK: vld1dupi8: +;CHECK-LABEL: vld1dupi8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[]}, [r0] %tmp1 = load i8* %A, align 8 @@ -11,7 +11,7 @@ define <8 x i8> @vld1dupi8(i8* %A) nounwind { } define <4 x i16> @vld1dupi16(i16* %A) nounwind { -;CHECK: vld1dupi16: +;CHECK-LABEL: vld1dupi16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld1.16 {d16[]}, [r0:16] %tmp1 = load i16* %A, align 8 @@ -21,7 +21,7 @@ define <4 x i16> @vld1dupi16(i16* %A) nounwind { } define <2 x i32> @vld1dupi32(i32* %A) nounwind { -;CHECK: vld1dupi32: +;CHECK-LABEL: vld1dupi32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld1.32 {d16[]}, [r0:32] %tmp1 = load i32* %A, align 8 @@ -31,7 +31,7 @@ define <2 x i32> @vld1dupi32(i32* %A) nounwind { } define <2 x float> @vld1dupf(float* %A) nounwind { -;CHECK: vld1dupf: +;CHECK-LABEL: vld1dupf: ;CHECK: vld1.32 {d16[]}, [r0:32] %tmp0 = load float* %A %tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0 @@ -40,7 +40,7 @@ define <2 x float> @vld1dupf(float* %A) nounwind { } define <16 x i8> @vld1dupQi8(i8* %A) nounwind { -;CHECK: vld1dupQi8: +;CHECK-LABEL: vld1dupQi8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[], d17[]}, [r0] %tmp1 = load i8* %A, align 8 @@ -50,7 +50,7 @@ define <16 x i8> @vld1dupQi8(i8* %A) nounwind { } define <4 x float> @vld1dupQf(float* %A) nounwind { -;CHECK: vld1dupQf: +;CHECK-LABEL: vld1dupQf: ;CHECK: vld1.32 {d16[], d17[]}, [r0:32] %tmp0 = load float* %A %tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0 @@ -63,7 +63,7 @@ define <4 x float> @vld1dupQf(float* %A) nounwind { %struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> } define <8 x i8> @vld2dupi8(i8* %A) nounwind { -;CHECK: vld2dupi8: +;CHECK-LABEL: vld2dupi8: ;Check the (default) alignment value. ;CHECK: vld2.8 {d16[], d17[]}, [r0] %tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1) @@ -76,7 +76,7 @@ define <8 x i8> @vld2dupi8(i8* %A) nounwind { } define <4 x i16> @vld2dupi16(i8* %A) nounwind { -;CHECK: vld2dupi16: +;CHECK-LABEL: vld2dupi16: ;Check that a power-of-two alignment smaller than the total size of the memory ;being loaded is ignored. ;CHECK: vld2.16 {d16[], d17[]}, [r0] @@ -91,7 +91,7 @@ define <4 x i16> @vld2dupi16(i8* %A) nounwind { ;Check for a post-increment updating load. define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { -;CHECK: vld2dupi16_update: +;CHECK-LABEL: vld2dupi16_update: ;CHECK: vld2.16 {d16[], d17[]}, [r1]! %A = load i16** %ptr %A2 = bitcast i16* %A to i8* @@ -107,7 +107,7 @@ define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind { } define <2 x i32> @vld2dupi32(i8* %A) nounwind { -;CHECK: vld2dupi32: +;CHECK-LABEL: vld2dupi32: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld2.32 {d16[], d17[]}, [r0:64] %tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16) @@ -128,7 +128,7 @@ declare %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8*, <2 x i32>, ;Check for a post-increment updating load with register increment. define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { -;CHECK: vld3dupi8_update: +;CHECK-LABEL: vld3dupi8_update: ;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1 %A = load i8** %ptr %tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8) @@ -146,7 +146,7 @@ define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind { } define <4 x i16> @vld3dupi16(i8* %A) nounwind { -;CHECK: vld3dupi16: +;CHECK-LABEL: vld3dupi16: ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0] %tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8) @@ -169,7 +169,7 @@ declare %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8*, <4 x i16>, ;Check for a post-increment updating load. define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { -;CHECK: vld4dupi16_update: +;CHECK-LABEL: vld4dupi16_update: ;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]! %A = load i16** %ptr %A2 = bitcast i16* %A to i8* @@ -191,7 +191,7 @@ define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind { } define <2 x i32> @vld4dupi32(i8* %A) nounwind { -;CHECK: vld4dupi32: +;CHECK-LABEL: vld4dupi32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. ;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64] diff --git a/test/CodeGen/ARM/vldlane.ll b/test/CodeGen/ARM/vldlane.ll index f35fa92f5d..a378555eed 100644 --- a/test/CodeGen/ARM/vldlane.ll +++ b/test/CodeGen/ARM/vldlane.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vld1lanei8: +;CHECK-LABEL: vld1lanei8: ;Check the (default) alignment value. ;CHECK: vld1.8 {d16[3]}, [r0] %tmp1 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vld1lanei16: +;CHECK-LABEL: vld1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld1.16 {d16[2]}, [r0:16] %tmp1 = load <4 x i16>* %B @@ -22,7 +22,7 @@ define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vld1lanei32: +;CHECK-LABEL: vld1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B @@ -32,7 +32,7 @@ define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind { } define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vld1lanei32a32: +;CHECK-LABEL: vld1lanei32a32: ;Check the alignment value. Legal values are none or :32. ;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B @@ -42,7 +42,7 @@ define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vld1lanef: +;CHECK-LABEL: vld1lanef: ;CHECK: vld1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x float>* %B %tmp2 = load float* %A, align 4 @@ -51,7 +51,7 @@ define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vld1laneQi8: +;CHECK-LABEL: vld1laneQi8: ;CHECK: vld1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B %tmp2 = load i8* %A, align 8 @@ -60,7 +60,7 @@ define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vld1laneQi16: +;CHECK-LABEL: vld1laneQi16: ;CHECK: vld1.16 {d17[1]}, [r0:16] %tmp1 = load <8 x i16>* %B %tmp2 = load i16* %A, align 8 @@ -69,7 +69,7 @@ define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vld1laneQi32: +;CHECK-LABEL: vld1laneQi32: ;CHECK: vld1.32 {d17[1]}, [r0:32] %tmp1 = load <4 x i32>* %B %tmp2 = load i32* %A, align 8 @@ -78,7 +78,7 @@ define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vld1laneQf: +;CHECK-LABEL: vld1laneQf: ;CHECK: vld1.32 {d16[0]}, [r0:32] %tmp1 = load <4 x float>* %B %tmp2 = load float* %A @@ -96,7 +96,7 @@ define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind { %struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> } define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vld2lanei8: +;CHECK-LABEL: vld2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>* %B @@ -108,7 +108,7 @@ define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vld2lanei16: +;CHECK-LABEL: vld2lanei16: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* @@ -121,7 +121,7 @@ define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vld2lanei32: +;CHECK-LABEL: vld2lanei32: ;CHECK: vld2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -134,7 +134,7 @@ define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind { ;Check for a post-increment updating load. define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { -;CHECK: vld2lanei32_update: +;CHECK-LABEL: vld2lanei32_update: ;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* @@ -149,7 +149,7 @@ define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind { } define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vld2lanef: +;CHECK-LABEL: vld2lanef: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -161,7 +161,7 @@ define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind { } define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vld2laneQi16: +;CHECK-LABEL: vld2laneQi16: ;Check the (default) alignment. ;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* @@ -174,7 +174,7 @@ define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vld2laneQi32: +;CHECK-LABEL: vld2laneQi32: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i32* %A to i8* @@ -187,7 +187,7 @@ define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vld2laneQf: +;CHECK-LABEL: vld2laneQf: ;CHECK: vld2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -217,7 +217,7 @@ declare %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2lane.v4f32(i8*, <4 x flo %struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> } define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vld3lanei8: +;CHECK-LABEL: vld3lanei8: ;CHECK: vld3.8 %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) @@ -230,7 +230,7 @@ define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vld3lanei16: +;CHECK-LABEL: vld3lanei16: ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* @@ -245,7 +245,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vld3lanei32: +;CHECK-LABEL: vld3lanei32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -259,7 +259,7 @@ define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vld3lanef: +;CHECK-LABEL: vld3lanef: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -273,7 +273,7 @@ define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind { } define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vld3laneQi16: +;CHECK-LABEL: vld3laneQi16: ;Check the (default) alignment value. VLD3 does not support alignment. ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* @@ -289,7 +289,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating load with register increment. define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { -;CHECK: vld3laneQi16_update: +;CHECK-LABEL: vld3laneQi16_update: ;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* @@ -306,7 +306,7 @@ define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounw } define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vld3laneQi32: +;CHECK-LABEL: vld3laneQi32: ;CHECK: vld3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B @@ -320,7 +320,7 @@ define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vld3laneQf: +;CHECK-LABEL: vld3laneQf: ;CHECK: vld3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -352,7 +352,7 @@ declare %struct.__neon_float32x4x3_t @llvm.arm.neon.vld3lane.v4f32(i8*, <4 x flo %struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> } define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vld4lanei8: +;CHECK-LABEL: vld4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32] %tmp1 = load <8 x i8>* %B @@ -369,7 +369,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating load. define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { -;CHECK: vld4lanei8_update: +;CHECK-LABEL: vld4lanei8_update: ;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B @@ -387,7 +387,7 @@ define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { } define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vld4lanei16: +;CHECK-LABEL: vld4lanei16: ;Check that a power-of-two alignment smaller than the total size of the memory ;being loaded is ignored. ;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}] @@ -405,7 +405,7 @@ define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vld4lanei32: +;CHECK-LABEL: vld4lanei32: ;Check the alignment value. An 8-byte alignment is allowed here even though ;it is smaller than the total size of the memory being loaded. ;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64] @@ -423,7 +423,7 @@ define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vld4lanef: +;CHECK-LABEL: vld4lanef: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -439,7 +439,7 @@ define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind { } define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vld4laneQi16: +;CHECK-LABEL: vld4laneQi16: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64] %tmp0 = bitcast i16* %A to i8* @@ -456,7 +456,7 @@ define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vld4laneQi32: +;CHECK-LABEL: vld4laneQi32: ;Check the (default) alignment. ;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}] %tmp0 = bitcast i32* %A to i8* @@ -473,7 +473,7 @@ define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vld4laneQf: +;CHECK-LABEL: vld4laneQf: ;CHECK: vld4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B diff --git a/test/CodeGen/ARM/vminmax.ll b/test/CodeGen/ARM/vminmax.ll index e3527c1a4d..81f45782a9 100644 --- a/test/CodeGen/ARM/vminmax.ll +++ b/test/CodeGen/ARM/vminmax.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmins8: +;CHECK-LABEL: vmins8: ;CHECK: vmin.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmins16: +;CHECK-LABEL: vmins16: ;CHECK: vmin.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmins32: +;CHECK-LABEL: vmins32: ;CHECK: vmin.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vminu8: +;CHECK-LABEL: vminu8: ;CHECK: vmin.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vminu16: +;CHECK-LABEL: vminu16: ;CHECK: vmin.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vminu32: +;CHECK-LABEL: vminu32: ;CHECK: vmin.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vminf32: +;CHECK-LABEL: vminf32: ;CHECK: vmin.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -64,7 +64,7 @@ define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vminQs8: +;CHECK-LABEL: vminQs8: ;CHECK: vmin.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -73,7 +73,7 @@ define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vminQs16: +;CHECK-LABEL: vminQs16: ;CHECK: vmin.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -82,7 +82,7 @@ define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vminQs32: +;CHECK-LABEL: vminQs32: ;CHECK: vmin.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -91,7 +91,7 @@ define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vminQu8: +;CHECK-LABEL: vminQu8: ;CHECK: vmin.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -100,7 +100,7 @@ define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vminQu16: +;CHECK-LABEL: vminQu16: ;CHECK: vmin.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -109,7 +109,7 @@ define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vminQu32: +;CHECK-LABEL: vminQu32: ;CHECK: vmin.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -118,7 +118,7 @@ define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vminQf32: +;CHECK-LABEL: vminQf32: ;CHECK: vmin.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -147,7 +147,7 @@ declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind read declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmaxs8: +;CHECK-LABEL: vmaxs8: ;CHECK: vmax.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -156,7 +156,7 @@ define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmaxs16: +;CHECK-LABEL: vmaxs16: ;CHECK: vmax.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -165,7 +165,7 @@ define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmaxs32: +;CHECK-LABEL: vmaxs32: ;CHECK: vmax.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -174,7 +174,7 @@ define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmaxu8: +;CHECK-LABEL: vmaxu8: ;CHECK: vmax.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -183,7 +183,7 @@ define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmaxu16: +;CHECK-LABEL: vmaxu16: ;CHECK: vmax.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -192,7 +192,7 @@ define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmaxu32: +;CHECK-LABEL: vmaxu32: ;CHECK: vmax.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -201,7 +201,7 @@ define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vmaxf32: +;CHECK-LABEL: vmaxf32: ;CHECK: vmax.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -210,7 +210,7 @@ define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vmaxQs8: +;CHECK-LABEL: vmaxQs8: ;CHECK: vmax.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -219,7 +219,7 @@ define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vmaxQs16: +;CHECK-LABEL: vmaxQs16: ;CHECK: vmax.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -228,7 +228,7 @@ define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vmaxQs32: +;CHECK-LABEL: vmaxQs32: ;CHECK: vmax.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -237,7 +237,7 @@ define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vmaxQu8: +;CHECK-LABEL: vmaxQu8: ;CHECK: vmax.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -246,7 +246,7 @@ define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vmaxQu16: +;CHECK-LABEL: vmaxQu16: ;CHECK: vmax.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -255,7 +255,7 @@ define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vmaxQu32: +;CHECK-LABEL: vmaxQu32: ;CHECK: vmax.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -264,7 +264,7 @@ define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vmaxQf32: +;CHECK-LABEL: vmaxQf32: ;CHECK: vmax.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B diff --git a/test/CodeGen/ARM/vmla.ll b/test/CodeGen/ARM/vmla.ll index 9c6b210be7..caf655609c 100644 --- a/test/CodeGen/ARM/vmla.ll +++ b/test/CodeGen/ARM/vmla.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { -;CHECK: vmlai8: +;CHECK-LABEL: vmlai8: ;CHECK: vmla.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { } define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlai16: +;CHECK-LABEL: vmlai16: ;CHECK: vmla.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -23,7 +23,7 @@ define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlai32: +;CHECK-LABEL: vmlai32: ;CHECK: vmla.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -34,7 +34,7 @@ define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { -;CHECK: vmlaf32: +;CHECK-LABEL: vmlaf32: ;CHECK: vmla.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -45,7 +45,7 @@ define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n } define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { -;CHECK: vmlaQi8: +;CHECK-LABEL: vmlaQi8: ;CHECK: vmla.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -56,7 +56,7 @@ define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind } define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: vmlaQi16: +;CHECK-LABEL: vmlaQi16: ;CHECK: vmla.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -67,7 +67,7 @@ define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind } define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: vmlaQi32: +;CHECK-LABEL: vmlaQi32: ;CHECK: vmla.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -78,7 +78,7 @@ define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind } define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { -;CHECK: vmlaQf32: +;CHECK-LABEL: vmlaQf32: ;CHECK: vmla.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -89,7 +89,7 @@ define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) } define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vmlals8: +;CHECK-LABEL: vmlals8: ;CHECK: vmlal.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -102,7 +102,7 @@ define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlals16: +;CHECK-LABEL: vmlals16: ;CHECK: vmlal.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -115,7 +115,7 @@ define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlals32: +;CHECK-LABEL: vmlals32: ;CHECK: vmlal.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -128,7 +128,7 @@ define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vmlalu8: +;CHECK-LABEL: vmlalu8: ;CHECK: vmlal.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -141,7 +141,7 @@ define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlalu16: +;CHECK-LABEL: vmlalu16: ;CHECK: vmlal.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -154,7 +154,7 @@ define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlalu32: +;CHECK-LABEL: vmlalu32: ;CHECK: vmlal.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vmls.ll b/test/CodeGen/ARM/vmls.ll index 65e7fe41bb..61f3424909 100644 --- a/test/CodeGen/ARM/vmls.ll +++ b/test/CodeGen/ARM/vmls.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { -;CHECK: vmlsi8: +;CHECK-LABEL: vmlsi8: ;CHECK: vmls.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind { } define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlsi16: +;CHECK-LABEL: vmlsi16: ;CHECK: vmls.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -23,7 +23,7 @@ define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlsi32: +;CHECK-LABEL: vmlsi32: ;CHECK: vmls.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -34,7 +34,7 @@ define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind { -;CHECK: vmlsf32: +;CHECK-LABEL: vmlsf32: ;CHECK: vmls.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -45,7 +45,7 @@ define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) n } define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind { -;CHECK: vmlsQi8: +;CHECK-LABEL: vmlsQi8: ;CHECK: vmls.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -56,7 +56,7 @@ define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind } define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind { -;CHECK: vmlsQi16: +;CHECK-LABEL: vmlsQi16: ;CHECK: vmls.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -67,7 +67,7 @@ define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind } define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind { -;CHECK: vmlsQi32: +;CHECK-LABEL: vmlsQi32: ;CHECK: vmls.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -78,7 +78,7 @@ define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind } define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind { -;CHECK: vmlsQf32: +;CHECK-LABEL: vmlsQf32: ;CHECK: vmls.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -89,7 +89,7 @@ define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) } define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vmlsls8: +;CHECK-LABEL: vmlsls8: ;CHECK: vmlsl.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -102,7 +102,7 @@ define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlsls16: +;CHECK-LABEL: vmlsls16: ;CHECK: vmlsl.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -115,7 +115,7 @@ define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlsls32: +;CHECK-LABEL: vmlsls32: ;CHECK: vmlsl.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -128,7 +128,7 @@ define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind } define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vmlslu8: +;CHECK-LABEL: vmlslu8: ;CHECK: vmlsl.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -141,7 +141,7 @@ define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vmlslu16: +;CHECK-LABEL: vmlslu16: ;CHECK: vmlsl.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -154,7 +154,7 @@ define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind } define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vmlslu32: +;CHECK-LABEL: vmlslu32: ;CHECK: vmlsl.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vmov.ll b/test/CodeGen/ARM/vmov.ll index 0c2387960b..2b277a2222 100644 --- a/test/CodeGen/ARM/vmov.ll +++ b/test/CodeGen/ARM/vmov.ll @@ -1,169 +1,169 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_movi8() nounwind { -;CHECK: v_movi8: +;CHECK-LABEL: v_movi8: ;CHECK: vmov.i8 d{{.*}}, #0x8 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <4 x i16> @v_movi16a() nounwind { -;CHECK: v_movi16a: +;CHECK-LABEL: v_movi16a: ;CHECK: vmov.i16 d{{.*}}, #0x10 ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > } define <4 x i16> @v_movi16b() nounwind { -;CHECK: v_movi16b: +;CHECK-LABEL: v_movi16b: ;CHECK: vmov.i16 d{{.*}}, #0x1000 ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i16> @v_mvni16a() nounwind { -;CHECK: v_mvni16a: +;CHECK-LABEL: v_mvni16a: ;CHECK: vmvn.i16 d{{.*}}, #0x10 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > } define <4 x i16> @v_mvni16b() nounwind { -;CHECK: v_mvni16b: +;CHECK-LABEL: v_mvni16b: ;CHECK: vmvn.i16 d{{.*}}, #0x1000 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > } define <2 x i32> @v_movi32a() nounwind { -;CHECK: v_movi32a: +;CHECK-LABEL: v_movi32a: ;CHECK: vmov.i32 d{{.*}}, #0x20 ret <2 x i32> < i32 32, i32 32 > } define <2 x i32> @v_movi32b() nounwind { -;CHECK: v_movi32b: +;CHECK-LABEL: v_movi32b: ;CHECK: vmov.i32 d{{.*}}, #0x2000 ret <2 x i32> < i32 8192, i32 8192 > } define <2 x i32> @v_movi32c() nounwind { -;CHECK: v_movi32c: +;CHECK-LABEL: v_movi32c: ;CHECK: vmov.i32 d{{.*}}, #0x200000 ret <2 x i32> < i32 2097152, i32 2097152 > } define <2 x i32> @v_movi32d() nounwind { -;CHECK: v_movi32d: +;CHECK-LABEL: v_movi32d: ;CHECK: vmov.i32 d{{.*}}, #0x20000000 ret <2 x i32> < i32 536870912, i32 536870912 > } define <2 x i32> @v_movi32e() nounwind { -;CHECK: v_movi32e: +;CHECK-LABEL: v_movi32e: ;CHECK: vmov.i32 d{{.*}}, #0x20ff ret <2 x i32> < i32 8447, i32 8447 > } define <2 x i32> @v_movi32f() nounwind { -;CHECK: v_movi32f: +;CHECK-LABEL: v_movi32f: ;CHECK: vmov.i32 d{{.*}}, #0x20ffff ret <2 x i32> < i32 2162687, i32 2162687 > } define <2 x i32> @v_mvni32a() nounwind { -;CHECK: v_mvni32a: +;CHECK-LABEL: v_mvni32a: ;CHECK: vmvn.i32 d{{.*}}, #0x20 ret <2 x i32> < i32 4294967263, i32 4294967263 > } define <2 x i32> @v_mvni32b() nounwind { -;CHECK: v_mvni32b: +;CHECK-LABEL: v_mvni32b: ;CHECK: vmvn.i32 d{{.*}}, #0x2000 ret <2 x i32> < i32 4294959103, i32 4294959103 > } define <2 x i32> @v_mvni32c() nounwind { -;CHECK: v_mvni32c: +;CHECK-LABEL: v_mvni32c: ;CHECK: vmvn.i32 d{{.*}}, #0x200000 ret <2 x i32> < i32 4292870143, i32 4292870143 > } define <2 x i32> @v_mvni32d() nounwind { -;CHECK: v_mvni32d: +;CHECK-LABEL: v_mvni32d: ;CHECK: vmvn.i32 d{{.*}}, #0x20000000 ret <2 x i32> < i32 3758096383, i32 3758096383 > } define <2 x i32> @v_mvni32e() nounwind { -;CHECK: v_mvni32e: +;CHECK-LABEL: v_mvni32e: ;CHECK: vmvn.i32 d{{.*}}, #0x20ff ret <2 x i32> < i32 4294958848, i32 4294958848 > } define <2 x i32> @v_mvni32f() nounwind { -;CHECK: v_mvni32f: +;CHECK-LABEL: v_mvni32f: ;CHECK: vmvn.i32 d{{.*}}, #0x20ffff ret <2 x i32> < i32 4292804608, i32 4292804608 > } define <1 x i64> @v_movi64() nounwind { -;CHECK: v_movi64: +;CHECK-LABEL: v_movi64: ;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff ret <1 x i64> < i64 18374687574888349695 > } define <16 x i8> @v_movQi8() nounwind { -;CHECK: v_movQi8: +;CHECK-LABEL: v_movQi8: ;CHECK: vmov.i8 q{{.*}}, #0x8 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > } define <8 x i16> @v_movQi16a() nounwind { -;CHECK: v_movQi16a: +;CHECK-LABEL: v_movQi16a: ;CHECK: vmov.i16 q{{.*}}, #0x10 ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > } define <8 x i16> @v_movQi16b() nounwind { -;CHECK: v_movQi16b: +;CHECK-LABEL: v_movQi16b: ;CHECK: vmov.i16 q{{.*}}, #0x1000 ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > } define <4 x i32> @v_movQi32a() nounwind { -;CHECK: v_movQi32a: +;CHECK-LABEL: v_movQi32a: ;CHECK: vmov.i32 q{{.*}}, #0x20 ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > } define <4 x i32> @v_movQi32b() nounwind { -;CHECK: v_movQi32b: +;CHECK-LABEL: v_movQi32b: ;CHECK: vmov.i32 q{{.*}}, #0x2000 ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > } define <4 x i32> @v_movQi32c() nounwind { -;CHECK: v_movQi32c: +;CHECK-LABEL: v_movQi32c: ;CHECK: vmov.i32 q{{.*}}, #0x200000 ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > } define <4 x i32> @v_movQi32d() nounwind { -;CHECK: v_movQi32d: +;CHECK-LABEL: v_movQi32d: ;CHECK: vmov.i32 q{{.*}}, #0x20000000 ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > } define <4 x i32> @v_movQi32e() nounwind { -;CHECK: v_movQi32e: +;CHECK-LABEL: v_movQi32e: ;CHECK: vmov.i32 q{{.*}}, #0x20ff ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > } define <4 x i32> @v_movQi32f() nounwind { -;CHECK: v_movQi32f: +;CHECK-LABEL: v_movQi32f: ;CHECK: vmov.i32 q{{.*}}, #0x20ffff ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > } define <2 x i64> @v_movQi64() nounwind { -;CHECK: v_movQi64: +;CHECK-LABEL: v_movQi64: ;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > } @@ -172,7 +172,7 @@ define <2 x i64> @v_movQi64() nounwind { %struct.int8x8_t = type { <8 x i8> } define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: -;CHECK: vdupn128: +;CHECK-LABEL: vdupn128: ;CHECK: vmov.i8 d{{.*}}, #0x80 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8 @@ -181,7 +181,7 @@ entry: define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind { entry: -;CHECK: vdupnneg75: +;CHECK-LABEL: vdupnneg75: ;CHECK: vmov.i8 d{{.*}}, #0xb5 %0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1] store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8 @@ -189,7 +189,7 @@ entry: } define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { -;CHECK: vmovls8: +;CHECK-LABEL: vmovls8: ;CHECK: vmovl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = sext <8 x i8> %tmp1 to <8 x i16> @@ -197,7 +197,7 @@ define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind { } define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { -;CHECK: vmovls16: +;CHECK-LABEL: vmovls16: ;CHECK: vmovl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = sext <4 x i16> %tmp1 to <4 x i32> @@ -205,7 +205,7 @@ define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind { } define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { -;CHECK: vmovls32: +;CHECK-LABEL: vmovls32: ;CHECK: vmovl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = sext <2 x i32> %tmp1 to <2 x i64> @@ -213,7 +213,7 @@ define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind { } define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { -;CHECK: vmovlu8: +;CHECK-LABEL: vmovlu8: ;CHECK: vmovl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = zext <8 x i8> %tmp1 to <8 x i16> @@ -221,7 +221,7 @@ define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind { } define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { -;CHECK: vmovlu16: +;CHECK-LABEL: vmovlu16: ;CHECK: vmovl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = zext <4 x i16> %tmp1 to <4 x i32> @@ -229,7 +229,7 @@ define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind { } define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { -;CHECK: vmovlu32: +;CHECK-LABEL: vmovlu32: ;CHECK: vmovl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = zext <2 x i32> %tmp1 to <2 x i64> @@ -237,7 +237,7 @@ define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind { } define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { -;CHECK: vmovni16: +;CHECK-LABEL: vmovni16: ;CHECK: vmovn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = trunc <8 x i16> %tmp1 to <8 x i8> @@ -245,7 +245,7 @@ define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind { } define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { -;CHECK: vmovni32: +;CHECK-LABEL: vmovni32: ;CHECK: vmovn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = trunc <4 x i32> %tmp1 to <4 x i16> @@ -253,7 +253,7 @@ define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind { } define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { -;CHECK: vmovni64: +;CHECK-LABEL: vmovni64: ;CHECK: vmovn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = trunc <2 x i64> %tmp1 to <2 x i32> @@ -261,7 +261,7 @@ define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind { } define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { -;CHECK: vqmovns16: +;CHECK-LABEL: vqmovns16: ;CHECK: vqmovn.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1) @@ -269,7 +269,7 @@ define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind { } define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { -;CHECK: vqmovns32: +;CHECK-LABEL: vqmovns32: ;CHECK: vqmovn.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1) @@ -277,7 +277,7 @@ define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind { } define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { -;CHECK: vqmovns64: +;CHECK-LABEL: vqmovns64: ;CHECK: vqmovn.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1) @@ -285,7 +285,7 @@ define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind { } define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { -;CHECK: vqmovnu16: +;CHECK-LABEL: vqmovnu16: ;CHECK: vqmovn.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1) @@ -293,7 +293,7 @@ define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind { } define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { -;CHECK: vqmovnu32: +;CHECK-LABEL: vqmovnu32: ;CHECK: vqmovn.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1) @@ -301,7 +301,7 @@ define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind { } define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { -;CHECK: vqmovnu64: +;CHECK-LABEL: vqmovnu64: ;CHECK: vqmovn.u64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1) @@ -309,7 +309,7 @@ define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind { } define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { -;CHECK: vqmovuns16: +;CHECK-LABEL: vqmovuns16: ;CHECK: vqmovun.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1) @@ -317,7 +317,7 @@ define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind { } define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { -;CHECK: vqmovuns32: +;CHECK-LABEL: vqmovuns32: ;CHECK: vqmovun.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1) @@ -325,7 +325,7 @@ define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind { } define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind { -;CHECK: vqmovuns64: +;CHECK-LABEL: vqmovuns64: ;CHECK: vqmovun.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1) @@ -358,7 +358,7 @@ define void @noTruncStore(<4 x i32>* %a, <4 x i16>* %b) nounwind { ; rdar://10437054 define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind { entry: -;CHECK: v_mov_v2f32: +;CHECK-LABEL: v_mov_v2f32: ;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01 store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4 ret void @@ -366,7 +366,7 @@ entry: define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind { entry: -;CHECK: v_mov_v4f32: +;CHECK-LABEL: v_mov_v4f32: ;CHECK: vmov.f32 q{{.*}}, #3.100000e+01 store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4 ret void @@ -374,7 +374,7 @@ entry: define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind { entry: -;CHECK: v_mov_v4f32_undef: +;CHECK-LABEL: v_mov_v4f32_undef: ;CHECK: vmov.f32 q{{.*}}, #1.000000e+00 %a = load <4 x float> *%p %b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0> diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index aa3cda0707..6210ad3695 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmuli8: +;CHECK-LABEL: vmuli8: ;CHECK: vmul.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmuli16: +;CHECK-LABEL: vmuli16: ;CHECK: vmul.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmuli32: +;CHECK-LABEL: vmuli32: ;CHECK: vmul.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vmulf32: +;CHECK-LABEL: vmulf32: ;CHECK: vmul.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -37,7 +37,7 @@ define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmulp8: +;CHECK-LABEL: vmulp8: ;CHECK: vmul.p8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -46,7 +46,7 @@ define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vmulQi8: +;CHECK-LABEL: vmulQi8: ;CHECK: vmul.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -55,7 +55,7 @@ define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vmulQi16: +;CHECK-LABEL: vmulQi16: ;CHECK: vmul.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -64,7 +64,7 @@ define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vmulQi32: +;CHECK-LABEL: vmulQi32: ;CHECK: vmul.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -73,7 +73,7 @@ define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vmulQf32: +;CHECK-LABEL: vmulQf32: ;CHECK: vmul.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -82,7 +82,7 @@ define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vmulQp8: +;CHECK-LABEL: vmulQp8: ;CHECK: vmul.p8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -148,7 +148,7 @@ entry: } define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmulls8: +;CHECK-LABEL: vmulls8: ;CHECK: vmull.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -159,7 +159,7 @@ define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmulls8_int: +;CHECK-LABEL: vmulls8_int: ;CHECK: vmull.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -168,7 +168,7 @@ define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmulls16: +;CHECK-LABEL: vmulls16: ;CHECK: vmull.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -179,7 +179,7 @@ define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmulls16_int: +;CHECK-LABEL: vmulls16_int: ;CHECK: vmull.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -188,7 +188,7 @@ define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmulls32: +;CHECK-LABEL: vmulls32: ;CHECK: vmull.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -199,7 +199,7 @@ define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmulls32_int: +;CHECK-LABEL: vmulls32_int: ;CHECK: vmull.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -208,7 +208,7 @@ define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmullu8: +;CHECK-LABEL: vmullu8: ;CHECK: vmull.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -219,7 +219,7 @@ define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmullu8_int: +;CHECK-LABEL: vmullu8_int: ;CHECK: vmull.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -228,7 +228,7 @@ define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmullu16: +;CHECK-LABEL: vmullu16: ;CHECK: vmull.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -239,7 +239,7 @@ define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vmullu16_int: +;CHECK-LABEL: vmullu16_int: ;CHECK: vmull.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -248,7 +248,7 @@ define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmullu32: +;CHECK-LABEL: vmullu32: ;CHECK: vmull.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -259,7 +259,7 @@ define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vmullu32_int: +;CHECK-LABEL: vmullu32_int: ;CHECK: vmull.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -268,7 +268,7 @@ define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vmullp8: +;CHECK-LABEL: vmullp8: ;CHECK: vmull.p8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -441,7 +441,7 @@ define <2 x i64> @vmull_extvec_u32(<2 x i32> %arg) nounwind { ; rdar://9197392 define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind { entry: -; CHECK: distribute: +; CHECK-LABEL: distribute: ; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]] ; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]] %0 = trunc i32 %mul to i8 diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll index 4a10732458..1be4f74821 100644 --- a/test/CodeGen/ARM/vneg.ll +++ b/test/CodeGen/ARM/vneg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { -;CHECK: vnegs8: +;CHECK-LABEL: vnegs8: ;CHECK: vneg.s8 %tmp1 = load <8 x i8>* %A %tmp2 = sub <8 x i8> zeroinitializer, %tmp1 @@ -9,7 +9,7 @@ define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { } define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { -;CHECK: vnegs16: +;CHECK-LABEL: vnegs16: ;CHECK: vneg.s16 %tmp1 = load <4 x i16>* %A %tmp2 = sub <4 x i16> zeroinitializer, %tmp1 @@ -17,7 +17,7 @@ define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { } define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { -;CHECK: vnegs32: +;CHECK-LABEL: vnegs32: ;CHECK: vneg.s32 %tmp1 = load <2 x i32>* %A %tmp2 = sub <2 x i32> zeroinitializer, %tmp1 @@ -25,7 +25,7 @@ define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { } define <2 x float> @vnegf32(<2 x float>* %A) nounwind { -;CHECK: vnegf32: +;CHECK-LABEL: vnegf32: ;CHECK: vneg.f32 %tmp1 = load <2 x float>* %A %tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 @@ -33,7 +33,7 @@ define <2 x float> @vnegf32(<2 x float>* %A) nounwind { } define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { -;CHECK: vnegQs8: +;CHECK-LABEL: vnegQs8: ;CHECK: vneg.s8 %tmp1 = load <16 x i8>* %A %tmp2 = sub <16 x i8> zeroinitializer, %tmp1 @@ -41,7 +41,7 @@ define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { -;CHECK: vnegQs16: +;CHECK-LABEL: vnegQs16: ;CHECK: vneg.s16 %tmp1 = load <8 x i16>* %A %tmp2 = sub <8 x i16> zeroinitializer, %tmp1 @@ -49,7 +49,7 @@ define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { -;CHECK: vnegQs32: +;CHECK-LABEL: vnegQs32: ;CHECK: vneg.s32 %tmp1 = load <4 x i32>* %A %tmp2 = sub <4 x i32> zeroinitializer, %tmp1 @@ -57,7 +57,7 @@ define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { } define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { -;CHECK: vnegQf32: +;CHECK-LABEL: vnegQf32: ;CHECK: vneg.f32 %tmp1 = load <4 x float>* %A %tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 @@ -65,7 +65,7 @@ define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { } define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { -;CHECK: vqnegs8: +;CHECK-LABEL: vqnegs8: ;CHECK: vqneg.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1) @@ -73,7 +73,7 @@ define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind { } define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { -;CHECK: vqnegs16: +;CHECK-LABEL: vqnegs16: ;CHECK: vqneg.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1) @@ -81,7 +81,7 @@ define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind { } define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { -;CHECK: vqnegs32: +;CHECK-LABEL: vqnegs32: ;CHECK: vqneg.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1) @@ -89,7 +89,7 @@ define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind { } define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { -;CHECK: vqnegQs8: +;CHECK-LABEL: vqnegQs8: ;CHECK: vqneg.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1) @@ -97,7 +97,7 @@ define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { -;CHECK: vqnegQs16: +;CHECK-LABEL: vqnegQs16: ;CHECK: vqneg.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1) @@ -105,7 +105,7 @@ define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind { -;CHECK: vqnegQs32: +;CHECK-LABEL: vqnegQs32: ;CHECK: vqneg.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1) diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll index 7296e936cd..a616a8d270 100644 --- a/test/CodeGen/ARM/vpadal.ll +++ b/test/CodeGen/ARM/vpadal.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpadals8: +;CHECK-LABEL: vpadals8: ;CHECK: vpadal.s8 %tmp1 = load <4 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { } define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpadals16: +;CHECK-LABEL: vpadals16: ;CHECK: vpadal.s16 %tmp1 = load <2 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { } define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpadals32: +;CHECK-LABEL: vpadals32: ;CHECK: vpadal.s32 %tmp1 = load <1 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { } define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpadalu8: +;CHECK-LABEL: vpadalu8: ;CHECK: vpadal.u8 %tmp1 = load <4 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { } define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpadalu16: +;CHECK-LABEL: vpadalu16: ;CHECK: vpadal.u16 %tmp1 = load <2 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { } define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpadalu32: +;CHECK-LABEL: vpadalu32: ;CHECK: vpadal.u32 %tmp1 = load <1 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { -;CHECK: vpadalQs8: +;CHECK-LABEL: vpadalQs8: ;CHECK: vpadal.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <16 x i8>* %B @@ -64,7 +64,7 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { } define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { -;CHECK: vpadalQs16: +;CHECK-LABEL: vpadalQs16: ;CHECK: vpadal.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <8 x i16>* %B @@ -73,7 +73,7 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { } define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { -;CHECK: vpadalQs32: +;CHECK-LABEL: vpadalQs32: ;CHECK: vpadal.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <4 x i32>* %B @@ -82,7 +82,7 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { } define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { -;CHECK: vpadalQu8: +;CHECK-LABEL: vpadalQu8: ;CHECK: vpadal.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <16 x i8>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { } define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { -;CHECK: vpadalQu16: +;CHECK-LABEL: vpadalQu16: ;CHECK: vpadal.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <8 x i16>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { } define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind { -;CHECK: vpadalQu32: +;CHECK-LABEL: vpadalQu32: ;CHECK: vpadal.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <4 x i32>* %B diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index 1ba68f5523..f84721f996 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpaddi8: +;CHECK-LABEL: vpaddi8: ;CHECK: vpadd.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpaddi16: +;CHECK-LABEL: vpaddi16: ;CHECK: vpadd.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpaddi32: +;CHECK-LABEL: vpaddi32: ;CHECK: vpadd.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vpaddf32: +;CHECK-LABEL: vpaddf32: ;CHECK: vpadd.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -43,7 +43,7 @@ declare <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32>, <2 x i32>) nounwind read declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { -;CHECK: vpaddls8: +;CHECK-LABEL: vpaddls8: ;CHECK: vpaddl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1) @@ -51,7 +51,7 @@ define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { } define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { -;CHECK: vpaddls16: +;CHECK-LABEL: vpaddls16: ;CHECK: vpaddl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1) @@ -59,7 +59,7 @@ define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { } define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { -;CHECK: vpaddls32: +;CHECK-LABEL: vpaddls32: ;CHECK: vpaddl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1) @@ -67,7 +67,7 @@ define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { } define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { -;CHECK: vpaddlu8: +;CHECK-LABEL: vpaddlu8: ;CHECK: vpaddl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1) @@ -75,7 +75,7 @@ define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { } define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { -;CHECK: vpaddlu16: +;CHECK-LABEL: vpaddlu16: ;CHECK: vpaddl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1) @@ -83,7 +83,7 @@ define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { } define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { -;CHECK: vpaddlu32: +;CHECK-LABEL: vpaddlu32: ;CHECK: vpaddl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1) @@ -91,7 +91,7 @@ define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { } define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { -;CHECK: vpaddlQs8: +;CHECK-LABEL: vpaddlQs8: ;CHECK: vpaddl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1) @@ -99,7 +99,7 @@ define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { } define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { -;CHECK: vpaddlQs16: +;CHECK-LABEL: vpaddlQs16: ;CHECK: vpaddl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1) @@ -107,7 +107,7 @@ define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { } define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { -;CHECK: vpaddlQs32: +;CHECK-LABEL: vpaddlQs32: ;CHECK: vpaddl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1) @@ -115,7 +115,7 @@ define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { } define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { -;CHECK: vpaddlQu8: +;CHECK-LABEL: vpaddlQu8: ;CHECK: vpaddl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1) @@ -123,7 +123,7 @@ define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { } define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { -;CHECK: vpaddlQu16: +;CHECK-LABEL: vpaddlQu16: ;CHECK: vpaddl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1) @@ -131,7 +131,7 @@ define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { } define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { -;CHECK: vpaddlQu32: +;CHECK-LABEL: vpaddlQu32: ;CHECK: vpaddl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1) diff --git a/test/CodeGen/ARM/vpminmax.ll b/test/CodeGen/ARM/vpminmax.ll index b75bcc99f6..c68b3193c1 100644 --- a/test/CodeGen/ARM/vpminmax.ll +++ b/test/CodeGen/ARM/vpminmax.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpmins8: +;CHECK-LABEL: vpmins8: ;CHECK: vpmin.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpmins16: +;CHECK-LABEL: vpmins16: ;CHECK: vpmin.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpmins32: +;CHECK-LABEL: vpmins32: ;CHECK: vpmin.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpminu8: +;CHECK-LABEL: vpminu8: ;CHECK: vpmin.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -37,7 +37,7 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpminu16: +;CHECK-LABEL: vpminu16: ;CHECK: vpmin.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpminu32: +;CHECK-LABEL: vpminu32: ;CHECK: vpmin.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -55,7 +55,7 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vpminf32: +;CHECK-LABEL: vpminf32: ;CHECK: vpmin.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -74,7 +74,7 @@ declare <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32>, <2 x i32>) nounwind rea declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpmaxs8: +;CHECK-LABEL: vpmaxs8: ;CHECK: vpmax.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -83,7 +83,7 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpmaxs16: +;CHECK-LABEL: vpmaxs16: ;CHECK: vpmax.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -92,7 +92,7 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpmaxs32: +;CHECK-LABEL: vpmaxs32: ;CHECK: vpmax.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -101,7 +101,7 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vpmaxu8: +;CHECK-LABEL: vpmaxu8: ;CHECK: vpmax.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -110,7 +110,7 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vpmaxu16: +;CHECK-LABEL: vpmaxu16: ;CHECK: vpmax.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -119,7 +119,7 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vpmaxu32: +;CHECK-LABEL: vpmaxu32: ;CHECK: vpmax.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -128,7 +128,7 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vpmaxf32: +;CHECK-LABEL: vpmaxf32: ;CHECK: vpmax.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B diff --git a/test/CodeGen/ARM/vqadd.ll b/test/CodeGen/ARM/vqadd.ll index a1669b60ab..7840766854 100644 --- a/test/CodeGen/ARM/vqadd.ll +++ b/test/CodeGen/ARM/vqadd.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqadds8: +;CHECK-LABEL: vqadds8: ;CHECK: vqadd.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqadds16: +;CHECK-LABEL: vqadds16: ;CHECK: vqadd.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqadds32: +;CHECK-LABEL: vqadds32: ;CHECK: vqadd.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqadds64: +;CHECK-LABEL: vqadds64: ;CHECK: vqadd.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqaddu8: +;CHECK-LABEL: vqaddu8: ;CHECK: vqadd.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -46,7 +46,7 @@ define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqaddu16: +;CHECK-LABEL: vqaddu16: ;CHECK: vqadd.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -55,7 +55,7 @@ define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqaddu32: +;CHECK-LABEL: vqaddu32: ;CHECK: vqadd.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -64,7 +64,7 @@ define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqaddu64: +;CHECK-LABEL: vqaddu64: ;CHECK: vqadd.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -73,7 +73,7 @@ define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqaddQs8: +;CHECK-LABEL: vqaddQs8: ;CHECK: vqadd.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqaddQs16: +;CHECK-LABEL: vqaddQs16: ;CHECK: vqadd.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqaddQs32: +;CHECK-LABEL: vqaddQs32: ;CHECK: vqadd.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqaddQs64: +;CHECK-LABEL: vqaddQs64: ;CHECK: vqadd.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -109,7 +109,7 @@ define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqaddQu8: +;CHECK-LABEL: vqaddQu8: ;CHECK: vqadd.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -118,7 +118,7 @@ define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqaddQu16: +;CHECK-LABEL: vqaddQu16: ;CHECK: vqadd.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -127,7 +127,7 @@ define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqaddQu32: +;CHECK-LABEL: vqaddQu32: ;CHECK: vqadd.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -136,7 +136,7 @@ define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqaddQu64: +;CHECK-LABEL: vqaddQu64: ;CHECK: vqadd.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vqdmul.ll b/test/CodeGen/ARM/vqdmul.ll index 08e7d2b2c0..a28cae9aae 100644 --- a/test/CodeGen/ARM/vqdmul.ll +++ b/test/CodeGen/ARM/vqdmul.ll @@ -3,7 +3,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32- target triple = "thumbv7-elf" define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqdmulhs16: +;CHECK-LABEL: vqdmulhs16: ;CHECK: vqdmulh.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -12,7 +12,7 @@ define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqdmulhs32: +;CHECK-LABEL: vqdmulhs32: ;CHECK: vqdmulh.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -21,7 +21,7 @@ define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqdmulhQs16: +;CHECK-LABEL: vqdmulhQs16: ;CHECK: vqdmulh.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -30,7 +30,7 @@ define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqdmulhQs32: +;CHECK-LABEL: vqdmulhQs32: ;CHECK: vqdmulh.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -81,7 +81,7 @@ declare <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind re declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqrdmulhs16: +;CHECK-LABEL: vqrdmulhs16: ;CHECK: vqrdmulh.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -90,7 +90,7 @@ define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqrdmulhs32: +;CHECK-LABEL: vqrdmulhs32: ;CHECK: vqrdmulh.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -99,7 +99,7 @@ define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqrdmulhQs16: +;CHECK-LABEL: vqrdmulhQs16: ;CHECK: vqrdmulh.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -108,7 +108,7 @@ define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqrdmulhQs32: +;CHECK-LABEL: vqrdmulhQs32: ;CHECK: vqrdmulh.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -159,7 +159,7 @@ declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind r declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqdmulls16: +;CHECK-LABEL: vqdmulls16: ;CHECK: vqdmull.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -168,7 +168,7 @@ define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqdmulls32: +;CHECK-LABEL: vqdmulls32: ;CHECK: vqdmull.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -198,7 +198,7 @@ declare <4 x i32> @llvm.arm.neon.vqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind r declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vqdmlals16: +;CHECK-LABEL: vqdmlals16: ;CHECK: vqdmlal.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -208,7 +208,7 @@ define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi } define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vqdmlals32: +;CHECK-LABEL: vqdmlals32: ;CHECK: vqdmlal.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -239,7 +239,7 @@ declare <4 x i32> @llvm.arm.neon.vqdmlal.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { -;CHECK: vqdmlsls16: +;CHECK-LABEL: vqdmlsls16: ;CHECK: vqdmlsl.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -249,7 +249,7 @@ define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwi } define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { -;CHECK: vqdmlsls32: +;CHECK-LABEL: vqdmlsls32: ;CHECK: vqdmlsl.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vqshl.ll b/test/CodeGen/ARM/vqshl.ll index e4d29a337c..b5cd71613d 100644 --- a/test/CodeGen/ARM/vqshl.ll +++ b/test/CodeGen/ARM/vqshl.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqshls8: +;CHECK-LABEL: vqshls8: ;CHECK: vqshl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqshls16: +;CHECK-LABEL: vqshls16: ;CHECK: vqshl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqshls32: +;CHECK-LABEL: vqshls32: ;CHECK: vqshl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqshls64: +;CHECK-LABEL: vqshls64: ;CHECK: vqshl.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqshlu8: +;CHECK-LABEL: vqshlu8: ;CHECK: vqshl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -46,7 +46,7 @@ define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqshlu16: +;CHECK-LABEL: vqshlu16: ;CHECK: vqshl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -55,7 +55,7 @@ define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqshlu32: +;CHECK-LABEL: vqshlu32: ;CHECK: vqshl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -64,7 +64,7 @@ define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqshlu64: +;CHECK-LABEL: vqshlu64: ;CHECK: vqshl.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -73,7 +73,7 @@ define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqshlQs8: +;CHECK-LABEL: vqshlQs8: ;CHECK: vqshl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqshlQs16: +;CHECK-LABEL: vqshlQs16: ;CHECK: vqshl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqshlQs32: +;CHECK-LABEL: vqshlQs32: ;CHECK: vqshl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqshlQs64: +;CHECK-LABEL: vqshlQs64: ;CHECK: vqshl.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -109,7 +109,7 @@ define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqshlQu8: +;CHECK-LABEL: vqshlQu8: ;CHECK: vqshl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -118,7 +118,7 @@ define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqshlQu16: +;CHECK-LABEL: vqshlQu16: ;CHECK: vqshl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -127,7 +127,7 @@ define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqshlQu32: +;CHECK-LABEL: vqshlQu32: ;CHECK: vqshl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -136,7 +136,7 @@ define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqshlQu64: +;CHECK-LABEL: vqshlQu64: ;CHECK: vqshl.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -145,7 +145,7 @@ define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind { -;CHECK: vqshls_n8: +;CHECK-LABEL: vqshls_n8: ;CHECK: vqshl.s8{{.*#7}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -153,7 +153,7 @@ define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind { } define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind { -;CHECK: vqshls_n16: +;CHECK-LABEL: vqshls_n16: ;CHECK: vqshl.s16{{.*#15}} %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -161,7 +161,7 @@ define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind { } define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind { -;CHECK: vqshls_n32: +;CHECK-LABEL: vqshls_n32: ;CHECK: vqshl.s32{{.*#31}} %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -169,7 +169,7 @@ define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind { } define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind { -;CHECK: vqshls_n64: +;CHECK-LABEL: vqshls_n64: ;CHECK: vqshl.s64{{.*#63}} %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) @@ -177,7 +177,7 @@ define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind { } define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind { -;CHECK: vqshlu_n8: +;CHECK-LABEL: vqshlu_n8: ;CHECK: vqshl.u8{{.*#7}} %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -185,7 +185,7 @@ define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind { } define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind { -;CHECK: vqshlu_n16: +;CHECK-LABEL: vqshlu_n16: ;CHECK: vqshl.u16{{.*#15}} %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -193,7 +193,7 @@ define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind { } define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind { -;CHECK: vqshlu_n32: +;CHECK-LABEL: vqshlu_n32: ;CHECK: vqshl.u32{{.*#31}} %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -201,7 +201,7 @@ define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind { } define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind { -;CHECK: vqshlu_n64: +;CHECK-LABEL: vqshlu_n64: ;CHECK: vqshl.u64{{.*#63}} %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) @@ -209,7 +209,7 @@ define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind { } define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind { -;CHECK: vqshlsu_n8: +;CHECK-LABEL: vqshlsu_n8: ;CHECK: vqshlu.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -217,7 +217,7 @@ define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind { } define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind { -;CHECK: vqshlsu_n16: +;CHECK-LABEL: vqshlsu_n16: ;CHECK: vqshlu.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -225,7 +225,7 @@ define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind { } define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind { -;CHECK: vqshlsu_n32: +;CHECK-LABEL: vqshlsu_n32: ;CHECK: vqshlu.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -233,7 +233,7 @@ define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind { } define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind { -;CHECK: vqshlsu_n64: +;CHECK-LABEL: vqshlsu_n64: ;CHECK: vqshlu.s64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) @@ -241,7 +241,7 @@ define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind { } define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind { -;CHECK: vqshlQs_n8: +;CHECK-LABEL: vqshlQs_n8: ;CHECK: vqshl.s8{{.*#7}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -249,7 +249,7 @@ define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind { } define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind { -;CHECK: vqshlQs_n16: +;CHECK-LABEL: vqshlQs_n16: ;CHECK: vqshl.s16{{.*#15}} %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) @@ -257,7 +257,7 @@ define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind { } define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind { -;CHECK: vqshlQs_n32: +;CHECK-LABEL: vqshlQs_n32: ;CHECK: vqshl.s32{{.*#31}} %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) @@ -265,7 +265,7 @@ define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind { } define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind { -;CHECK: vqshlQs_n64: +;CHECK-LABEL: vqshlQs_n64: ;CHECK: vqshl.s64{{.*#63}} %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) @@ -273,7 +273,7 @@ define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind { } define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind { -;CHECK: vqshlQu_n8: +;CHECK-LABEL: vqshlQu_n8: ;CHECK: vqshl.u8{{.*#7}} %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -281,7 +281,7 @@ define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind { } define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind { -;CHECK: vqshlQu_n16: +;CHECK-LABEL: vqshlQu_n16: ;CHECK: vqshl.u16{{.*#15}} %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) @@ -289,7 +289,7 @@ define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind { } define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind { -;CHECK: vqshlQu_n32: +;CHECK-LABEL: vqshlQu_n32: ;CHECK: vqshl.u32{{.*#31}} %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) @@ -297,7 +297,7 @@ define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind { } define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind { -;CHECK: vqshlQu_n64: +;CHECK-LABEL: vqshlQu_n64: ;CHECK: vqshl.u64{{.*#63}} %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) @@ -305,7 +305,7 @@ define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind { } define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind { -;CHECK: vqshlQsu_n8: +;CHECK-LABEL: vqshlQsu_n8: ;CHECK: vqshlu.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -313,7 +313,7 @@ define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind { } define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind { -;CHECK: vqshlQsu_n16: +;CHECK-LABEL: vqshlQsu_n16: ;CHECK: vqshlu.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) @@ -321,7 +321,7 @@ define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind { } define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind { -;CHECK: vqshlQsu_n32: +;CHECK-LABEL: vqshlQsu_n32: ;CHECK: vqshlu.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) @@ -329,7 +329,7 @@ define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind { } define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind { -;CHECK: vqshlQsu_n64: +;CHECK-LABEL: vqshlQsu_n64: ;CHECK: vqshlu.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) @@ -367,7 +367,7 @@ declare <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32>, <4 x i32>) nounwind declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqrshls8: +;CHECK-LABEL: vqrshls8: ;CHECK: vqrshl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -376,7 +376,7 @@ define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqrshls16: +;CHECK-LABEL: vqrshls16: ;CHECK: vqrshl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -385,7 +385,7 @@ define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqrshls32: +;CHECK-LABEL: vqrshls32: ;CHECK: vqrshl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -394,7 +394,7 @@ define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqrshls64: +;CHECK-LABEL: vqrshls64: ;CHECK: vqrshl.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -403,7 +403,7 @@ define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqrshlu8: +;CHECK-LABEL: vqrshlu8: ;CHECK: vqrshl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -412,7 +412,7 @@ define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqrshlu16: +;CHECK-LABEL: vqrshlu16: ;CHECK: vqrshl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -421,7 +421,7 @@ define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqrshlu32: +;CHECK-LABEL: vqrshlu32: ;CHECK: vqrshl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -430,7 +430,7 @@ define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqrshlu64: +;CHECK-LABEL: vqrshlu64: ;CHECK: vqrshl.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -439,7 +439,7 @@ define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqrshlQs8: +;CHECK-LABEL: vqrshlQs8: ;CHECK: vqrshl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -448,7 +448,7 @@ define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqrshlQs16: +;CHECK-LABEL: vqrshlQs16: ;CHECK: vqrshl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -457,7 +457,7 @@ define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqrshlQs32: +;CHECK-LABEL: vqrshlQs32: ;CHECK: vqrshl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -466,7 +466,7 @@ define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqrshlQs64: +;CHECK-LABEL: vqrshlQs64: ;CHECK: vqrshl.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -475,7 +475,7 @@ define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqrshlQu8: +;CHECK-LABEL: vqrshlQu8: ;CHECK: vqrshl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -484,7 +484,7 @@ define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqrshlQu16: +;CHECK-LABEL: vqrshlQu16: ;CHECK: vqrshl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -493,7 +493,7 @@ define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqrshlQu32: +;CHECK-LABEL: vqrshlQu32: ;CHECK: vqrshl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -502,7 +502,7 @@ define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqrshlQu64: +;CHECK-LABEL: vqrshlQu64: ;CHECK: vqrshl.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vqshrn.ll b/test/CodeGen/ARM/vqshrn.ll index 5da79432bb..4abae700f8 100644 --- a/test/CodeGen/ARM/vqshrn.ll +++ b/test/CodeGen/ARM/vqshrn.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { -;CHECK: vqshrns8: +;CHECK-LABEL: vqshrns8: ;CHECK: vqshrn.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -9,7 +9,7 @@ define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind { -;CHECK: vqshrns16: +;CHECK-LABEL: vqshrns16: ;CHECK: vqshrn.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -17,7 +17,7 @@ define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind { -;CHECK: vqshrns32: +;CHECK-LABEL: vqshrns32: ;CHECK: vqshrn.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -25,7 +25,7 @@ define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind { } define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind { -;CHECK: vqshrnu8: +;CHECK-LABEL: vqshrnu8: ;CHECK: vqshrn.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -33,7 +33,7 @@ define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind { -;CHECK: vqshrnu16: +;CHECK-LABEL: vqshrnu16: ;CHECK: vqshrn.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -41,7 +41,7 @@ define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind { -;CHECK: vqshrnu32: +;CHECK-LABEL: vqshrnu32: ;CHECK: vqshrn.u64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -49,7 +49,7 @@ define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind { } define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind { -;CHECK: vqshruns8: +;CHECK-LABEL: vqshruns8: ;CHECK: vqshrun.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -57,7 +57,7 @@ define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind { -;CHECK: vqshruns16: +;CHECK-LABEL: vqshruns16: ;CHECK: vqshrun.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -65,7 +65,7 @@ define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind { -;CHECK: vqshruns32: +;CHECK-LABEL: vqshruns32: ;CHECK: vqshrun.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -85,7 +85,7 @@ declare <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32>, <4 x i32>) nounwind declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind { -;CHECK: vqrshrns8: +;CHECK-LABEL: vqrshrns8: ;CHECK: vqrshrn.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -93,7 +93,7 @@ define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind { -;CHECK: vqrshrns16: +;CHECK-LABEL: vqrshrns16: ;CHECK: vqrshrn.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -101,7 +101,7 @@ define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind { -;CHECK: vqrshrns32: +;CHECK-LABEL: vqrshrns32: ;CHECK: vqrshrn.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -109,7 +109,7 @@ define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind { } define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind { -;CHECK: vqrshrnu8: +;CHECK-LABEL: vqrshrnu8: ;CHECK: vqrshrn.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -117,7 +117,7 @@ define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind { -;CHECK: vqrshrnu16: +;CHECK-LABEL: vqrshrnu16: ;CHECK: vqrshrn.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -125,7 +125,7 @@ define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind { -;CHECK: vqrshrnu32: +;CHECK-LABEL: vqrshrnu32: ;CHECK: vqrshrn.u64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -133,7 +133,7 @@ define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind { } define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind { -;CHECK: vqrshruns8: +;CHECK-LABEL: vqrshruns8: ;CHECK: vqrshrun.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -141,7 +141,7 @@ define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind { -;CHECK: vqrshruns16: +;CHECK-LABEL: vqrshruns16: ;CHECK: vqrshrun.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -149,7 +149,7 @@ define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind { -;CHECK: vqrshruns32: +;CHECK-LABEL: vqrshruns32: ;CHECK: vqrshrun.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) diff --git a/test/CodeGen/ARM/vqsub.ll b/test/CodeGen/ARM/vqsub.ll index 4231fca37e..90bc3492fc 100644 --- a/test/CodeGen/ARM/vqsub.ll +++ b/test/CodeGen/ARM/vqsub.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqsubs8: +;CHECK-LABEL: vqsubs8: ;CHECK: vqsub.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqsubs16: +;CHECK-LABEL: vqsubs16: ;CHECK: vqsub.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqsubs32: +;CHECK-LABEL: vqsubs32: ;CHECK: vqsub.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqsubs64: +;CHECK-LABEL: vqsubs64: ;CHECK: vqsub.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vqsubu8: +;CHECK-LABEL: vqsubu8: ;CHECK: vqsub.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -46,7 +46,7 @@ define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vqsubu16: +;CHECK-LABEL: vqsubu16: ;CHECK: vqsub.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -55,7 +55,7 @@ define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vqsubu32: +;CHECK-LABEL: vqsubu32: ;CHECK: vqsub.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -64,7 +64,7 @@ define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vqsubu64: +;CHECK-LABEL: vqsubu64: ;CHECK: vqsub.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -73,7 +73,7 @@ define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqsubQs8: +;CHECK-LABEL: vqsubQs8: ;CHECK: vqsub.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqsubQs16: +;CHECK-LABEL: vqsubQs16: ;CHECK: vqsub.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqsubQs32: +;CHECK-LABEL: vqsubQs32: ;CHECK: vqsub.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqsubQs64: +;CHECK-LABEL: vqsubQs64: ;CHECK: vqsub.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -109,7 +109,7 @@ define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vqsubQu8: +;CHECK-LABEL: vqsubQu8: ;CHECK: vqsub.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -118,7 +118,7 @@ define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vqsubQu16: +;CHECK-LABEL: vqsubQu16: ;CHECK: vqsub.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -127,7 +127,7 @@ define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vqsubQu32: +;CHECK-LABEL: vqsubQu32: ;CHECK: vqsub.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -136,7 +136,7 @@ define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vqsubQu64: +;CHECK-LABEL: vqsubQu64: ;CHECK: vqsub.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vrec.ll b/test/CodeGen/ARM/vrec.ll index 99989e9d61..c0deca9957 100644 --- a/test/CodeGen/ARM/vrec.ll +++ b/test/CodeGen/ARM/vrec.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { -;CHECK: vrecpei32: +;CHECK-LABEL: vrecpei32: ;CHECK: vrecpe.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1) @@ -9,7 +9,7 @@ define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind { } define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind { -;CHECK: vrecpeQi32: +;CHECK-LABEL: vrecpeQi32: ;CHECK: vrecpe.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1) @@ -17,7 +17,7 @@ define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind { } define <2 x float> @vrecpef32(<2 x float>* %A) nounwind { -;CHECK: vrecpef32: +;CHECK-LABEL: vrecpef32: ;CHECK: vrecpe.f32 %tmp1 = load <2 x float>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1) @@ -25,7 +25,7 @@ define <2 x float> @vrecpef32(<2 x float>* %A) nounwind { } define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind { -;CHECK: vrecpeQf32: +;CHECK-LABEL: vrecpeQf32: ;CHECK: vrecpe.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1) @@ -39,7 +39,7 @@ declare <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vrecpsf32: +;CHECK-LABEL: vrecpsf32: ;CHECK: vrecps.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -48,7 +48,7 @@ define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vrecpsQf32: +;CHECK-LABEL: vrecpsQf32: ;CHECK: vrecps.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -60,7 +60,7 @@ declare <2 x float> @llvm.arm.neon.vrecps.v2f32(<2 x float>, <2 x float>) nounwi declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind { -;CHECK: vrsqrtei32: +;CHECK-LABEL: vrsqrtei32: ;CHECK: vrsqrte.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1) @@ -68,7 +68,7 @@ define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind { } define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind { -;CHECK: vrsqrteQi32: +;CHECK-LABEL: vrsqrteQi32: ;CHECK: vrsqrte.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1) @@ -76,7 +76,7 @@ define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind { } define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind { -;CHECK: vrsqrtef32: +;CHECK-LABEL: vrsqrtef32: ;CHECK: vrsqrte.f32 %tmp1 = load <2 x float>* %A %tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1) @@ -84,7 +84,7 @@ define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind { } define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind { -;CHECK: vrsqrteQf32: +;CHECK-LABEL: vrsqrteQf32: ;CHECK: vrsqrte.f32 %tmp1 = load <4 x float>* %A %tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1) @@ -98,7 +98,7 @@ declare <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float>) nounwind readnone declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vrsqrtsf32: +;CHECK-LABEL: vrsqrtsf32: ;CHECK: vrsqrts.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -107,7 +107,7 @@ define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vrsqrtsQf32: +;CHECK-LABEL: vrsqrtsQf32: ;CHECK: vrsqrts.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B diff --git a/test/CodeGen/ARM/vselect_imax.ll b/test/CodeGen/ARM/vselect_imax.ll index 9744f4dde8..9ea56a47bd 100644 --- a/test/CodeGen/ARM/vselect_imax.ll +++ b/test/CodeGen/ARM/vselect_imax.ll @@ -15,7 +15,7 @@ define void @vmax_v4i32(<4 x i32>* %m, <4 x i32> %a, <4 x i32> %b) { ; lowering we also need to adjust the cost. %T0_10 = type <16 x i16> %T1_10 = type <16 x i1> -; CHECK: func_blend10: +; CHECK-LABEL: func_blend10: define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, %T1_10* %blend, %T0_10* %storeaddr) { %v0 = load %T0_10* %loadaddr @@ -31,7 +31,7 @@ define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2, } %T0_14 = type <8 x i32> %T1_14 = type <8 x i1> -; CHECK: func_blend14: +; CHECK-LABEL: func_blend14: define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, %T1_14* %blend, %T0_14* %storeaddr) { %v0 = load %T0_14* %loadaddr @@ -47,7 +47,7 @@ define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2, } %T0_15 = type <16 x i32> %T1_15 = type <16 x i1> -; CHECK: func_blend15: +; CHECK-LABEL: func_blend15: define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, %T1_15* %blend, %T0_15* %storeaddr) { ; CHECK: vbsl @@ -63,7 +63,7 @@ define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2, } %T0_18 = type <4 x i64> %T1_18 = type <4 x i1> -; CHECK: func_blend18: +; CHECK-LABEL: func_blend18: define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2, %T1_18* %blend, %T0_18* %storeaddr) { ; CHECK: vbsl @@ -79,7 +79,7 @@ define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2, } %T0_19 = type <8 x i64> %T1_19 = type <8 x i1> -; CHECK: func_blend19: +; CHECK-LABEL: func_blend19: define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2, %T1_19* %blend, %T0_19* %storeaddr) { ; CHECK: vbsl @@ -97,7 +97,7 @@ define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2, } %T0_20 = type <16 x i64> %T1_20 = type <16 x i1> -; CHECK: func_blend20: +; CHECK-LABEL: func_blend20: define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2, %T1_20* %blend, %T0_20* %storeaddr) { ; CHECK: vbsl diff --git a/test/CodeGen/ARM/vshift.ll b/test/CodeGen/ARM/vshift.ll index f3cbec7457..de380d3d12 100644 --- a/test/CodeGen/ARM/vshift.ll +++ b/test/CodeGen/ARM/vshift.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vshls8: +;CHECK-LABEL: vshls8: ;CHECK: vshl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vshls16: +;CHECK-LABEL: vshls16: ;CHECK: vshl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vshls32: +;CHECK-LABEL: vshls32: ;CHECK: vshl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vshls64: +;CHECK-LABEL: vshls64: ;CHECK: vshl.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { -;CHECK: vshli8: +;CHECK-LABEL: vshli8: ;CHECK: vshl.i8 %tmp1 = load <8 x i8>* %A %tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > @@ -45,7 +45,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { } define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { -;CHECK: vshli16: +;CHECK-LABEL: vshli16: ;CHECK: vshl.i16 %tmp1 = load <4 x i16>* %A %tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 > @@ -53,7 +53,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { } define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { -;CHECK: vshli32: +;CHECK-LABEL: vshli32: ;CHECK: vshl.i32 %tmp1 = load <2 x i32>* %A %tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 > @@ -61,7 +61,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { } define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { -;CHECK: vshli64: +;CHECK-LABEL: vshli64: ;CHECK: vshl.i64 %tmp1 = load <1 x i64>* %A %tmp2 = shl <1 x i64> %tmp1, < i64 63 > @@ -69,7 +69,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { } define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vshlQs8: +;CHECK-LABEL: vshlQs8: ;CHECK: vshl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -78,7 +78,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vshlQs16: +;CHECK-LABEL: vshlQs16: ;CHECK: vshl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -87,7 +87,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vshlQs32: +;CHECK-LABEL: vshlQs32: ;CHECK: vshl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -96,7 +96,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vshlQs64: +;CHECK-LABEL: vshlQs64: ;CHECK: vshl.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -105,7 +105,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { -;CHECK: vshlQi8: +;CHECK-LABEL: vshlQi8: ;CHECK: vshl.i8 %tmp1 = load <16 x i8>* %A %tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 > @@ -113,7 +113,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { } define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { -;CHECK: vshlQi16: +;CHECK-LABEL: vshlQi16: ;CHECK: vshl.i16 %tmp1 = load <8 x i16>* %A %tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 > @@ -121,7 +121,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { } define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { -;CHECK: vshlQi32: +;CHECK-LABEL: vshlQi32: ;CHECK: vshl.i32 %tmp1 = load <4 x i32>* %A %tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 > @@ -129,7 +129,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { } define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { -;CHECK: vshlQi64: +;CHECK-LABEL: vshlQi64: ;CHECK: vshl.i64 %tmp1 = load <2 x i64>* %A %tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 > @@ -137,7 +137,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { } define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vlshru8: +;CHECK-LABEL: vlshru8: ;CHECK: vneg.s8 ;CHECK: vshl.u8 %tmp1 = load <8 x i8>* %A @@ -147,7 +147,7 @@ define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vlshru16: +;CHECK-LABEL: vlshru16: ;CHECK: vneg.s16 ;CHECK: vshl.u16 %tmp1 = load <4 x i16>* %A @@ -157,7 +157,7 @@ define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vlshru32: +;CHECK-LABEL: vlshru32: ;CHECK: vneg.s32 ;CHECK: vshl.u32 %tmp1 = load <2 x i32>* %A @@ -167,7 +167,7 @@ define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vlshru64: +;CHECK-LABEL: vlshru64: ;CHECK: vsub.i64 ;CHECK: vshl.u64 %tmp1 = load <1 x i64>* %A @@ -177,7 +177,7 @@ define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind { -;CHECK: vlshri8: +;CHECK-LABEL: vlshri8: ;CHECK: vshr.u8 %tmp1 = load <8 x i8>* %A %tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > @@ -185,7 +185,7 @@ define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind { } define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind { -;CHECK: vlshri16: +;CHECK-LABEL: vlshri16: ;CHECK: vshr.u16 %tmp1 = load <4 x i16>* %A %tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > @@ -193,7 +193,7 @@ define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind { } define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind { -;CHECK: vlshri32: +;CHECK-LABEL: vlshri32: ;CHECK: vshr.u32 %tmp1 = load <2 x i32>* %A %tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 > @@ -201,7 +201,7 @@ define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind { } define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind { -;CHECK: vlshri64: +;CHECK-LABEL: vlshri64: ;CHECK: vshr.u64 %tmp1 = load <1 x i64>* %A %tmp2 = lshr <1 x i64> %tmp1, < i64 64 > @@ -209,7 +209,7 @@ define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind { } define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vlshrQu8: +;CHECK-LABEL: vlshrQu8: ;CHECK: vneg.s8 ;CHECK: vshl.u8 %tmp1 = load <16 x i8>* %A @@ -219,7 +219,7 @@ define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vlshrQu16: +;CHECK-LABEL: vlshrQu16: ;CHECK: vneg.s16 ;CHECK: vshl.u16 %tmp1 = load <8 x i16>* %A @@ -229,7 +229,7 @@ define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vlshrQu32: +;CHECK-LABEL: vlshrQu32: ;CHECK: vneg.s32 ;CHECK: vshl.u32 %tmp1 = load <4 x i32>* %A @@ -239,7 +239,7 @@ define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vlshrQu64: +;CHECK-LABEL: vlshrQu64: ;CHECK: vsub.i64 ;CHECK: vshl.u64 %tmp1 = load <2 x i64>* %A @@ -249,7 +249,7 @@ define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind { -;CHECK: vlshrQi8: +;CHECK-LABEL: vlshrQi8: ;CHECK: vshr.u8 %tmp1 = load <16 x i8>* %A %tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > @@ -257,7 +257,7 @@ define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind { } define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind { -;CHECK: vlshrQi16: +;CHECK-LABEL: vlshrQi16: ;CHECK: vshr.u16 %tmp1 = load <8 x i16>* %A %tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > @@ -265,7 +265,7 @@ define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind { } define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind { -;CHECK: vlshrQi32: +;CHECK-LABEL: vlshrQi32: ;CHECK: vshr.u32 %tmp1 = load <4 x i32>* %A %tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > @@ -273,7 +273,7 @@ define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind { } define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind { -;CHECK: vlshrQi64: +;CHECK-LABEL: vlshrQi64: ;CHECK: vshr.u64 %tmp1 = load <2 x i64>* %A %tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 > @@ -288,7 +288,7 @@ entry: } define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vashrs8: +;CHECK-LABEL: vashrs8: ;CHECK: vneg.s8 ;CHECK: vshl.s8 %tmp1 = load <8 x i8>* %A @@ -298,7 +298,7 @@ define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vashrs16: +;CHECK-LABEL: vashrs16: ;CHECK: vneg.s16 ;CHECK: vshl.s16 %tmp1 = load <4 x i16>* %A @@ -308,7 +308,7 @@ define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vashrs32: +;CHECK-LABEL: vashrs32: ;CHECK: vneg.s32 ;CHECK: vshl.s32 %tmp1 = load <2 x i32>* %A @@ -318,7 +318,7 @@ define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vashrs64: +;CHECK-LABEL: vashrs64: ;CHECK: vsub.i64 ;CHECK: vshl.s64 %tmp1 = load <1 x i64>* %A @@ -328,7 +328,7 @@ define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vashri8(<8 x i8>* %A) nounwind { -;CHECK: vashri8: +;CHECK-LABEL: vashri8: ;CHECK: vshr.s8 %tmp1 = load <8 x i8>* %A %tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > @@ -336,7 +336,7 @@ define <8 x i8> @vashri8(<8 x i8>* %A) nounwind { } define <4 x i16> @vashri16(<4 x i16>* %A) nounwind { -;CHECK: vashri16: +;CHECK-LABEL: vashri16: ;CHECK: vshr.s16 %tmp1 = load <4 x i16>* %A %tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 > @@ -344,7 +344,7 @@ define <4 x i16> @vashri16(<4 x i16>* %A) nounwind { } define <2 x i32> @vashri32(<2 x i32>* %A) nounwind { -;CHECK: vashri32: +;CHECK-LABEL: vashri32: ;CHECK: vshr.s32 %tmp1 = load <2 x i32>* %A %tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 > @@ -352,7 +352,7 @@ define <2 x i32> @vashri32(<2 x i32>* %A) nounwind { } define <1 x i64> @vashri64(<1 x i64>* %A) nounwind { -;CHECK: vashri64: +;CHECK-LABEL: vashri64: ;CHECK: vshr.s64 %tmp1 = load <1 x i64>* %A %tmp2 = ashr <1 x i64> %tmp1, < i64 64 > @@ -360,7 +360,7 @@ define <1 x i64> @vashri64(<1 x i64>* %A) nounwind { } define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vashrQs8: +;CHECK-LABEL: vashrQs8: ;CHECK: vneg.s8 ;CHECK: vshl.s8 %tmp1 = load <16 x i8>* %A @@ -370,7 +370,7 @@ define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vashrQs16: +;CHECK-LABEL: vashrQs16: ;CHECK: vneg.s16 ;CHECK: vshl.s16 %tmp1 = load <8 x i16>* %A @@ -380,7 +380,7 @@ define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vashrQs32: +;CHECK-LABEL: vashrQs32: ;CHECK: vneg.s32 ;CHECK: vshl.s32 %tmp1 = load <4 x i32>* %A @@ -390,7 +390,7 @@ define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vashrQs64: +;CHECK-LABEL: vashrQs64: ;CHECK: vsub.i64 ;CHECK: vshl.s64 %tmp1 = load <2 x i64>* %A @@ -400,7 +400,7 @@ define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind { -;CHECK: vashrQi8: +;CHECK-LABEL: vashrQi8: ;CHECK: vshr.s8 %tmp1 = load <16 x i8>* %A %tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > @@ -408,7 +408,7 @@ define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind { } define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind { -;CHECK: vashrQi16: +;CHECK-LABEL: vashrQi16: ;CHECK: vshr.s16 %tmp1 = load <8 x i16>* %A %tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > @@ -416,7 +416,7 @@ define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind { } define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind { -;CHECK: vashrQi32: +;CHECK-LABEL: vashrQi32: ;CHECK: vshr.s32 %tmp1 = load <4 x i32>* %A %tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 > @@ -424,7 +424,7 @@ define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind { } define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind { -;CHECK: vashrQi64: +;CHECK-LABEL: vashrQi64: ;CHECK: vshr.s64 %tmp1 = load <2 x i64>* %A %tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 > diff --git a/test/CodeGen/ARM/vshiftins.ll b/test/CodeGen/ARM/vshiftins.ll index 3a4f8574e3..27610bfa67 100644 --- a/test/CodeGen/ARM/vshiftins.ll +++ b/test/CodeGen/ARM/vshiftins.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsli8: +;CHECK-LABEL: vsli8: ;CHECK: vsli.8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsli16: +;CHECK-LABEL: vsli16: ;CHECK: vsli.16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsli32: +;CHECK-LABEL: vsli32: ;CHECK: vsli.32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vsli64: +;CHECK-LABEL: vsli64: ;CHECK: vsli.64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vsliQ8: +;CHECK-LABEL: vsliQ8: ;CHECK: vsli.8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -46,7 +46,7 @@ define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsliQ16: +;CHECK-LABEL: vsliQ16: ;CHECK: vsli.16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -55,7 +55,7 @@ define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsliQ32: +;CHECK-LABEL: vsliQ32: ;CHECK: vsli.32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -64,7 +64,7 @@ define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsliQ64: +;CHECK-LABEL: vsliQ64: ;CHECK: vsli.64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -73,7 +73,7 @@ define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsri8: +;CHECK-LABEL: vsri8: ;CHECK: vsri.8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -82,7 +82,7 @@ define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsri16: +;CHECK-LABEL: vsri16: ;CHECK: vsri.16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -91,7 +91,7 @@ define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsri32: +;CHECK-LABEL: vsri32: ;CHECK: vsri.32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -100,7 +100,7 @@ define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vsri64: +;CHECK-LABEL: vsri64: ;CHECK: vsri.64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -109,7 +109,7 @@ define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vsriQ8: +;CHECK-LABEL: vsriQ8: ;CHECK: vsri.8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -118,7 +118,7 @@ define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsriQ16: +;CHECK-LABEL: vsriQ16: ;CHECK: vsri.16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -127,7 +127,7 @@ define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsriQ32: +;CHECK-LABEL: vsriQ32: ;CHECK: vsri.32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -136,7 +136,7 @@ define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsriQ64: +;CHECK-LABEL: vsriQ64: ;CHECK: vsri.64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vshl.ll b/test/CodeGen/ARM/vshl.ll index 818e71b8ff..462f7fe7fb 100644 --- a/test/CodeGen/ARM/vshl.ll +++ b/test/CodeGen/ARM/vshl.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vshls8: +;CHECK-LABEL: vshls8: ;CHECK: vshl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vshls16: +;CHECK-LABEL: vshls16: ;CHECK: vshl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vshls32: +;CHECK-LABEL: vshls32: ;CHECK: vshl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vshls64: +;CHECK-LABEL: vshls64: ;CHECK: vshl.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vshlu8: +;CHECK-LABEL: vshlu8: ;CHECK: vshl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -46,7 +46,7 @@ define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vshlu16: +;CHECK-LABEL: vshlu16: ;CHECK: vshl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -55,7 +55,7 @@ define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vshlu32: +;CHECK-LABEL: vshlu32: ;CHECK: vshl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -64,7 +64,7 @@ define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vshlu64: +;CHECK-LABEL: vshlu64: ;CHECK: vshl.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -73,7 +73,7 @@ define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vshlQs8: +;CHECK-LABEL: vshlQs8: ;CHECK: vshl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vshlQs16: +;CHECK-LABEL: vshlQs16: ;CHECK: vshl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -91,7 +91,7 @@ define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vshlQs32: +;CHECK-LABEL: vshlQs32: ;CHECK: vshl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vshlQs64: +;CHECK-LABEL: vshlQs64: ;CHECK: vshl.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -109,7 +109,7 @@ define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vshlQu8: +;CHECK-LABEL: vshlQu8: ;CHECK: vshl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -118,7 +118,7 @@ define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vshlQu16: +;CHECK-LABEL: vshlQu16: ;CHECK: vshl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -127,7 +127,7 @@ define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vshlQu32: +;CHECK-LABEL: vshlQu32: ;CHECK: vshl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -136,7 +136,7 @@ define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vshlQu64: +;CHECK-LABEL: vshlQu64: ;CHECK: vshl.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -148,7 +148,7 @@ define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { ; Test a mix of both signed and unsigned intrinsics. define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { -;CHECK: vshli8: +;CHECK-LABEL: vshli8: ;CHECK: vshl.i8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -156,7 +156,7 @@ define <8 x i8> @vshli8(<8 x i8>* %A) nounwind { } define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { -;CHECK: vshli16: +;CHECK-LABEL: vshli16: ;CHECK: vshl.i16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -164,7 +164,7 @@ define <4 x i16> @vshli16(<4 x i16>* %A) nounwind { } define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { -;CHECK: vshli32: +;CHECK-LABEL: vshli32: ;CHECK: vshl.i32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -172,7 +172,7 @@ define <2 x i32> @vshli32(<2 x i32>* %A) nounwind { } define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { -;CHECK: vshli64: +;CHECK-LABEL: vshli64: ;CHECK: vshl.i64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >) @@ -180,7 +180,7 @@ define <1 x i64> @vshli64(<1 x i64>* %A) nounwind { } define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { -;CHECK: vshlQi8: +;CHECK-LABEL: vshlQi8: ;CHECK: vshl.i8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -188,7 +188,7 @@ define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind { } define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { -;CHECK: vshlQi16: +;CHECK-LABEL: vshlQi16: ;CHECK: vshl.i16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >) @@ -196,7 +196,7 @@ define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind { } define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { -;CHECK: vshlQi32: +;CHECK-LABEL: vshlQi32: ;CHECK: vshl.i32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >) @@ -204,7 +204,7 @@ define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind { } define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { -;CHECK: vshlQi64: +;CHECK-LABEL: vshlQi64: ;CHECK: vshl.i64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >) @@ -214,7 +214,7 @@ define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind { ; Right shift by immediate: define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind { -;CHECK: vshrs8: +;CHECK-LABEL: vshrs8: ;CHECK: vshr.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -222,7 +222,7 @@ define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind { } define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind { -;CHECK: vshrs16: +;CHECK-LABEL: vshrs16: ;CHECK: vshr.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -230,7 +230,7 @@ define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind { } define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind { -;CHECK: vshrs32: +;CHECK-LABEL: vshrs32: ;CHECK: vshr.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) @@ -238,7 +238,7 @@ define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind { } define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind { -;CHECK: vshrs64: +;CHECK-LABEL: vshrs64: ;CHECK: vshr.s64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) @@ -246,7 +246,7 @@ define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind { } define <8 x i8> @vshru8(<8 x i8>* %A) nounwind { -;CHECK: vshru8: +;CHECK-LABEL: vshru8: ;CHECK: vshr.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -254,7 +254,7 @@ define <8 x i8> @vshru8(<8 x i8>* %A) nounwind { } define <4 x i16> @vshru16(<4 x i16>* %A) nounwind { -;CHECK: vshru16: +;CHECK-LABEL: vshru16: ;CHECK: vshr.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -262,7 +262,7 @@ define <4 x i16> @vshru16(<4 x i16>* %A) nounwind { } define <2 x i32> @vshru32(<2 x i32>* %A) nounwind { -;CHECK: vshru32: +;CHECK-LABEL: vshru32: ;CHECK: vshr.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) @@ -270,7 +270,7 @@ define <2 x i32> @vshru32(<2 x i32>* %A) nounwind { } define <1 x i64> @vshru64(<1 x i64>* %A) nounwind { -;CHECK: vshru64: +;CHECK-LABEL: vshru64: ;CHECK: vshr.u64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) @@ -278,7 +278,7 @@ define <1 x i64> @vshru64(<1 x i64>* %A) nounwind { } define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind { -;CHECK: vshrQs8: +;CHECK-LABEL: vshrQs8: ;CHECK: vshr.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -286,7 +286,7 @@ define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind { -;CHECK: vshrQs16: +;CHECK-LABEL: vshrQs16: ;CHECK: vshr.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -294,7 +294,7 @@ define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind { -;CHECK: vshrQs32: +;CHECK-LABEL: vshrQs32: ;CHECK: vshr.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) @@ -302,7 +302,7 @@ define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind { } define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind { -;CHECK: vshrQs64: +;CHECK-LABEL: vshrQs64: ;CHECK: vshr.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) @@ -310,7 +310,7 @@ define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind { } define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind { -;CHECK: vshrQu8: +;CHECK-LABEL: vshrQu8: ;CHECK: vshr.u8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -318,7 +318,7 @@ define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind { } define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind { -;CHECK: vshrQu16: +;CHECK-LABEL: vshrQu16: ;CHECK: vshr.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -326,7 +326,7 @@ define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind { } define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind { -;CHECK: vshrQu32: +;CHECK-LABEL: vshrQu32: ;CHECK: vshr.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) @@ -334,7 +334,7 @@ define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind { } define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind { -;CHECK: vshrQu64: +;CHECK-LABEL: vshrQu64: ;CHECK: vshr.u64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) @@ -362,7 +362,7 @@ declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>) nounwind re declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrshls8: +;CHECK-LABEL: vrshls8: ;CHECK: vrshl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -371,7 +371,7 @@ define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrshls16: +;CHECK-LABEL: vrshls16: ;CHECK: vrshl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -380,7 +380,7 @@ define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrshls32: +;CHECK-LABEL: vrshls32: ;CHECK: vrshl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -389,7 +389,7 @@ define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vrshls64: +;CHECK-LABEL: vrshls64: ;CHECK: vrshl.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -398,7 +398,7 @@ define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrshlu8: +;CHECK-LABEL: vrshlu8: ;CHECK: vrshl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -407,7 +407,7 @@ define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrshlu16: +;CHECK-LABEL: vrshlu16: ;CHECK: vrshl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -416,7 +416,7 @@ define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrshlu32: +;CHECK-LABEL: vrshlu32: ;CHECK: vrshl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -425,7 +425,7 @@ define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vrshlu64: +;CHECK-LABEL: vrshlu64: ;CHECK: vrshl.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -434,7 +434,7 @@ define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrshlQs8: +;CHECK-LABEL: vrshlQs8: ;CHECK: vrshl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -443,7 +443,7 @@ define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrshlQs16: +;CHECK-LABEL: vrshlQs16: ;CHECK: vrshl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -452,7 +452,7 @@ define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrshlQs32: +;CHECK-LABEL: vrshlQs32: ;CHECK: vrshl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -461,7 +461,7 @@ define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vrshlQs64: +;CHECK-LABEL: vrshlQs64: ;CHECK: vrshl.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -470,7 +470,7 @@ define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrshlQu8: +;CHECK-LABEL: vrshlQu8: ;CHECK: vrshl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -479,7 +479,7 @@ define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrshlQu16: +;CHECK-LABEL: vrshlQu16: ;CHECK: vrshl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -488,7 +488,7 @@ define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrshlQu32: +;CHECK-LABEL: vrshlQu32: ;CHECK: vrshl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -497,7 +497,7 @@ define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vrshlQu64: +;CHECK-LABEL: vrshlQu64: ;CHECK: vrshl.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -506,7 +506,7 @@ define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind { -;CHECK: vrshrs8: +;CHECK-LABEL: vrshrs8: ;CHECK: vrshr.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -514,7 +514,7 @@ define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind { } define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind { -;CHECK: vrshrs16: +;CHECK-LABEL: vrshrs16: ;CHECK: vrshr.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -522,7 +522,7 @@ define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind { } define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind { -;CHECK: vrshrs32: +;CHECK-LABEL: vrshrs32: ;CHECK: vrshr.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) @@ -530,7 +530,7 @@ define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind { } define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind { -;CHECK: vrshrs64: +;CHECK-LABEL: vrshrs64: ;CHECK: vrshr.s64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) @@ -538,7 +538,7 @@ define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind { } define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind { -;CHECK: vrshru8: +;CHECK-LABEL: vrshru8: ;CHECK: vrshr.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -546,7 +546,7 @@ define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind { } define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind { -;CHECK: vrshru16: +;CHECK-LABEL: vrshru16: ;CHECK: vrshr.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -554,7 +554,7 @@ define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind { } define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind { -;CHECK: vrshru32: +;CHECK-LABEL: vrshru32: ;CHECK: vrshr.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >) @@ -562,7 +562,7 @@ define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind { } define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind { -;CHECK: vrshru64: +;CHECK-LABEL: vrshru64: ;CHECK: vrshr.u64 %tmp1 = load <1 x i64>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >) @@ -570,7 +570,7 @@ define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind { } define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind { -;CHECK: vrshrQs8: +;CHECK-LABEL: vrshrQs8: ;CHECK: vrshr.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -578,7 +578,7 @@ define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind { } define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind { -;CHECK: vrshrQs16: +;CHECK-LABEL: vrshrQs16: ;CHECK: vrshr.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -586,7 +586,7 @@ define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind { } define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind { -;CHECK: vrshrQs32: +;CHECK-LABEL: vrshrQs32: ;CHECK: vrshr.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) @@ -594,7 +594,7 @@ define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind { } define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind { -;CHECK: vrshrQs64: +;CHECK-LABEL: vrshrQs64: ;CHECK: vrshr.s64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) @@ -602,7 +602,7 @@ define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind { } define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind { -;CHECK: vrshrQu8: +;CHECK-LABEL: vrshrQu8: ;CHECK: vrshr.u8 %tmp1 = load <16 x i8>* %A %tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >) @@ -610,7 +610,7 @@ define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind { } define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind { -;CHECK: vrshrQu16: +;CHECK-LABEL: vrshrQu16: ;CHECK: vrshr.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >) @@ -618,7 +618,7 @@ define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind { } define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind { -;CHECK: vrshrQu32: +;CHECK-LABEL: vrshrQu32: ;CHECK: vrshr.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >) @@ -626,7 +626,7 @@ define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind { } define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind { -;CHECK: vrshrQu64: +;CHECK-LABEL: vrshrQu64: ;CHECK: vrshr.u64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >) diff --git a/test/CodeGen/ARM/vshll.ll b/test/CodeGen/ARM/vshll.ll index 8e85b98f49..ae80664148 100644 --- a/test/CodeGen/ARM/vshll.ll +++ b/test/CodeGen/ARM/vshll.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { -;CHECK: vshlls8: +;CHECK-LABEL: vshlls8: ;CHECK: vshll.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -9,7 +9,7 @@ define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind { } define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { -;CHECK: vshlls16: +;CHECK-LABEL: vshlls16: ;CHECK: vshll.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -17,7 +17,7 @@ define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind { } define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { -;CHECK: vshlls32: +;CHECK-LABEL: vshlls32: ;CHECK: vshll.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -25,7 +25,7 @@ define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind { } define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { -;CHECK: vshllu8: +;CHECK-LABEL: vshllu8: ;CHECK: vshll.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) @@ -33,7 +33,7 @@ define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind { } define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { -;CHECK: vshllu16: +;CHECK-LABEL: vshllu16: ;CHECK: vshll.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) @@ -41,7 +41,7 @@ define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind { } define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { -;CHECK: vshllu32: +;CHECK-LABEL: vshllu32: ;CHECK: vshll.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) @@ -51,7 +51,7 @@ define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind { ; The following tests use the maximum shift count, so the signedness is ; irrelevant. Test both signed and unsigned versions. define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { -;CHECK: vshlli8: +;CHECK-LABEL: vshlli8: ;CHECK: vshll.i8 %tmp1 = load <8 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >) @@ -59,7 +59,7 @@ define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind { } define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { -;CHECK: vshlli16: +;CHECK-LABEL: vshlli16: ;CHECK: vshll.i16 %tmp1 = load <4 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >) @@ -67,7 +67,7 @@ define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind { } define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind { -;CHECK: vshlli32: +;CHECK-LABEL: vshlli32: ;CHECK: vshll.i32 %tmp1 = load <2 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >) diff --git a/test/CodeGen/ARM/vshrn.ll b/test/CodeGen/ARM/vshrn.ll index e2544f424a..40a94fee0d 100644 --- a/test/CodeGen/ARM/vshrn.ll +++ b/test/CodeGen/ARM/vshrn.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { -;CHECK: vshrns8: +;CHECK-LABEL: vshrns8: ;CHECK: vshrn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -9,7 +9,7 @@ define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { -;CHECK: vshrns16: +;CHECK-LABEL: vshrns16: ;CHECK: vshrn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -17,7 +17,7 @@ define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind { -;CHECK: vshrns32: +;CHECK-LABEL: vshrns32: ;CHECK: vshrn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) @@ -29,7 +29,7 @@ declare <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32>, <4 x i32>) nounwind re declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { -;CHECK: vrshrns8: +;CHECK-LABEL: vrshrns8: ;CHECK: vrshrn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >) @@ -37,7 +37,7 @@ define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind { } define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { -;CHECK: vrshrns16: +;CHECK-LABEL: vrshrns16: ;CHECK: vrshrn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >) @@ -45,7 +45,7 @@ define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind { } define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind { -;CHECK: vrshrns32: +;CHECK-LABEL: vrshrns32: ;CHECK: vrshrn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >) diff --git a/test/CodeGen/ARM/vsra.ll b/test/CodeGen/ARM/vsra.ll index acb672d00f..7a211c31ac 100644 --- a/test/CodeGen/ARM/vsra.ll +++ b/test/CodeGen/ARM/vsra.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsras8: +;CHECK-LABEL: vsras8: ;CHECK: vsra.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -11,7 +11,7 @@ define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsras16: +;CHECK-LABEL: vsras16: ;CHECK: vsra.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -21,7 +21,7 @@ define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsras32: +;CHECK-LABEL: vsras32: ;CHECK: vsra.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -31,7 +31,7 @@ define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vsras64: +;CHECK-LABEL: vsras64: ;CHECK: vsra.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -41,7 +41,7 @@ define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vsraQs8: +;CHECK-LABEL: vsraQs8: ;CHECK: vsra.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -51,7 +51,7 @@ define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsraQs16: +;CHECK-LABEL: vsraQs16: ;CHECK: vsra.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -61,7 +61,7 @@ define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsraQs32: +;CHECK-LABEL: vsraQs32: ;CHECK: vsra.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -71,7 +71,7 @@ define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsraQs64: +;CHECK-LABEL: vsraQs64: ;CHECK: vsra.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -81,7 +81,7 @@ define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsrau8: +;CHECK-LABEL: vsrau8: ;CHECK: vsra.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -91,7 +91,7 @@ define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsrau16: +;CHECK-LABEL: vsrau16: ;CHECK: vsra.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -101,7 +101,7 @@ define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsrau32: +;CHECK-LABEL: vsrau32: ;CHECK: vsra.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -111,7 +111,7 @@ define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vsrau64: +;CHECK-LABEL: vsrau64: ;CHECK: vsra.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -121,7 +121,7 @@ define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vsraQu8: +;CHECK-LABEL: vsraQu8: ;CHECK: vsra.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -131,7 +131,7 @@ define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsraQu16: +;CHECK-LABEL: vsraQu16: ;CHECK: vsra.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -141,7 +141,7 @@ define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsraQu32: +;CHECK-LABEL: vsraQu32: ;CHECK: vsra.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -151,7 +151,7 @@ define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsraQu64: +;CHECK-LABEL: vsraQu64: ;CHECK: vsra.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -161,7 +161,7 @@ define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrsras8: +;CHECK-LABEL: vrsras8: ;CHECK: vrsra.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -171,7 +171,7 @@ define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrsras16: +;CHECK-LABEL: vrsras16: ;CHECK: vrsra.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -181,7 +181,7 @@ define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrsras32: +;CHECK-LABEL: vrsras32: ;CHECK: vrsra.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -191,7 +191,7 @@ define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vrsras64: +;CHECK-LABEL: vrsras64: ;CHECK: vrsra.s64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -201,7 +201,7 @@ define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vrsrau8: +;CHECK-LABEL: vrsrau8: ;CHECK: vrsra.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -211,7 +211,7 @@ define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vrsrau16: +;CHECK-LABEL: vrsrau16: ;CHECK: vrsra.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -221,7 +221,7 @@ define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vrsrau32: +;CHECK-LABEL: vrsrau32: ;CHECK: vrsra.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -231,7 +231,7 @@ define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vrsrau64: +;CHECK-LABEL: vrsrau64: ;CHECK: vrsra.u64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -241,7 +241,7 @@ define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrsraQs8: +;CHECK-LABEL: vrsraQs8: ;CHECK: vrsra.s8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -251,7 +251,7 @@ define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrsraQs16: +;CHECK-LABEL: vrsraQs16: ;CHECK: vrsra.s16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -261,7 +261,7 @@ define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrsraQs32: +;CHECK-LABEL: vrsraQs32: ;CHECK: vrsra.s32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -271,7 +271,7 @@ define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vrsraQs64: +;CHECK-LABEL: vrsraQs64: ;CHECK: vrsra.s64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -281,7 +281,7 @@ define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vrsraQu8: +;CHECK-LABEL: vrsraQu8: ;CHECK: vrsra.u8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -291,7 +291,7 @@ define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrsraQu16: +;CHECK-LABEL: vrsraQu16: ;CHECK: vrsra.u16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -301,7 +301,7 @@ define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrsraQu32: +;CHECK-LABEL: vrsraQu32: ;CHECK: vrsra.u32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -311,7 +311,7 @@ define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vrsraQu64: +;CHECK-LABEL: vrsraQu64: ;CHECK: vrsra.u64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vst1.ll b/test/CodeGen/ARM/vst1.ll index e1f3e88907..36439fd7ad 100644 --- a/test/CodeGen/ARM/vst1.ll +++ b/test/CodeGen/ARM/vst1.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst1i8: +;CHECK-LABEL: vst1i8: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst1.8 {d16}, [r0:64] %tmp1 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind { } define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst1i16: +;CHECK-LABEL: vst1i16: ;CHECK: vst1.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst1i32: +;CHECK-LABEL: vst1i32: ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst1f(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst1f: +;CHECK-LABEL: vst1f: ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -38,7 +38,7 @@ define void @vst1f(float* %A, <2 x float>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind { -;CHECK: vst1f_update: +;CHECK-LABEL: vst1f_update: ;CHECK: vst1.32 {d16}, [r1]! %A = load float** %ptr %tmp0 = bitcast float* %A to i8* @@ -50,7 +50,7 @@ define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind { } define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { -;CHECK: vst1i64: +;CHECK-LABEL: vst1i64: ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = load <1 x i64>* %B @@ -59,7 +59,7 @@ define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind { } define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vst1Qi8: +;CHECK-LABEL: vst1Qi8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.8 {d16, d17}, [r0:64] %tmp1 = load <16 x i8>* %B @@ -68,7 +68,7 @@ define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind { } define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst1Qi16: +;CHECK-LABEL: vst1Qi16: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -79,7 +79,7 @@ define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { -;CHECK: vst1Qi16_update: +;CHECK-LABEL: vst1Qi16_update: ;CHECK: vst1.16 {d16, d17}, [r1:64], r2 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* @@ -91,7 +91,7 @@ define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { } define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst1Qi32: +;CHECK-LABEL: vst1Qi32: ;CHECK: vst1.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B @@ -100,7 +100,7 @@ define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst1Qf: +;CHECK-LABEL: vst1Qf: ;CHECK: vst1.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -109,7 +109,7 @@ define void @vst1Qf(float* %A, <4 x float>* %B) nounwind { } define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind { -;CHECK: vst1Qi64: +;CHECK-LABEL: vst1Qi64: ;CHECK: vst1.64 %tmp0 = bitcast i64* %A to i8* %tmp1 = load <2 x i64>* %B diff --git a/test/CodeGen/ARM/vst2.ll b/test/CodeGen/ARM/vst2.ll index a31f8635fe..af8246325c 100644 --- a/test/CodeGen/ARM/vst2.ll +++ b/test/CodeGen/ARM/vst2.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst2i8: +;CHECK-LABEL: vst2i8: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst2.8 {d16, d17}, [r0:64] %tmp1 = load <8 x i8>* %B @@ -11,7 +11,7 @@ define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { -;CHECK: vst2i8_update: +;CHECK-LABEL: vst2i8_update: ;CHECK: vst2.8 {d16, d17}, [r1], r2 %A = load i8** %ptr %tmp1 = load <8 x i8>* %B @@ -22,7 +22,7 @@ define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { } define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst2i16: +;CHECK-LABEL: vst2i16: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst2.16 {d16, d17}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -32,7 +32,7 @@ define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst2i32: +;CHECK-LABEL: vst2i32: ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -41,7 +41,7 @@ define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst2f(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst2f: +;CHECK-LABEL: vst2f: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -50,7 +50,7 @@ define void @vst2f(float* %A, <2 x float>* %B) nounwind { } define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { -;CHECK: vst2i64: +;CHECK-LABEL: vst2i64: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst1.64 {d16, d17}, [r0:128] %tmp0 = bitcast i64* %A to i8* @@ -61,7 +61,7 @@ define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind { ;Check for a post-increment updating store. define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { -;CHECK: vst2i64_update: +;CHECK-LABEL: vst2i64_update: ;CHECK: vst1.64 {d16, d17}, [r1:64]! %A = load i64** %ptr %tmp0 = bitcast i64* %A to i8* @@ -73,7 +73,7 @@ define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind { } define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vst2Qi8: +;CHECK-LABEL: vst2Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <16 x i8>* %B @@ -82,7 +82,7 @@ define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind { } define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst2Qi16: +;CHECK-LABEL: vst2Qi16: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -92,7 +92,7 @@ define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst2Qi32: +;CHECK-LABEL: vst2Qi32: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* @@ -102,7 +102,7 @@ define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst2Qf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst2Qf: +;CHECK-LABEL: vst2Qf: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B diff --git a/test/CodeGen/ARM/vst3.ll b/test/CodeGen/ARM/vst3.ll index 281bb730fe..91eb7fce2b 100644 --- a/test/CodeGen/ARM/vst3.ll +++ b/test/CodeGen/ARM/vst3.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst3i8: +;CHECK-LABEL: vst3i8: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] @@ -11,7 +11,7 @@ define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind { } define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst3i16: +;CHECK-LABEL: vst3i16: ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B @@ -20,7 +20,7 @@ define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst3i32: +;CHECK-LABEL: vst3i32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -30,7 +30,7 @@ define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind { ;Check for a post-increment updating store. define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind { -;CHECK: vst3i32_update: +;CHECK-LABEL: vst3i32_update: ;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* @@ -42,7 +42,7 @@ define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind { } define void @vst3f(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst3f: +;CHECK-LABEL: vst3f: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -51,7 +51,7 @@ define void @vst3f(float* %A, <2 x float>* %B) nounwind { } define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { -;CHECK: vst3i64: +;CHECK-LABEL: vst3i64: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64] @@ -62,7 +62,7 @@ define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind { } define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vst3Qi8: +;CHECK-LABEL: vst3Qi8: ;Check the alignment value. Max for this instruction is 64 bits: ;This test runs at -O0 so do not check for specific register numbers. ;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]! @@ -73,7 +73,7 @@ define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind { } define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst3Qi16: +;CHECK-LABEL: vst3Qi16: ;CHECK: vst3.16 ;CHECK: vst3.16 %tmp0 = bitcast i16* %A to i8* @@ -84,7 +84,7 @@ define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind { ;Check for a post-increment updating store. define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind { -;CHECK: vst3Qi16_update: +;CHECK-LABEL: vst3Qi16_update: ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! ;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]! %A = load i16** %ptr @@ -97,7 +97,7 @@ define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind { } define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst3Qi32: +;CHECK-LABEL: vst3Qi32: ;CHECK: vst3.32 ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* @@ -107,7 +107,7 @@ define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst3Qf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst3Qf: +;CHECK-LABEL: vst3Qf: ;CHECK: vst3.32 ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* diff --git a/test/CodeGen/ARM/vst4.ll b/test/CodeGen/ARM/vst4.ll index 7dedb2fafe..ef5c83a57d 100644 --- a/test/CodeGen/ARM/vst4.ll +++ b/test/CodeGen/ARM/vst4.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst4i8: +;CHECK-LABEL: vst4i8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64] %tmp1 = load <8 x i8>* %B @@ -11,7 +11,7 @@ define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { -;CHECK: vst4i8_update: +;CHECK-LABEL: vst4i8_update: ;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2 %A = load i8** %ptr %tmp1 = load <8 x i8>* %B @@ -22,7 +22,7 @@ define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind { } define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst4i16: +;CHECK-LABEL: vst4i16: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128] %tmp0 = bitcast i16* %A to i8* @@ -32,7 +32,7 @@ define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst4i32: +;CHECK-LABEL: vst4i32: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i32* %A to i8* @@ -42,7 +42,7 @@ define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst4f(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst4f: +;CHECK-LABEL: vst4f: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -51,7 +51,7 @@ define void @vst4f(float* %A, <2 x float>* %B) nounwind { } define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { -;CHECK: vst4i64: +;CHECK-LABEL: vst4i64: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256] %tmp0 = bitcast i64* %A to i8* @@ -61,7 +61,7 @@ define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind { } define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vst4Qi8: +;CHECK-LABEL: vst4Qi8: ;Check the alignment value. Max for this instruction is 256 bits: ;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]! ;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256] @@ -71,7 +71,7 @@ define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind { } define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst4Qi16: +;CHECK-LABEL: vst4Qi16: ;Check for no alignment specifier. ;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]! ;CHECK: vst4.16 {d17, d19, d21, d23}, [r0] @@ -82,7 +82,7 @@ define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst4Qi32: +;CHECK-LABEL: vst4Qi32: ;CHECK: vst4.32 ;CHECK: vst4.32 %tmp0 = bitcast i32* %A to i8* @@ -92,7 +92,7 @@ define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst4Qf: +;CHECK-LABEL: vst4Qf: ;CHECK: vst4.32 ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* @@ -103,7 +103,7 @@ define void @vst4Qf(float* %A, <4 x float>* %B) nounwind { ;Check for a post-increment updating store. define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind { -;CHECK: vst4Qf_update: +;CHECK-LABEL: vst4Qf_update: ;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]! ;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]! %A = load float** %ptr diff --git a/test/CodeGen/ARM/vstlane.ll b/test/CodeGen/ARM/vstlane.ll index 67f251f706..651b6d5c47 100644 --- a/test/CodeGen/ARM/vstlane.ll +++ b/test/CodeGen/ARM/vstlane.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst1lanei8: +;CHECK-LABEL: vst1lanei8: ;Check the (default) alignment. ;CHECK: vst1.8 {d16[3]}, [r0] %tmp1 = load <8 x i8>* %B @@ -12,7 +12,7 @@ define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { -;CHECK: vst1lanei8_update: +;CHECK-LABEL: vst1lanei8_update: ;CHECK: vst1.8 {d16[3]}, [r2]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B @@ -24,7 +24,7 @@ define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { } define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst1lanei16: +;CHECK-LABEL: vst1lanei16: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vst1.16 {d16[2]}, [r0:16] %tmp1 = load <4 x i16>* %B @@ -34,7 +34,7 @@ define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst1lanei32: +;CHECK-LABEL: vst1lanei32: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x i32>* %B @@ -44,7 +44,7 @@ define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst1lanef: +;CHECK-LABEL: vst1lanef: ;CHECK: vst1.32 {d16[1]}, [r0:32] %tmp1 = load <2 x float>* %B %tmp2 = extractelement <2 x float> %tmp1, i32 1 @@ -53,7 +53,7 @@ define void @vst1lanef(float* %A, <2 x float>* %B) nounwind { } define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { -;CHECK: vst1laneQi8: +;CHECK-LABEL: vst1laneQi8: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.8 {d17[1]}, [r0] %tmp1 = load <16 x i8>* %B @@ -63,7 +63,7 @@ define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind { } define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst1laneQi16: +;CHECK-LABEL: vst1laneQi16: ;CHECK: vst1.16 {d17[1]}, [r0:16] %tmp1 = load <8 x i16>* %B %tmp2 = extractelement <8 x i16> %tmp1, i32 5 @@ -72,7 +72,7 @@ define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst1laneQi32: +;CHECK-LABEL: vst1laneQi32: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r0:32] %tmp1 = load <4 x i32>* %B @@ -83,7 +83,7 @@ define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check for a post-increment updating store. define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { -;CHECK: vst1laneQi32_update: +;CHECK-LABEL: vst1laneQi32_update: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r1:32]! %A = load i32** %ptr @@ -96,7 +96,7 @@ define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { } define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst1laneQf: +;CHECK-LABEL: vst1laneQf: ; // Can use scalar load. No need to use vectors. ; // CHE-CK: vst1.32 {d17[1]}, [r0] %tmp1 = load <4 x float>* %B @@ -106,7 +106,7 @@ define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind { } define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst2lanei8: +;CHECK-LABEL: vst2lanei8: ;Check the alignment value. Max for this instruction is 16 bits: ;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16] %tmp1 = load <8 x i8>* %B @@ -115,7 +115,7 @@ define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind { } define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst2lanei16: +;CHECK-LABEL: vst2lanei16: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32] %tmp0 = bitcast i16* %A to i8* @@ -126,7 +126,7 @@ define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind { ;Check for a post-increment updating store with register increment. define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { -;CHECK: vst2lanei16_update: +;CHECK-LABEL: vst2lanei16_update: ;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2 %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* @@ -138,7 +138,7 @@ define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind { } define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst2lanei32: +;CHECK-LABEL: vst2lanei32: ;CHECK: vst2.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -147,7 +147,7 @@ define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst2lanef: +;CHECK-LABEL: vst2lanef: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -156,7 +156,7 @@ define void @vst2lanef(float* %A, <2 x float>* %B) nounwind { } define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst2laneQi16: +;CHECK-LABEL: vst2laneQi16: ;Check the (default) alignment. ;CHECK: vst2.16 {d17[1], d19[1]}, [r0] %tmp0 = bitcast i16* %A to i8* @@ -166,7 +166,7 @@ define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst2laneQi32: +;CHECK-LABEL: vst2laneQi32: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64] %tmp0 = bitcast i32* %A to i8* @@ -176,7 +176,7 @@ define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst2laneQf: +;CHECK-LABEL: vst2laneQf: ;CHECK: vst2.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -194,7 +194,7 @@ declare void @llvm.arm.neon.vst2lane.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32) declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst3lanei8: +;CHECK-LABEL: vst3lanei8: ;CHECK: vst3.8 %tmp1 = load <8 x i8>* %B call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1) @@ -202,7 +202,7 @@ define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind { } define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst3lanei16: +;CHECK-LABEL: vst3lanei16: ;Check the (default) alignment value. VST3 does not support alignment. ;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0] %tmp0 = bitcast i16* %A to i8* @@ -212,7 +212,7 @@ define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst3lanei32: +;CHECK-LABEL: vst3lanei32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <2 x i32>* %B @@ -221,7 +221,7 @@ define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst3lanef: +;CHECK-LABEL: vst3lanef: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -230,7 +230,7 @@ define void @vst3lanef(float* %A, <2 x float>* %B) nounwind { } define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst3laneQi16: +;CHECK-LABEL: vst3laneQi16: ;Check the (default) alignment value. VST3 does not support alignment. ;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0] %tmp0 = bitcast i16* %A to i8* @@ -240,7 +240,7 @@ define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst3laneQi32: +;CHECK-LABEL: vst3laneQi32: ;CHECK: vst3.32 %tmp0 = bitcast i32* %A to i8* %tmp1 = load <4 x i32>* %B @@ -250,7 +250,7 @@ define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind { ;Check for a post-increment updating store. define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { -;CHECK: vst3laneQi32_update: +;CHECK-LABEL: vst3laneQi32_update: ;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]! %A = load i32** %ptr %tmp0 = bitcast i32* %A to i8* @@ -262,7 +262,7 @@ define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind { } define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst3laneQf: +;CHECK-LABEL: vst3laneQf: ;CHECK: vst3.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -281,7 +281,7 @@ declare void @llvm.arm.neon.vst3lane.v4f32(i8*, <4 x float>, <4 x float>, <4 x f define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { -;CHECK: vst4lanei8: +;CHECK-LABEL: vst4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32] %tmp1 = load <8 x i8>* %B @@ -291,7 +291,7 @@ define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;Check for a post-increment updating store. define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { -;CHECK: vst4lanei8_update: +;CHECK-LABEL: vst4lanei8_update: ;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]! %A = load i8** %ptr %tmp1 = load <8 x i8>* %B @@ -302,7 +302,7 @@ define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind { } define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { -;CHECK: vst4lanei16: +;CHECK-LABEL: vst4lanei16: ;CHECK: vst4.16 %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B @@ -311,7 +311,7 @@ define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind { } define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { -;CHECK: vst4lanei32: +;CHECK-LABEL: vst4lanei32: ;Check the alignment value. Max for this instruction is 128 bits: ;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128] %tmp0 = bitcast i32* %A to i8* @@ -321,7 +321,7 @@ define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind { } define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { -;CHECK: vst4lanef: +;CHECK-LABEL: vst4lanef: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <2 x float>* %B @@ -330,7 +330,7 @@ define void @vst4lanef(float* %A, <2 x float>* %B) nounwind { } define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { -;CHECK: vst4laneQi16: +;CHECK-LABEL: vst4laneQi16: ;Check the alignment value. Max for this instruction is 64 bits: ;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64] %tmp0 = bitcast i16* %A to i8* @@ -340,7 +340,7 @@ define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind { } define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { -;CHECK: vst4laneQi32: +;CHECK-LABEL: vst4laneQi32: ;Check the (default) alignment. ;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] %tmp0 = bitcast i32* %A to i8* @@ -350,7 +350,7 @@ define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind { } define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { -;CHECK: vst4laneQf: +;CHECK-LABEL: vst4laneQf: ;CHECK: vst4.32 %tmp0 = bitcast float* %A to i8* %tmp1 = load <4 x float>* %B @@ -360,7 +360,7 @@ define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind { ; Make sure this doesn't crash; PR10258 define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone { -;CHECK: variable_insertelement: +;CHECK-LABEL: variable_insertelement: %r = insertelement <8 x i16> %a, i16 %b, i32 %c ret <8 x i16> %r } diff --git a/test/CodeGen/ARM/vsub.ll b/test/CodeGen/ARM/vsub.ll index df77bb31fc..89c3095ab2 100644 --- a/test/CodeGen/ARM/vsub.ll +++ b/test/CodeGen/ARM/vsub.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsubi8: +;CHECK-LABEL: vsubi8: ;CHECK: vsub.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsubi16: +;CHECK-LABEL: vsubi16: ;CHECK: vsub.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -19,7 +19,7 @@ define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsubi32: +;CHECK-LABEL: vsubi32: ;CHECK: vsub.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -28,7 +28,7 @@ define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { -;CHECK: vsubi64: +;CHECK-LABEL: vsubi64: ;CHECK: vsub.i64 %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B @@ -37,7 +37,7 @@ define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vsubf32: +;CHECK-LABEL: vsubf32: ;CHECK: vsub.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B @@ -46,7 +46,7 @@ define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vsubQi8: +;CHECK-LABEL: vsubQi8: ;CHECK: vsub.i8 %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -55,7 +55,7 @@ define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsubQi16: +;CHECK-LABEL: vsubQi16: ;CHECK: vsub.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -64,7 +64,7 @@ define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsubQi32: +;CHECK-LABEL: vsubQi32: ;CHECK: vsub.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -73,7 +73,7 @@ define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsubQi64: +;CHECK-LABEL: vsubQi64: ;CHECK: vsub.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -82,7 +82,7 @@ define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { } define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vsubQf32: +;CHECK-LABEL: vsubQf32: ;CHECK: vsub.f32 %tmp1 = load <4 x float>* %A %tmp2 = load <4 x float>* %B @@ -91,7 +91,7 @@ define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind { } define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vsubhni16: +;CHECK-LABEL: vsubhni16: ;CHECK: vsubhn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -100,7 +100,7 @@ define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vsubhni32: +;CHECK-LABEL: vsubhni32: ;CHECK: vsubhn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -109,7 +109,7 @@ define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vsubhni64: +;CHECK-LABEL: vsubhni64: ;CHECK: vsubhn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -122,7 +122,7 @@ declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind rea declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vrsubhni16: +;CHECK-LABEL: vrsubhni16: ;CHECK: vrsubhn.i16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -131,7 +131,7 @@ define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vrsubhni32: +;CHECK-LABEL: vrsubhni32: ;CHECK: vrsubhn.i32 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -140,7 +140,7 @@ define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind { -;CHECK: vrsubhni64: +;CHECK-LABEL: vrsubhni64: ;CHECK: vrsubhn.i64 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B @@ -153,7 +153,7 @@ declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind re declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsubls8: +;CHECK-LABEL: vsubls8: ;CHECK: vsubl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -164,7 +164,7 @@ define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsubls16: +;CHECK-LABEL: vsubls16: ;CHECK: vsubl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -175,7 +175,7 @@ define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsubls32: +;CHECK-LABEL: vsubls32: ;CHECK: vsubl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -186,7 +186,7 @@ define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsublu8: +;CHECK-LABEL: vsublu8: ;CHECK: vsubl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -197,7 +197,7 @@ define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsublu16: +;CHECK-LABEL: vsublu16: ;CHECK: vsubl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -208,7 +208,7 @@ define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsublu32: +;CHECK-LABEL: vsublu32: ;CHECK: vsubl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B @@ -219,7 +219,7 @@ define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsubws8: +;CHECK-LABEL: vsubws8: ;CHECK: vsubw.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -229,7 +229,7 @@ define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsubws16: +;CHECK-LABEL: vsubws16: ;CHECK: vsubw.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -239,7 +239,7 @@ define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsubws32: +;CHECK-LABEL: vsubws32: ;CHECK: vsubw.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B @@ -249,7 +249,7 @@ define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { -;CHECK: vsubwu8: +;CHECK-LABEL: vsubwu8: ;CHECK: vsubw.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i8>* %B @@ -259,7 +259,7 @@ define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind { } define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { -;CHECK: vsubwu16: +;CHECK-LABEL: vsubwu16: ;CHECK: vsubw.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i16>* %B @@ -269,7 +269,7 @@ define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind { } define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind { -;CHECK: vsubwu32: +;CHECK-LABEL: vsubwu32: ;CHECK: vsubw.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i32>* %B diff --git a/test/CodeGen/ARM/vtbl.ll b/test/CodeGen/ARM/vtbl.ll index 926498739e..21614b044f 100644 --- a/test/CodeGen/ARM/vtbl.ll +++ b/test/CodeGen/ARM/vtbl.ll @@ -5,7 +5,7 @@ %struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vtbl1: +;CHECK-LABEL: vtbl1: ;CHECK: vtbl.8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -14,7 +14,7 @@ define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind { -;CHECK: vtbl2: +;CHECK-LABEL: vtbl2: ;CHECK: vtbl.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x2_t* %B @@ -25,7 +25,7 @@ define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind { } define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind { -;CHECK: vtbl3: +;CHECK-LABEL: vtbl3: ;CHECK: vtbl.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x3_t* %B @@ -37,7 +37,7 @@ define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind { } define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind { -;CHECK: vtbl4: +;CHECK-LABEL: vtbl4: ;CHECK: vtbl.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x4_t* %B @@ -50,7 +50,7 @@ define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind { } define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { -;CHECK: vtbx1: +;CHECK-LABEL: vtbx1: ;CHECK: vtbx.8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -60,7 +60,7 @@ define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { } define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind { -;CHECK: vtbx2: +;CHECK-LABEL: vtbx2: ;CHECK: vtbx.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x2_t* %B @@ -72,7 +72,7 @@ define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C } define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind { -;CHECK: vtbx3: +;CHECK-LABEL: vtbx3: ;CHECK: vtbx.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x3_t* %B @@ -85,7 +85,7 @@ define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C } define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind { -;CHECK: vtbx4: +;CHECK-LABEL: vtbx4: ;CHECK: vtbx.8 %tmp1 = load <8 x i8>* %A %tmp2 = load %struct.__neon_int8x8x4_t* %B diff --git a/test/CodeGen/ARM/vtrn.ll b/test/CodeGen/ARM/vtrn.ll index b1c2f93b47..7d101bc619 100644 --- a/test/CodeGen/ARM/vtrn.ll +++ b/test/CodeGen/ARM/vtrn.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vtrni8: +;CHECK-LABEL: vtrni8: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -13,7 +13,7 @@ define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vtrni16: +;CHECK-LABEL: vtrni16: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <4 x i16>* %A @@ -25,7 +25,7 @@ define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { -;CHECK: vtrni32: +;CHECK-LABEL: vtrni32: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.i32 %tmp1 = load <2 x i32>* %A @@ -37,7 +37,7 @@ define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { -;CHECK: vtrnf: +;CHECK-LABEL: vtrnf: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.f32 %tmp1 = load <2 x float>* %A @@ -49,7 +49,7 @@ define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind { } define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vtrnQi8: +;CHECK-LABEL: vtrnQi8: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <16 x i8>* %A @@ -61,7 +61,7 @@ define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vtrnQi16: +;CHECK-LABEL: vtrnQi16: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <8 x i16>* %A @@ -73,7 +73,7 @@ define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vtrnQi32: +;CHECK-LABEL: vtrnQi32: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.i32 %tmp1 = load <4 x i32>* %A @@ -85,7 +85,7 @@ define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vtrnQf: +;CHECK-LABEL: vtrnQf: ;CHECK: vtrn.32 ;CHECK-NEXT: vadd.f32 %tmp1 = load <4 x float>* %A @@ -99,7 +99,7 @@ define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; Undef shuffle indices should not prevent matching to VTRN: define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vtrni8_undef: +;CHECK-LABEL: vtrni8_undef: ;CHECK: vtrn.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -111,7 +111,7 @@ define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vtrnQi16_undef: +;CHECK-LABEL: vtrnQi16_undef: ;CHECK: vtrn.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <8 x i16>* %A diff --git a/test/CodeGen/ARM/vuzp.ll b/test/CodeGen/ARM/vuzp.ll index 9130f62891..2d193c1141 100644 --- a/test/CodeGen/ARM/vuzp.ll +++ b/test/CodeGen/ARM/vuzp.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vuzpi8: +;CHECK-LABEL: vuzpi8: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -13,7 +13,7 @@ define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vuzpi16: +;CHECK-LABEL: vuzpi16: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <4 x i16>* %A @@ -27,7 +27,7 @@ define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors. define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vuzpQi8: +;CHECK-LABEL: vuzpQi8: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <16 x i8>* %A @@ -39,7 +39,7 @@ define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vuzpQi16: +;CHECK-LABEL: vuzpQi16: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <8 x i16>* %A @@ -51,7 +51,7 @@ define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vuzpQi32: +;CHECK-LABEL: vuzpQi32: ;CHECK: vuzp.32 ;CHECK-NEXT: vadd.i32 %tmp1 = load <4 x i32>* %A @@ -63,7 +63,7 @@ define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vuzpQf: +;CHECK-LABEL: vuzpQf: ;CHECK: vuzp.32 ;CHECK-NEXT: vadd.f32 %tmp1 = load <4 x float>* %A @@ -77,7 +77,7 @@ define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; Undef shuffle indices should not prevent matching to VUZP: define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vuzpi8_undef: +;CHECK-LABEL: vuzpi8_undef: ;CHECK: vuzp.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -89,7 +89,7 @@ define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vuzpQi16_undef: +;CHECK-LABEL: vuzpQi16_undef: ;CHECK: vuzp.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <8 x i16>* %A diff --git a/test/CodeGen/ARM/vzip.ll b/test/CodeGen/ARM/vzip.ll index 926970aeb2..f71aef7ef1 100644 --- a/test/CodeGen/ARM/vzip.ll +++ b/test/CodeGen/ARM/vzip.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vzipi8: +;CHECK-LABEL: vzipi8: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -13,7 +13,7 @@ define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: vzipi16: +;CHECK-LABEL: vzipi16: ;CHECK: vzip.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <4 x i16>* %A @@ -27,7 +27,7 @@ define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors. define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vzipQi8: +;CHECK-LABEL: vzipQi8: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <16 x i8>* %A @@ -39,7 +39,7 @@ define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: vzipQi16: +;CHECK-LABEL: vzipQi16: ;CHECK: vzip.16 ;CHECK-NEXT: vadd.i16 %tmp1 = load <8 x i16>* %A @@ -51,7 +51,7 @@ define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: vzipQi32: +;CHECK-LABEL: vzipQi32: ;CHECK: vzip.32 ;CHECK-NEXT: vadd.i32 %tmp1 = load <4 x i32>* %A @@ -63,7 +63,7 @@ define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { -;CHECK: vzipQf: +;CHECK-LABEL: vzipQf: ;CHECK: vzip.32 ;CHECK-NEXT: vadd.f32 %tmp1 = load <4 x float>* %A @@ -77,7 +77,7 @@ define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind { ; Undef shuffle indices should not prevent matching to VZIP: define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: vzipi8_undef: +;CHECK-LABEL: vzipi8_undef: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <8 x i8>* %A @@ -89,7 +89,7 @@ define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: vzipQi8_undef: +;CHECK-LABEL: vzipQi8_undef: ;CHECK: vzip.8 ;CHECK-NEXT: vadd.i8 %tmp1 = load <16 x i8>* %A |