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author | Evan Cheng <evan.cheng@apple.com> | 2009-11-20 00:54:03 +0000 |
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committer | Evan Cheng <evan.cheng@apple.com> | 2009-11-20 00:54:03 +0000 |
commit | 9ef4835bd879e1baa5f59619b958cae57d516481 (patch) | |
tree | a92c5b03466fc6a72adc55458cc67c6135576bbe /test/CodeGen/ARM | |
parent | 8783e401a3ad187dcd0f306153f9339f7270621d (diff) | |
download | llvm-9ef4835bd879e1baa5f59619b958cae57d516481.tar.gz llvm-9ef4835bd879e1baa5f59619b958cae57d516481.tar.bz2 llvm-9ef4835bd879e1baa5f59619b958cae57d516481.tar.xz |
Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89423 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
-rw-r--r-- | test/CodeGen/ARM/remat.ll | 2 | ||||
-rw-r--r-- | test/CodeGen/ARM/select-imm.ll | 48 |
2 files changed, 49 insertions, 1 deletions
diff --git a/test/CodeGen/ARM/remat.ll b/test/CodeGen/ARM/remat.ll index 50da997ed4..9565c8bca6 100644 --- a/test/CodeGen/ARM/remat.ll +++ b/test/CodeGen/ARM/remat.ll @@ -1,5 +1,5 @@ ; RUN: llc < %s -mtriple=arm-apple-darwin -; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 5 +; RUN: llc < %s -mtriple=arm-apple-darwin -stats -info-output-file - | grep "Number of re-materialization" | grep 3 %struct.CONTENTBOX = type { i32, i32, i32, i32, i32 } %struct.LOCBOX = type { i32, i32, i32, i32 } diff --git a/test/CodeGen/ARM/select-imm.ll b/test/CodeGen/ARM/select-imm.ll new file mode 100644 index 0000000000..07edc91519 --- /dev/null +++ b/test/CodeGen/ARM/select-imm.ll @@ -0,0 +1,48 @@ +; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM +; RUN: llc < %s -march=arm -mattr=+thumb2 | FileCheck %s --check-prefix=T2 + +define arm_apcscc i32 @t1(i32 %c) nounwind readnone { +entry: +; ARM: t1: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movgt r0, #123 + +; T2: t1: +; T2: movw r0, #357 +; T2: movgt r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 123, i32 357 + ret i32 %1 +} + +define arm_apcscc i32 @t2(i32 %c) nounwind readnone { +entry: +; ARM: t2: +; ARM: mov r1, #101 +; ARM: orr r1, r1, #1, 24 +; ARM: movle r0, #123 + +; T2: t2: +; T2: movw r0, #357 +; T2: movle r0, #123 + + %0 = icmp sgt i32 %c, 1 + %1 = select i1 %0, i32 357, i32 123 + ret i32 %1 +} + +define arm_apcscc i32 @t3(i32 %a) nounwind readnone { +entry: +; ARM: t3: +; ARM: mov r0, #0 +; ARM: moveq r0, #1 + +; T2: t3: +; T2: mov r0, #0 +; T2: moveq r0, #1 + %0 = icmp eq i32 %a, 160 + %1 = zext i1 %0 to i32 + ret i32 %1 +} |