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| author | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
|---|---|---|
| committer | Stephen Lin <stephenwlin@gmail.com> | 2013-07-13 20:38:47 +0000 |
| commit | b4dc0233c9f70e8cf946822811f233bb613a02e9 (patch) | |
| tree | 6cb47482e15d250ae95e5c6c96abd2afb56f6fca /test/CodeGen/ARM | |
| parent | ae4e1a94e3fb7d1d2d0eec6eb7d04b74326c8453 (diff) | |
| download | llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.gz llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.bz2 llvm-b4dc0233c9f70e8cf946822811f233bb613a02e9.tar.xz | |
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/ARM')
36 files changed, 195 insertions, 195 deletions
diff --git a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll index ed7dd03320..057c19948c 100644 --- a/test/CodeGen/ARM/2011-04-26-SchedTweak.ll +++ b/test/CodeGen/ARM/2011-04-26-SchedTweak.ll @@ -15,7 +15,7 @@ define i32 @test() nounwind optsize ssp { entry: -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: push ; CHECK-NOT: push %block_size = alloca i32, align 4 diff --git a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll index 113cbfe396..8a65f2e82b 100644 --- a/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll +++ b/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll @@ -6,7 +6,7 @@ @i8_src2 = global <2 x i8> <i8 2, i8 1> define void @test_neon_vector_add_2xi8() nounwind { -; CHECK: test_neon_vector_add_2xi8: +; CHECK-LABEL: test_neon_vector_add_2xi8: %1 = load <2 x i8>* @i8_src1 %2 = load <2 x i8>* @i8_src2 %3 = add <2 x i8> %1, %2 @@ -15,7 +15,7 @@ define void @test_neon_vector_add_2xi8() nounwind { } define void @test_neon_ld_st_volatile_with_ashr_2xi8() { -; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8: +; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8: %1 = load volatile <2 x i8>* @i8_src1 %2 = load volatile <2 x i8>* @i8_src2 %3 = ashr <2 x i8> %1, %2 diff --git a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll index 2ab6a4fcc9..42eb32d14c 100644 --- a/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll +++ b/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll @@ -7,7 +7,7 @@ declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind define void @test_neon_call_return_v2i16() { -; CHECK: test_neon_call_return_v2i16: +; CHECK-LABEL: test_neon_call_return_v2i16: %1 = load <2 x i16>* @src1_v2i16 %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind store <2 x i16> %2, <2 x i16>* @res_v2i16 diff --git a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll index 0d0d03b23e..a263c9c8d6 100644 --- a/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll +++ b/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll @@ -4,7 +4,7 @@ define void @test_sqrt(<4 x float>* %X) nounwind { -; CHECK: test_sqrt: +; CHECK-LABEL: test_sqrt: ; CHECK: movw r1, :lower16:{{.*}} ; CHECK: movt r1, :upper16:{{.*}} @@ -27,7 +27,7 @@ declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly define void @test_cos(<4 x float>* %X) nounwind { -; CHECK: test_cos: +; CHECK-LABEL: test_cos: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -58,7 +58,7 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly define void @test_exp(<4 x float>* %X) nounwind { -; CHECK: test_exp: +; CHECK-LABEL: test_exp: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -89,7 +89,7 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly define void @test_exp2(<4 x float>* %X) nounwind { -; CHECK: test_exp2: +; CHECK-LABEL: test_exp2: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -120,7 +120,7 @@ declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly define void @test_log10(<4 x float>* %X) nounwind { -; CHECK: test_log10: +; CHECK-LABEL: test_log10: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -151,7 +151,7 @@ declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly define void @test_log(<4 x float>* %X) nounwind { -; CHECK: test_log: +; CHECK-LABEL: test_log: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -182,7 +182,7 @@ declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly define void @test_log2(<4 x float>* %X) nounwind { -; CHECK: test_log2: +; CHECK-LABEL: test_log2: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -214,7 +214,7 @@ declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly define void @test_pow(<4 x float>* %X) nounwind { -; CHECK: test_pow: +; CHECK-LABEL: test_pow: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -248,7 +248,7 @@ declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly define void @test_powi(<4 x float>* %X) nounwind { -; CHECK: test_powi: +; CHECK-LABEL: test_powi: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -271,7 +271,7 @@ declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly define void @test_sin(<4 x float>* %X) nounwind { -; CHECK: test_sin: +; CHECK-LABEL: test_sin: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} @@ -302,7 +302,7 @@ declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly define void @test_floor(<4 x float>* %X) nounwind { -; CHECK: test_floor: +; CHECK-LABEL: test_floor: ; CHECK: movw [[reg0:r[0-9]+]], :lower16:{{.*}} ; CHECK: movt [[reg0]], :upper16:{{.*}} diff --git a/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/test/CodeGen/ARM/2012-08-09-neon-extload.ll index 764c58f2e1..a7108253cb 100644 --- a/test/CodeGen/ARM/2012-08-09-neon-extload.ll +++ b/test/CodeGen/ARM/2012-08-09-neon-extload.ll @@ -12,7 +12,7 @@ @var_v2i64 = global <2 x i64> zeroinitializer define void @test_v2i8tov2i32() { -; CHECK: test_v2i8tov2i32: +; CHECK-LABEL: test_v2i8tov2i32: %i8val = load <2 x i8>* @var_v2i8 @@ -26,7 +26,7 @@ define void @test_v2i8tov2i32() { } define void @test_v2i8tov2i64() { -; CHECK: test_v2i8tov2i64: +; CHECK-LABEL: test_v2i8tov2i64: %i8val = load <2 x i8>* @var_v2i8 @@ -44,7 +44,7 @@ define void @test_v2i8tov2i64() { } define void @test_v4i8tov4i16() { -; CHECK: test_v4i8tov4i16: +; CHECK-LABEL: test_v4i8tov4i16: %i8val = load <4 x i8>* @var_v4i8 @@ -59,7 +59,7 @@ define void @test_v4i8tov4i16() { } define void @test_v4i8tov4i32() { -; CHECK: test_v4i8tov4i32: +; CHECK-LABEL: test_v4i8tov4i32: %i8val = load <4 x i8>* @var_v4i8 @@ -73,7 +73,7 @@ define void @test_v4i8tov4i32() { } define void @test_v2i16tov2i32() { -; CHECK: test_v2i16tov2i32: +; CHECK-LABEL: test_v2i16tov2i32: %i16val = load <2 x i16>* @var_v2i16 @@ -88,7 +88,7 @@ define void @test_v2i16tov2i32() { } define void @test_v2i16tov2i64() { -; CHECK: test_v2i16tov2i64: +; CHECK-LABEL: test_v2i16tov2i64: %i16val = load <2 x i16>* @var_v2i16 diff --git a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll index e599f43fad..645e68ba15 100644 --- a/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll +++ b/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll @@ -7,7 +7,7 @@ declare void @llvm.va_start(i8*) nounwind declare void @llvm.va_end(i8*) nounwind -; CHECK: test_byval_8_bytes_alignment: +; CHECK-LABEL: test_byval_8_bytes_alignment: define void @test_byval_8_bytes_alignment(i32 %i, ...) { entry: ; CHECK: stm r0, {r1, r2, r3} @@ -40,7 +40,7 @@ entry: declare void @f(double); -; CHECK: test_byval_8_bytes_alignment_fixed_arg: +; CHECK-LABEL: test_byval_8_bytes_alignment_fixed_arg: ; CHECK-NOT: str r1 ; CHECK: str r3, [sp, #12] ; CHECK: str r2, [sp, #8] diff --git a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll index 478048d096..c9ccc103e2 100644 --- a/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll +++ b/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll @@ -6,7 +6,7 @@ declare i32 @printf(i8*, ...) -; CHECK: test_byval_usage_scheduling: +; CHECK-LABEL: test_byval_usage_scheduling: ; CHECK: str r3, [sp, #12] ; CHECK: str r2, [sp, #8] ; CHECK: vldr d16, [sp, #8] diff --git a/test/CodeGen/ARM/atomic-64bit.ll b/test/CodeGen/ARM/atomic-64bit.ll index 669c56302f..93664e37e6 100644 --- a/test/CodeGen/ARM/atomic-64bit.ll +++ b/test/CodeGen/ARM/atomic-64bit.ll @@ -2,7 +2,7 @@ ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB define i64 @test1(i64* %ptr, i64 %val) { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]] @@ -27,7 +27,7 @@ define i64 @test1(i64* %ptr, i64 %val) { } define i64 @test2(i64* %ptr, i64 %val) { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]] @@ -52,7 +52,7 @@ define i64 @test2(i64* %ptr, i64 %val) { } define i64 @test3(i64* %ptr, i64 %val) { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]] @@ -77,7 +77,7 @@ define i64 @test3(i64* %ptr, i64 %val) { } define i64 @test4(i64* %ptr, i64 %val) { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]] @@ -102,7 +102,7 @@ define i64 @test4(i64* %ptr, i64 %val) { } define i64 @test5(i64* %ptr, i64 %val) { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]] @@ -127,7 +127,7 @@ define i64 @test5(i64* %ptr, i64 %val) { } define i64 @test6(i64* %ptr, i64 %val) { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} @@ -148,7 +148,7 @@ define i64 @test6(i64* %ptr, i64 %val) { } define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: cmp [[REG1]] @@ -178,7 +178,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) { ; Compiles down to cmpxchg ; FIXME: Should compile to a single ldrexd define i64 @test8(i64* %ptr) { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: cmp [[REG1]] ; CHECK: cmpeq [[REG2]] @@ -206,7 +206,7 @@ define i64 @test8(i64* %ptr) { ; Compiles down to atomicrmw xchg; there really isn't any more efficient ; way to write it. define void @test9(i64* %ptr, i64 %val) { -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}} @@ -227,7 +227,7 @@ define void @test9(i64* %ptr, i64 %val) { } define i64 @test10(i64* %ptr, i64 %val) { -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] @@ -254,7 +254,7 @@ define i64 @test10(i64* %ptr, i64 %val) { } define i64 @test11(i64* %ptr, i64 %val) { -; CHECK: test11: +; CHECK-LABEL: test11: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] @@ -282,7 +282,7 @@ define i64 @test11(i64* %ptr, i64 %val) { } define i64 @test12(i64* %ptr, i64 %val) { -; CHECK: test12: +; CHECK-LABEL: test12: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] @@ -309,7 +309,7 @@ define i64 @test12(i64* %ptr, i64 %val) { } define i64 @test13(i64* %ptr, i64 %val) { -; CHECK: test13: +; CHECK-LABEL: test13: ; CHECK: dmb {{ish$}} ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]] ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]] diff --git a/test/CodeGen/ARM/crash-shufflevector.ll b/test/CodeGen/ARM/crash-shufflevector.ll index bdc0e0ea4d..0ae866800c 100644 --- a/test/CodeGen/ARM/crash-shufflevector.ll +++ b/test/CodeGen/ARM/crash-shufflevector.ll @@ -7,4 +7,4 @@ define void @f(<4 x i8> %param1, <4 x i8> %param2) { %z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19> call void @g(<16 x i8> %z) ret void -}
\ No newline at end of file +} diff --git a/test/CodeGen/ARM/dagcombine-concatvector.ll b/test/CodeGen/ARM/dagcombine-concatvector.ll index e9e0fe3239..d8c6c64558 100644 --- a/test/CodeGen/ARM/dagcombine-concatvector.ll +++ b/test/CodeGen/ARM/dagcombine-concatvector.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s ; PR15525 -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: ldr.w [[REG:r[0-9]+]], [sp] ; CHECK-NEXT: vmov {{d[0-9]+}}, r1, r2 ; CHECK-NEXT: vmov {{d[0-9]+}}, r3, [[REG]] diff --git a/test/CodeGen/ARM/domain-conv-vmovs.ll b/test/CodeGen/ARM/domain-conv-vmovs.ll index b5586cc99f..d6528db741 100644 --- a/test/CodeGen/ARM/domain-conv-vmovs.ll +++ b/test/CodeGen/ARM/domain-conv-vmovs.ll @@ -1,7 +1,7 @@ ; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) { -; CHECK: test_vmovs_via_vext_lane0to0: +; CHECK-LABEL: test_vmovs_via_vext_lane0to0: %vec = insertelement <2 x float> %in, float %arg, i32 0 %res = fadd <2 x float> %vec, %vec @@ -13,7 +13,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) { } define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) { -; CHECK: test_vmovs_via_vext_lane0to1: +; CHECK-LABEL: test_vmovs_via_vext_lane0to1: %vec = insertelement <2 x float> %in, float %arg, i32 1 %res = fadd <2 x float> %vec, %vec @@ -25,7 +25,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) { } define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) { -; CHECK: test_vmovs_via_vext_lane1to0: +; CHECK-LABEL: test_vmovs_via_vext_lane1to0: %vec = insertelement <2 x float> %in, float %arg, i32 0 %res = fadd <2 x float> %vec, %vec @@ -37,7 +37,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> } define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) { -; CHECK: test_vmovs_via_vext_lane1to1: +; CHECK-LABEL: test_vmovs_via_vext_lane1to1: %vec = insertelement <2 x float> %in, float %arg, i32 1 %res = fadd <2 x float> %vec, %vec @@ -50,7 +50,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) { -; CHECK: test_vmovs_via_vdup: +; CHECK-LABEL: test_vmovs_via_vdup: ; Do an operation (which will end up NEON because of +neonfp) to convince the ; execution-domain pass that NEON is a good thing to use. @@ -68,7 +68,7 @@ declare void @bar() ; This is a comp define float @test_ineligible(float, float %in) { -; CHECK: test_ineligible: +; CHECK-LABEL: test_ineligible: %sqrt = call float @llvm.sqrt.f32(float %in) %val = fadd float %sqrt, %sqrt @@ -85,7 +85,7 @@ define float @test_ineligible(float, float %in) { } define i32 @test_vmovs_no_sreg(i32 %in) { -; CHECK: test_vmovs_no_sreg: +; CHECK-LABEL: test_vmovs_no_sreg: ; Check that the movement to and from GPRs takes place in the NEON domain. ; CHECK: vmov.32 d diff --git a/test/CodeGen/ARM/fabs-neon.ll b/test/CodeGen/ARM/fabs-neon.ll index 614117ff7b..e3094aaf57 100644 --- a/test/CodeGen/ARM/fabs-neon.ll +++ b/test/CodeGen/ARM/fabs-neon.ll @@ -1,6 +1,6 @@ ; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s -; CHECK: test: +; CHECK-LABEL: test: ; CHECK: vabs.f32 q0, q0 define <4 x float> @test(<4 x float> %a) { %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a) @@ -8,7 +8,7 @@ define <4 x float> @test(<4 x float> %a) { } declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a) -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: vabs.f32 d0, d0 define <2 x float> @test2(<2 x float> %a) { %foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a) diff --git a/test/CodeGen/ARM/fabss.ll b/test/CodeGen/ARM/fabss.ll index c3e00ce470..77c21c5be9 100644 --- a/test/CodeGen/ARM/fabss.ll +++ b/test/CodeGen/ARM/fabss.ll @@ -13,17 +13,17 @@ entry: declare float @fabsf(float) -; VFP2: test: +; VFP2-LABEL: test: ; VFP2: vabs.f32 s -; NFP1: test: +; NFP1-LABEL: test: ; NFP1: vabs.f32 d -; NFP0: test: +; NFP0-LABEL: test: ; NFP0: vabs.f32 s -; CORTEXA8: test: +; CORTEXA8-LABEL: test: ; CORTEXA8: vadd.f32 [[D1:d[0-9]+]] ; CORTEXA8: vabs.f32 {{d[0-9]+}}, [[D1]] -; CORTEXA9: test: +; CORTEXA9-LABEL: test: ; CORTEXA9: vabs.f32 s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fadds.ll b/test/CodeGen/ARM/fadds.ll index c7e2f5d094..21219ce18e 100644 --- a/test/CodeGen/ARM/fadds.ll +++ b/test/CodeGen/ARM/fadds.ll @@ -11,17 +11,17 @@ entry: ret float %0 } -; VFP2: test: +; VFP2-LABEL: test: ; VFP2: vadd.f32 s -; NFP1: test: +; NFP1-LABEL: test: ; NFP1: vadd.f32 d -; NFP0: test: +; NFP0-LABEL: test: ; NFP0: vadd.f32 s -; CORTEXA8: test: +; CORTEXA8-LABEL: test: ; CORTEXA8: vadd.f32 s -; CORTEXA8U: test: +; CORTEXA8U-LABEL: test: ; CORTEXA8U: vadd.f32 d -; CORTEXA9: test: +; CORTEXA9-LABEL: test: ; CORTEXA9: vadd.f32 s diff --git a/test/CodeGen/ARM/fast-isel.ll b/test/CodeGen/ARM/fast-isel.ll index fd846bd97d..682fa35c12 100644 --- a/test/CodeGen/ARM/fast-isel.ll +++ b/test/CodeGen/ARM/fast-isel.ll @@ -27,16 +27,16 @@ br label %if.end if.end: ; preds = %if.then, %entry ret void -; ARM: test1: +; ARM-LABEL: test1: ; ARM: tst r0, #1 -; THUMB: test1: +; THUMB-LABEL: test1: ; THUMB: tst.w r0, #1 } ; Check some simple operations with immediates define void @test2(i32 %tmp, i32* %ptr) nounwind { -; THUMB: test2: -; ARM: test2: +; THUMB-LABEL: test2: +; ARM-LABEL: test2: b1: %a = add i32 %tmp, 4096 @@ -64,8 +64,8 @@ b3: } define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind { -; THUMB: test3: -; ARM: test3: +; THUMB-LABEL: test3: +; ARM-LABEL: test3: bb1: %a1 = trunc i32 %tmp to i16 diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll index 5511d24cb2..1de057208c 100644 --- a/test/CodeGen/ARM/fcopysign.ll +++ b/test/CodeGen/ARM/fcopysign.ll @@ -4,11 +4,11 @@ ; rdar://8984306 define float @test1(float %x, float %y) nounwind { entry: -; SOFT: test1: +; SOFT-LABEL: test1: ; SOFT: lsr r1, r1, #31 ; SOFT: bfi r0, r1, #31, #1 -; HARD: test1: +; HARD-LABEL: test1: ; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000 ; HARD: vbsl [[REG1]], d %0 = tail call float @copysignf(float %x, float %y) nounwind readnone @@ -17,11 +17,11 @@ entry: define double @test2(double %x, double %y) nounwind { entry: -; SOFT: test2: +; SOFT-LABEL: test2: ; SOFT: lsr r2, r3, #31 ; SOFT: bfi r1, r2, #31, #1 -; HARD: test2: +; HARD-LABEL: test2: ; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000 ; HARD: vshl.i64 [[REG2]], [[REG2]], #32 ; HARD: vbsl [[REG2]], d1, d0 @@ -31,7 +31,7 @@ entry: define double @test3(double %x, double %y, double %z) nounwind { entry: -; SOFT: test3: +; SOFT-LABEL: test3: ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32 ; SOFT: vbsl [[REG3]], @@ -43,7 +43,7 @@ entry: ; rdar://9287902 define float @test4() nounwind { entry: -; SOFT: test4: +; SOFT-LABEL: test4: ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32 diff --git a/test/CodeGen/ARM/fdivs.ll b/test/CodeGen/ARM/fdivs.ll index 8f13f395e0..a4fecfe145 100644 --- a/test/CodeGen/ARM/fdivs.ll +++ b/test/CodeGen/ARM/fdivs.ll @@ -9,15 +9,15 @@ entry: ret float %0 } -; VFP2: test: +; VFP2-LABEL: test: ; VFP2: vdiv.f32 s{{.}}, s{{.}}, s{{.}} -; NFP1: test: +; NFP1-LABEL: test: ; NFP1: vdiv.f32 s{{.}}, s{{.}}, s{{.}} -; NFP0: test: +; NFP0-LABEL: test: ; NFP0: vdiv.f32 s{{.}}, s{{.}}, s{{.}} -; CORTEXA8: test: +; CORTEXA8-LABEL: test: ; CORTEXA8: vdiv.f32 s{{.}}, s{{.}}, s{{.}} -; CORTEXA9: test: +; CORTEXA9-LABEL: test: ; CORTEXA9: vdiv.f32 s{{.}}, s{{.}}, s{{.}} diff --git a/test/CodeGen/ARM/fmuls.ll b/test/CodeGen/ARM/fmuls.ll index f5245c9463..d11f6bd1bd 100644 --- a/test/CodeGen/ARM/fmuls.ll +++ b/test/CodeGen/ARM/fmuls.ll @@ -11,19 +11,19 @@ entry: ret float %0 } -; VFP2: test: +; VFP2-LABEL: test: ; VFP2: vmul.f32 s -; NFP1: test: +; NFP1-LABEL: test: ; NFP1: vmul.f32 d -; NFP0: test: +; NFP0-LABEL: test: ; NFP0: vmul.f32 s -; CORTEXA8: test: +; CORTEXA8-LABEL: test: ; CORTEXA8: vmul.f32 s -; CORTEXA8U: test: +; CORTEXA8U-LABEL: test: ; CORTEXA8U: vmul.f32 d -; CORTEXA9: test: +; CORTEXA9-LABEL: test: ; CORTEXA9: vmul.f32 s ; VFP2: test2 diff --git a/test/CodeGen/ARM/fnegs.ll b/test/CodeGen/ARM/fnegs.ll index d84690ba4e..dc4c2e33e4 100644 --- a/test/CodeGen/ARM/fnegs.ll +++ b/test/CodeGen/ARM/fnegs.ll @@ -14,22 +14,22 @@ entry: %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] ret float %retval } -; VFP2: test1: +; VFP2-LABEL: test1: ; VFP2: vneg.f32 s{{.*}}, s{{.*}} -; NFP1: test1: +; NFP1-LABEL: test1: ; NFP1: vneg.f32 d{{.*}}, d{{.*}} -; NFP0: test1: +; NFP0-LABEL: test1: ; NFP0: vneg.f32 s{{.*}}, s{{.*}} -; CORTEXA8: test1: +; CORTEXA8-LABEL: test1: ; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} -; CORTEXA8U: test1: +; CORTEXA8U-LABEL: test1: ; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} -; CORTEXA9: test1: +; CORTEXA9-LABEL: test1: ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} define float @test2(float* %a) { @@ -41,21 +41,21 @@ entry: %retval = select i1 %3, float %1, float %0 ; <float> [#uses=1] ret float %retval } -; VFP2: test2: +; VFP2-LABEL: test2: ; VFP2: vneg.f32 s{{.*}}, s{{.*}} -; NFP1: test2: +; NFP1-LABEL: test2: ; NFP1: vneg.f32 d{{.*}}, d{{.*}} -; NFP0: test2: +; NFP0-LABEL: test2: ; NFP0: vneg.f32 s{{.*}}, s{{.*}} -; CORTEXA8: test2: +; CORTEXA8-LABEL: test2: ; CORTEXA8: vneg.f32 s{{.*}}, s{{.*}} -; CORTEXA8U: test2: +; CORTEXA8U-LABEL: test2: ; CORTEXA8U: vneg.f32 d{{.*}}, d{{.*}} -; CORTEXA9: test2: +; CORTEXA9-LABEL: test2: ; CORTEXA9: vneg.f32 s{{.*}}, s{{.*}} diff --git a/test/CodeGen/ARM/fp_convert.ll b/test/CodeGen/ARM/fp_convert.ll index 3c47eb580f..f0d910052a 100644 --- a/test/CodeGen/ARM/fp_convert.ll +++ b/test/CodeGen/ARM/fp_convert.ll @@ -6,9 +6,9 @@ ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2 define i32 @test1(float %a, float %b) { -; VFP2: test1: +; VFP2-LABEL: test1: ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}} -; NEON: test1: +; NEON-LABEL: test1: ; NEON: vadd.f32 [[D0:d[0-9]+]] ; NEON: vcvt.s32.f32 d0, [[D0]] entry: @@ -18,9 +18,9 @@ entry: } define i32 @test2(float %a, float %b) { -; VFP2: test2: +; VFP2-LABEL: test2: ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}} -; NEON: test2: +; NEON-LABEL: test2: ; NEON: vadd.f32 [[D0:d[0-9]+]] ; NEON: vcvt.u32.f32 d0, [[D0]] entry: @@ -30,9 +30,9 @@ entry: } define float @test3(i32 %a, i32 %b) { -; VFP2: test3: +; VFP2-LABEL: test3: ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}} -; NEON: test3: +; NEON-LABEL: test3: ; NEON: vcvt.f32.u32 d entry: %0 = add i32 %a, %b @@ -41,9 +41,9 @@ entry: } define float @test4(i32 %a, i32 %b) { -; VFP2: test4: +; VFP2-LABEL: test4: ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}} -; NEON: test4: +; NEON-LABEL: test4: ; NEON: vcvt.f32.s32 d entry: %0 = add i32 %a, %b diff --git a/test/CodeGen/ARM/ldr_post.ll b/test/CodeGen/ARM/ldr_post.ll index a6ca434483..f5ff7dda5e 100644 --- a/test/CodeGen/ARM/ldr_post.ll +++ b/test/CodeGen/ARM/ldr_post.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: ldr {{.*, \[.*]}}, -r2 ; CHECK-NOT: ldr define i32 @test1(i32 %a, i32 %b, i32 %c) { @@ -13,7 +13,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) { ret i32 %tmp5 } -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: ldr {{.*, \[.*\]}}, #-16 ; CHECK-NOT: ldr define i32 @test2(i32 %a, i32 %b) { diff --git a/test/CodeGen/ARM/ldr_pre.ll b/test/CodeGen/ARM/ldr_pre.ll index 6c40ad7326..82818272cf 100644 --- a/test/CodeGen/ARM/ldr_pre.ll +++ b/test/CodeGen/ARM/ldr_pre.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: ldr {{.*!}} ; CHECK-NOT: ldr define i32* @test1(i32* %X, i32* %dest) { @@ -11,7 +11,7 @@ define i32* @test1(i32* %X, i32* %dest) { ret i32* %Y } -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: ldr {{.*!}} ; CHECK-NOT: ldr define i32 @test2(i32 %a, i32 %b, i32 %c) { diff --git a/test/CodeGen/ARM/neon_vabs.ll b/test/CodeGen/ARM/neon_vabs.ll index bf2770b15b..76b6044239 100644 --- a/test/CodeGen/ARM/neon_vabs.ll +++ b/test/CodeGen/ARM/neon_vabs.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <4 x i32> @test1(<4 x i32> %a) nounwind { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: vabs.s32 q %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> @@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind { } define <4 x i32> @test2(<4 x i32> %a) nounwind { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: vabs.s32 q %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sge <4 x i32> %a, zeroinitializer @@ -19,7 +19,7 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind { } define <8 x i16> @test3(<8 x i16> %a) nounwind { -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: vabs.s16 q %tmp1neg = sub <8 x i16> zeroinitializer, %a %b = icmp sgt <8 x i16> %a, zeroinitializer @@ -28,7 +28,7 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind { } define <16 x i8> @test4(<16 x i8> %a) nounwind { -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: vabs.s8 q %tmp1neg = sub <16 x i8> zeroinitializer, %a %b = icmp slt <16 x i8> %a, zeroinitializer @@ -37,7 +37,7 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind { } define <4 x i32> @test5(<4 x i32> %a) nounwind { -; CHECK: test5: +; CHECK-LABEL: test5: ; CHECK: vabs.s32 q %tmp1neg = sub <4 x i32> zeroinitializer, %a %b = icmp sle <4 x i32> %a, zeroinitializer @@ -46,7 +46,7 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind { } define <2 x i32> @test6(<2 x i32> %a) nounwind { -; CHECK: test6: +; CHECK-LABEL: test6: ; CHECK: vabs.s32 d %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1> @@ -55,7 +55,7 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind { } define <2 x i32> @test7(<2 x i32> %a) nounwind { -; CHECK: test7: +; CHECK-LABEL: test7: ; CHECK: vabs.s32 d %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sge <2 x i32> %a, zeroinitializer @@ -64,7 +64,7 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind { } define <4 x i16> @test8(<4 x i16> %a) nounwind { -; CHECK: test8: +; CHECK-LABEL: test8: ; CHECK: vabs.s16 d %tmp1neg = sub <4 x i16> zeroinitializer, %a %b = icmp sgt <4 x i16> %a, zeroinitializer @@ -73,7 +73,7 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind { } define <8 x i8> @test9(<8 x i8> %a) nounwind { -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: vabs.s8 d %tmp1neg = sub <8 x i8> zeroinitializer, %a %b = icmp slt <8 x i8> %a, zeroinitializer @@ -82,7 +82,7 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind { } define <2 x i32> @test10(<2 x i32> %a) nounwind { -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: vabs.s32 d %tmp1neg = sub <2 x i32> zeroinitializer, %a %b = icmp sle <2 x i32> %a, zeroinitializer diff --git a/test/CodeGen/ARM/pack.ll b/test/CodeGen/ARM/pack.ll index f6cc75e04f..fbc115518f 100644 --- a/test/CodeGen/ARM/pack.ll +++ b/test/CodeGen/ARM/pack.ll @@ -90,7 +90,7 @@ define i32 @test8(i32 %X, i32 %Y) { ret i32 %tmp57 } -; CHECK: test9: +; CHECK-LABEL: test9: ; CHECK: pkhtb r0, r0, r1, asr #16 define i32 @test9(i32 %src1, i32 %src2) { entry: @@ -100,7 +100,7 @@ entry: ret i32 %tmp3 } -; CHECK: test10: +; CHECK-LABEL: test10: ; CHECK: pkhtb r0, r0, r1, asr #17 define i32 @test10(i32 %src1, i32 %src2) { entry: diff --git a/test/CodeGen/ARM/rev.ll b/test/CodeGen/ARM/rev.ll index 6bb6743119..6c380aee3d 100644 --- a/test/CodeGen/ARM/rev.ll +++ b/test/CodeGen/ARM/rev.ll @@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind { ; rdar://9147637 define i32 @test3(i16 zeroext %a) nounwind { entry: -; CHECK: test3: +; CHECK-LABEL: test3: ; CHECK: revsh r0, r0 %0 = tail call i16 @llvm.bswap.i16(i16 %a) %1 = sext i16 %0 to i32 @@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone define i32 @test4(i16 zeroext %a) nounwind { entry: -; CHECK: test4: +; CHECK-LABEL: test4: ; CHECK: revsh r0, r0 %conv = zext i16 %a to i32 %shr9 = lshr i16 %a, 8 diff --git a/test/CodeGen/ARM/shifter_operand.ll b/test/CodeGen/ARM/shifter_operand.ll index eb971ff72e..f14adcae66 100644 --- a/test/CodeGen/ARM/shifter_operand.ll +++ b/test/CodeGen/ARM/shifter_operand.ll @@ -4,10 +4,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) { -; A8: test1: +; A8-LABEL: test1: ; A8: add r0, r0, r1, lsl r2 -; A9: test1: +; A9-LABEL: test1: ; A9: add r0, r0, r1, lsl r2 %shift.upgrd.1 = zext i8 %sh to i32 %A = shl i32 %Y, %shift.upgrd.1 @@ -16,10 +16,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) { } define i32 @test2(i32 %X, i32 %Y, i8 %sh) { -; A8: test2: +; A8-LABEL: test2: ; A8: bic r0, r0, r1, asr r2 -; A9: test2: +; A9-LABEL: test2: ; A9: bic r0, r0, r1, asr r2 %shift.upgrd.2 = zext i8 %sh to i32 %A = ashr i32 %Y, %shift.upgrd.2 @@ -30,12 +30,12 @@ define i32 @test2(i32 %X, i32 %Y, i8 %sh) { define i32 @test3(i32 %base, i32 %base2, i32 %offset) { entry: -; A8: test3: +; A8-LABEL: test3: ; A8: ldr r0, [r0, r2, lsl #2] ; A8: ldr r1, [r1, r2, lsl #2] ; lsl #2 is free -; A9: test3: +; A9-LABEL: test3: ; A9: ldr r0, [r0, r2, lsl #2] ; A9: ldr r1, [r1, r2, lsl #2] %tmp1 = shl i32 %offset, 2 @@ -53,13 +53,13 @@ declare i8* @malloc(...) define fastcc void @test4(i16 %addr) nounwind { entry: -; A8: test4: +; A8-LABEL: test4: ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! ; A8: str [[REG]], [r0, r1, lsl #2] ; A8-NOT: str [[REG]], [r0] -; A9: test4: +; A9-LABEL: test4: ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2] ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]! ; A9: str [[REG]], [r0, r1, lsl #2] diff --git a/test/CodeGen/ARM/str_post.ll b/test/CodeGen/ARM/str_post.ll index 97916f169b..32e3b856c0 100644 --- a/test/CodeGen/ARM/str_post.ll +++ b/test/CodeGen/ARM/str_post.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm | FileCheck %s define i16 @test1(i32* %X, i16* %A) { -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK: strh {{.*}}[{{.*}}], #-4 %Y = load i32* %X ; <i32> [#uses=1] %tmp1 = trunc i32 %Y to i16 ; <i16> [#uses=1] @@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) { } define i32 @test2(i32* %X, i32* %A) { -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK: str {{.*}}[{{.*}}], %Y = load i32* %X ; <i32> [#uses=1] store i32 %Y, i32* %A diff --git a/test/CodeGen/ARM/swift-atomics.ll b/test/CodeGen/ARM/swift-atomics.ll index 9711a9f151..1d71815571 100644 --- a/test/CodeGen/ARM/swift-atomics.ll +++ b/test/CodeGen/ARM/swift-atomics.ll @@ -4,7 +4,7 @@ ; Release operations only need the store barrier provided by a "dmb ishst", define void @test_store_release(i32* %p, i32 %v) { -; CHECK: test_store_release: +; CHECK-LABEL: test_store_release: ; CHECK: dmb ishst ; CHECK: str @@ -17,7 +17,7 @@ define void @test_store_release(i32* %p, i32 %v) { ; followed by an acquire does not get reordered. In that case a "dmb ishst" is ; not adequate. define i32 @test_seq_cst(i32* %p, i32 %v) { -; CHECK: test_seq_cst: +; CHECK-LABEL: test_seq_cst: ; CHECK: dmb ishst ; CHECK: str ; CHECK: dmb {{ish$}} @@ -35,7 +35,7 @@ define i32 @test_seq_cst(i32* %p, i32 %v) { ; Also, pure acquire operations should definitely not have an ishst barrier. define i32 @test_acq(i32* %addr) { -; CHECK: test_acq: +; CHECK-LABEL: test_acq: ; CHECK: ldr ; CHECK: dmb {{ish$}} diff --git a/test/CodeGen/ARM/thumb1-varalloc.ll b/test/CodeGen/ARM/thumb1-varalloc.ll index aa88ae0c1a..e07e8aab77 100644 --- a/test/CodeGen/ARM/thumb1-varalloc.ll +++ b/test/CodeGen/ARM/thumb1-varalloc.ll @@ -39,4 +39,4 @@ bb3: } declare noalias i8* @strdup(i8* nocapture) nounwind -declare i32 @_called_func(i8*, i32*) nounwind
\ No newline at end of file +declare i32 @_called_func(i8*, i32*) nounwind diff --git a/test/CodeGen/ARM/va_arg.ll b/test/CodeGen/ARM/va_arg.ll index af477b40a7..f18b498228 100644 --- a/test/CodeGen/ARM/va_arg.ll +++ b/test/CodeGen/ARM/va_arg.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s ; Test that we correctly align elements when using va_arg -; CHECK: test1: +; CHECK-LABEL: test1: ; CHECK-NOT: bfc ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 ; CHECK: bfc [[REG]], #0, #3 @@ -17,7 +17,7 @@ entry: ret i64 %0 } -; CHECK: test2: +; CHECK-LABEL: test2: ; CHECK-NOT: bfc ; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 ; CHECK: bfc [[REG]], #0, #3 diff --git a/test/CodeGen/ARM/vbsl.ll b/test/CodeGen/ARM/vbsl.ll index 750fb0de53..56e40ebc9a 100644 --- a/test/CodeGen/ARM/vbsl.ll +++ b/test/CodeGen/ARM/vbsl.ll @@ -163,28 +163,28 @@ define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind } define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp { -; CHECK: test_vbsl_s64: +; CHECK-LABEL: test_vbsl_s64: ; CHECK: vbsl d %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind ret <1 x i64> %vbsl3.i } define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp { -; CHECK: test_vbsl_u64: +; CHECK-LABEL: test_vbsl_u64: ; CHECK: vbsl d %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind ret <1 x i64> %vbsl3.i } define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp { -; CHECK: test_vbslq_s64: +; CHECK-LABEL: test_vbslq_s64: ; CHECK: vbsl q %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind ret <2 x i64> %vbsl3.i } define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp { -; CHECK: test_vbslq_u64: +; CHECK-LABEL: test_vbslq_u64: ; CHECK: vbsl q %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind ret <2 x i64> %vbsl3.i diff --git a/test/CodeGen/ARM/vext.ll b/test/CodeGen/ARM/vext.ll index ef22a3ba53..5555a4759b 100644 --- a/test/CodeGen/ARM/vext.ll +++ b/test/CodeGen/ARM/vext.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: test_vextd: +;CHECK-LABEL: test_vextd: ;CHECK: vext %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -10,7 +10,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: test_vextRd: +;CHECK-LABEL: test_vextRd: ;CHECK: vext %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -19,7 +19,7 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: test_vextq: +;CHECK-LABEL: test_vextq: ;CHECK: vext %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -28,7 +28,7 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: test_vextRq: +;CHECK-LABEL: test_vextRq: ;CHECK: vext %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -37,7 +37,7 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { -;CHECK: test_vextd16: +;CHECK-LABEL: test_vextd16: ;CHECK: vext %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B @@ -46,7 +46,7 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { -;CHECK: test_vextq32: +;CHECK-LABEL: test_vextq32: ;CHECK: vext %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B @@ -57,7 +57,7 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind { ; Undef shuffle indices should not prevent matching to VEXT: define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { -;CHECK: test_vextd_undef: +;CHECK-LABEL: test_vextd_undef: ;CHECK: vext %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B @@ -66,7 +66,7 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { -;CHECK: test_vextRq_undef: +;CHECK-LABEL: test_vextRq_undef: ;CHECK: vext %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B @@ -75,7 +75,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind { -;CHECK: test_vextq_undef_op2: +;CHECK-LABEL: test_vextq_undef_op2: ;CHECK: vext entry: %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1> @@ -83,7 +83,7 @@ entry: } define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind { -;CHECK: test_vextd_undef_op2: +;CHECK-LABEL: test_vextd_undef_op2: ;CHECK: vext entry: %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1> @@ -92,7 +92,7 @@ entry: define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind { -;CHECK: test_vextq_undef_op2_undef: +;CHECK-LABEL: test_vextq_undef_op2_undef: ;CHECK: vext entry: %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1> @@ -100,7 +100,7 @@ entry: } define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind { -;CHECK: test_vextd_undef_op2_undef: +;CHECK-LABEL: test_vextd_undef_op2_undef: ;CHECK: vext entry: %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1> @@ -114,7 +114,7 @@ entry: ; Also checks interleaving of sources is handled correctly. ; Essence: a vext is used on %A and something saner than stack load/store for final result. define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: test_interleaved: +;CHECK-LABEL: test_interleaved: ;CHECK: vext.16 ;CHECK-NOT: vext.16 ;CHECK: vzip.16 @@ -126,7 +126,7 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; An undef in the shuffle list should still be optimizable define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: test_undef: +;CHECK-LABEL: test_undef: ;CHECK: vzip.16 %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B @@ -138,7 +138,7 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; Use illegal <32 x i16> type to produce such a shuffle after legalizing types. ; Try to look for fallback to by-element inserts. define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { -;CHECK: test_multisource: +;CHECK-LABEL: test_multisource: ;CHECK: vmov.16 [[REG:d[0-9]+]][0] ;CHECK: vmov.16 [[REG]][1] ;CHECK: vmov.16 [[REG]][2] @@ -151,7 +151,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind { ; We don't handle shuffles using more than half of a 128-bit vector. ; Again, test for fallback to by-element inserts. define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { -;CHECK: test_largespan: +;CHECK-LABEL: test_largespan: ;CHECK: vmov.16 [[REG:d[0-9]+]][0] ;CHECK: vmov.16 [[REG]][1] ;CHECK: vmov.16 [[REG]][2] @@ -165,7 +165,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind { ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite ; lowering loop can result otherwise). define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { -;CHECK: test_illegal: +;CHECK-LABEL: test_illegal: ;CHECK: vmov.16 [[REG:d[0-9]+]][0] ;CHECK: vmov.16 [[REG]][1] ;CHECK: vmov.16 [[REG]][2] @@ -183,7 +183,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind { ; PR11129 ; Make sure this doesn't crash define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind { -; CHECK: test_elem_mismatch: +; CHECK-LABEL: test_elem_mismatch: ; CHECK: vstr %tmp0 = load <2 x i64>* %src, align 16 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32> diff --git a/test/CodeGen/ARM/vfp.ll b/test/CodeGen/ARM/vfp.ll index 7a4b34f4a3..5d2943cbfd 100644 --- a/test/CodeGen/ARM/vfp.ll +++ b/test/CodeGen/ARM/vfp.ll @@ -14,7 +14,7 @@ declare float @fabsf(float) declare double @fabs(double) define void @test_abs(float* %P, double* %D) { -;CHECK: test_abs: +;CHECK-LABEL: test_abs: %a = load float* %P ; <float> [#uses=1] ;CHECK: vabs.f32 %b = call float @fabsf( float %a ) readnone ; <float> [#uses=1] @@ -27,7 +27,7 @@ define void @test_abs(float* %P, double* %D) { } define void @test_add(float* %P, double* %D) { -;CHECK: test_add: +;CHECK-LABEL: test_add: %a = load float* %P ; <float> [#uses=2] %b = fadd float %a, %a ; <float> [#uses=1] store float %b, float* %P @@ -38,7 +38,7 @@ define void @test_add(float* %P, double* %D) { } define void @test_ext_round(float* %P, double* %D) { -;CHECK: test_ext_round: +;CHECK-LABEL: test_ext_round: %a = load float* %P ; <float> [#uses=1] ;CHECK: vcvt.f64.f32 ;CHECK: vcvt.f32.f64 @@ -51,7 +51,7 @@ define void @test_ext_round(float* %P, double* %D) { } define void @test_fma(float* %P1, float* %P2, float* %P3) { -;CHECK: test_fma: +;CHECK-LABEL: test_fma: %a1 = load float* %P1 ; <float> [#uses=1] %a2 = load float* %P2 ; <float> [#uses=1] %a3 = load float* %P3 ; <float> [#uses=1] @@ -63,7 +63,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) { } define i32 @test_ftoi(float* %P1) { -;CHECK: test_ftoi: +;CHECK-LABEL: test_ftoi: %a1 = load float* %P1 ; <float> [#uses=1] ;CHECK: vcvt.s32.f32 %b1 = fptosi float %a1 to i32 ; <i32> [#uses=1] @@ -71,7 +71,7 @@ define i32 @test_ftoi(float* %P1) { } define i32 @test_ftou(float* %P1) { -;CHECK: test_ftou: +;CHECK-LABEL: test_ftou: %a1 = load float* %P1 ; <float> [#uses=1] ;CHECK: vcvt.u32.f32 %b1 = fptoui float %a1 to i32 ; <i32> [#uses=1] @@ -79,7 +79,7 @@ define i32 @test_ftou(float* %P1) { } define i32 @test_dtoi(double* %P1) { -;CHECK: test_dtoi: +;CHECK-LABEL: test_dtoi: %a1 = load double* %P1 ; <double> [#uses=1] ;CHECK: vcvt.s32.f64 %b1 = fptosi double %a1 to i32 ; <i32> [#uses=1] @@ -87,7 +87,7 @@ define i32 @test_dtoi(double* %P1) { } define i32 @test_dtou(double* %P1) { -;CHECK: test_dtou: +;CHECK-LABEL: test_dtou: %a1 = load double* %P1 ; <double> [#uses=1] ;CHECK: vcvt.u32.f64 %b1 = fptoui double %a1 to i32 ; <i32> [#uses=1] @@ -95,7 +95,7 @@ define i32 @test_dtou(double* %P1) { } define void @test_utod(double* %P1, i32 %X) { -;CHECK: test_utod: +;CHECK-LABEL: test_utod: ;CHECK: vcvt.f64.u32 %b1 = uitofp i32 %X to double ; <double> [#uses=1] store double %b1, double* %P1 @@ -103,7 +103,7 @@ define void @test_utod(double* %P1, i32 %X) { } define void @test_utod2(double* %P1, i8 %X) { -;CHECK: test_utod2: +;CHECK-LABEL: test_utod2: ;CHECK: vcvt.f64.u32 %b1 = uitofp i8 %X to double ; <double> [#uses=1] store double %b1, double* %P1 @@ -111,7 +111,7 @@ define void @test_utod2(double* %P1, i8 %X) { } define void @test_cmp(float* %glob, i32 %X) { -;CHECK: test_cmp: +;CHECK-LABEL: test_cmp: entry: %tmp = load float* %glob ; <float> [#uses=2] %tmp3 = getelementptr float* %glob, i32 2 ; <float*> [#uses=1] @@ -139,7 +139,7 @@ declare i32 @bar(...) declare i32 @baz(...) define void @test_cmpfp0(float* %glob, i32 %X) { -;CHECK: test_cmpfp0: +;CHECK-LABEL: test_cmpfp0: entry: %tmp = load float* %glob ; <float> [#uses=1] ;CHECK: vcmpe.f32 diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll index c9ce3b7450..806ec95df0 100644 --- a/test/CodeGen/ARM/vget_lane.ll +++ b/test/CodeGen/ARM/vget_lane.ll @@ -207,7 +207,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind { } define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind { -;CHECK: test_vset_lanef32: +;CHECK-LABEL: test_vset_lanef32: ;CHECK: vmov.f32 s3, s0 ;CHECK: vmov.f64 d0, d1 entry: diff --git a/test/CodeGen/ARM/vmul.ll b/test/CodeGen/ARM/vmul.ll index eb5ad8f0c3..aa3cda0707 100644 --- a/test/CodeGen/ARM/vmul.ll +++ b/test/CodeGen/ARM/vmul.ll @@ -95,7 +95,7 @@ declare <16 x i8> @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind rea define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone { entry: -; CHECK: test_vmul_lanef32: +; CHECK-LABEL: test_vmul_lanef32: ; CHECK: vmul.f32 d0, d0, d1[0] %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1] %1 = fmul <2 x float> %0, %arg0_float32x2_t ; <<2 x float>> [#uses=1] @@ -104,7 +104,7 @@ entry: define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { entry: -; CHECK: test_vmul_lanes16: +; CHECK-LABEL: test_vmul_lanes16: ; CHECK: vmul.i16 d0, d0, d1[1] %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$ %1 = mul <4 x i16> %0, %arg0_int16x4_t ; <<4 x i16>> [#uses=1] @@ -113,7 +113,7 @@ entry: define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { entry: -; CHECK: test_vmul_lanes32: +; CHECK-LABEL: test_vmul_lanes32: ; CHECK: vmul.i32 d0, d0, d1[1] %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1] %1 = mul <2 x i32> %0, %arg0_int32x2_t ; <<2 x i32>> [#uses=1] @@ -122,7 +122,7 @@ entry: define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone { entry: -; CHECK: test_vmulQ_lanef32: +; CHECK-LABEL: test_vmulQ_lanef32: ; CHECK: vmul.f32 q0, q0, d2[1] %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$ %1 = fmul <4 x float> %0, %arg0_float32x4_t ; <<4 x float>> [#uses=1] @@ -131,7 +131,7 @@ entry: define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone { entry: -; CHECK: test_vmulQ_lanes16: +; CHECK-LABEL: test_vmulQ_lanes16: ; CHECK: vmul.i16 q0, q0, d2[1] %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %1 = mul <8 x i16> %0, %arg0_int16x8_t ; <<8 x i16>> [#uses=1] @@ -140,7 +140,7 @@ entry: define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone { entry: -; CHECK: test_vmulQ_lanes32: +; CHECK-LABEL: test_vmulQ_lanes32: ; CHECK: vmul.i32 q0, q0, d2[1] %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$ %1 = mul <4 x i32> %0, %arg0_int32x4_t ; <<4 x i32>> [#uses=1] diff --git a/test/CodeGen/ARM/vrev.ll b/test/CodeGen/ARM/vrev.ll index 122ec0357f..b6da694e18 100644 --- a/test/CodeGen/ARM/vrev.ll +++ b/test/CodeGen/ARM/vrev.ll @@ -1,7 +1,7 @@ ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { -;CHECK: test_vrev64D8: +;CHECK-LABEL: test_vrev64D8: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> @@ -9,7 +9,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind { } define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { -;CHECK: test_vrev64D16: +;CHECK-LABEL: test_vrev64D16: ;CHECK: vrev64.16 %tmp1 = load <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0> @@ -17,7 +17,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind { } define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { -;CHECK: test_vrev64D32: +;CHECK-LABEL: test_vrev64D32: ;CHECK: vrev64.32 %tmp1 = load <2 x i32>* %A %tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0> @@ -25,7 +25,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind { } define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { -;CHECK: test_vrev64Df: +;CHECK-LABEL: test_vrev64Df: ;CHECK: vrev64.32 %tmp1 = load <2 x float>* %A %tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0> @@ -33,7 +33,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind { } define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { -;CHECK: test_vrev64Q8: +;CHECK-LABEL: test_vrev64Q8: ;CHECK: vrev64.8 %tmp1 = load <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8> @@ -41,7 +41,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind { } define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { -;CHECK: test_vrev64Q16: +;CHECK-LABEL: test_vrev64Q16: ;CHECK: vrev64.16 %tmp1 = load <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> @@ -49,7 +49,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind { } define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { -;CHECK: test_vrev64Q32: +;CHECK-LABEL: test_vrev64Q32: ;CHECK: vrev64.32 %tmp1 = load <4 x i32>* %A %tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> @@ -57,7 +57,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind { } define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { -;CHECK: test_vrev64Qf: +;CHECK-LABEL: test_vrev64Qf: ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %A %tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> @@ -65,7 +65,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind { } define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { -;CHECK: test_vrev32D8: +;CHECK-LABEL: test_vrev32D8: ;CHECK: vrev32.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4> @@ -73,7 +73,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind { } define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { -;CHECK: test_vrev32D16: +;CHECK-LABEL: test_vrev32D16: ;CHECK: vrev32.16 %tmp1 = load <4 x i16>* %A %tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2> @@ -81,7 +81,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind { } define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { -;CHECK: test_vrev32Q8: +;CHECK-LABEL: test_vrev32Q8: ;CHECK: vrev32.8 %tmp1 = load <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12> @@ -89,7 +89,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind { } define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { -;CHECK: test_vrev32Q16: +;CHECK-LABEL: test_vrev32Q16: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> @@ -97,7 +97,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind { } define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { -;CHECK: test_vrev16D8: +;CHECK-LABEL: test_vrev16D8: ;CHECK: vrev16.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6> @@ -105,7 +105,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind { } define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { -;CHECK: test_vrev16Q8: +;CHECK-LABEL: test_vrev16Q8: ;CHECK: vrev16.8 %tmp1 = load <16 x i8>* %A %tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14> @@ -115,7 +115,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind { ; Undef shuffle indices should not prevent matching to VREV: define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { -;CHECK: test_vrev64D8_undef: +;CHECK-LABEL: test_vrev64D8_undef: ;CHECK: vrev64.8 %tmp1 = load <8 x i8>* %A %tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0> @@ -123,7 +123,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind { } define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { -;CHECK: test_vrev32Q16_undef: +;CHECK-LABEL: test_vrev32Q16_undef: ;CHECK: vrev32.16 %tmp1 = load <8 x i16>* %A %tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef> @@ -133,7 +133,7 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind { ; A vcombine feeding a VREV should not obscure things. Radar 8597007. define void @test_with_vcombine(<4 x float>* %v) nounwind { -;CHECK: test_with_vcombine: +;CHECK-LABEL: test_with_vcombine: ;CHECK-NOT: vext ;CHECK: vrev64.32 %tmp1 = load <4 x float>* %v, align 16 @@ -151,7 +151,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind { ; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored ; to <2 x i16> when stored to memory. define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { -; CHECK: test_vrev64: +; CHECK-LABEL: test_vrev64: ; CHECK: vst1.32 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* |