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authorAndrew Trick <atrick@apple.com>2012-03-21 04:12:19 +0000
committerAndrew Trick <atrick@apple.com>2012-03-21 04:12:19 +0000
commitc6a19dd7fbfce7668920daff2845abb2dd73a134 (patch)
treee1459b804aeda14bad6d00ee8126d9df1d5f8c7e /test/CodeGen/Generic
parentf70af52a8fc735a84aa8d63b84dd56abd0b9e77c (diff)
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misched: beginning to add unit tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153163 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Generic')
-rw-r--r--test/CodeGen/Generic/misched.ll20
1 files changed, 20 insertions, 0 deletions
diff --git a/test/CodeGen/Generic/misched.ll b/test/CodeGen/Generic/misched.ll
new file mode 100644
index 0000000000..6ab1dd24a3
--- /dev/null
+++ b/test/CodeGen/Generic/misched.ll
@@ -0,0 +1,20 @@
+; RUN: llc -enable-misched -misched=shuffle -misched-bottomup < %s
+; XFAIL: *
+;
+; Interesting MachineScheduler cases.
+
+declare void @llvm.memcpy.p0i8.p0i8.i64(i8* nocapture, i8* nocapture, i64, i32, i1) nounwind
+
+; From oggenc.
+; After coalescing, we have a dead superreg (RAX) definition.
+define fastcc void @_preextrapolate_helper() nounwind uwtable ssp {
+entry:
+ br i1 undef, label %for.cond.preheader, label %if.end
+
+for.cond.preheader: ; preds = %entry
+ call void @llvm.memcpy.p0i8.p0i8.i64(i8* undef, i8* null, i64 128, i32 4, i1 false) nounwind
+ unreachable
+
+if.end: ; preds = %entry
+ ret void
+}