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| author | Sirish Pande <spande@codeaurora.org> | 2012-04-12 21:06:54 +0000 |
|---|---|---|
| committer | Sirish Pande <spande@codeaurora.org> | 2012-04-12 21:06:54 +0000 |
| commit | 2f69e4cf32ca2a120e0008f50acd5e6f40ff14b6 (patch) | |
| tree | 9e7f2aae99e43403a8db1576d88d39dc5cb803c0 /test/CodeGen/Hexagon/struct_args.ll | |
| parent | d1a87a68064e0b9af3b71b681286954f861bb1b3 (diff) | |
| download | llvm-2f69e4cf32ca2a120e0008f50acd5e6f40ff14b6.tar.gz llvm-2f69e4cf32ca2a120e0008f50acd5e6f40ff14b6.tar.bz2 llvm-2f69e4cf32ca2a120e0008f50acd5e6f40ff14b6.tar.xz | |
Disable Hexagon test temporarily.
There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA).
This assert needs to addressed for post RA scheduler. Until that assert is addressed,
any passes that uses post ra scheduler will fail. So, I am temporarily disabling the
hexagon tests until that fix is in.
The assert is as follows:
assert(!MI->isTerminator() && !MI->isLabel() &&
"Cannot schedule terminators or labels!");
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154617 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon/struct_args.ll')
| -rw-r--r-- | test/CodeGen/Hexagon/struct_args.ll | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/test/CodeGen/Hexagon/struct_args.ll b/test/CodeGen/Hexagon/struct_args.ll index cc409db562..2c962d0961 100644 --- a/test/CodeGen/Hexagon/struct_args.ll +++ b/test/CodeGen/Hexagon/struct_args.ll @@ -1,4 +1,5 @@ -; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; RUN: true +; DISABLED: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s ; CHECK: r1:0 = or(r{{[0-9]}}:{{[0-9]}}, r{{[0-9]}}:{{[0-9]}}) %struct.small = type { i32, i32 } |