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| author | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-05 18:15:34 +0000 |
|---|---|---|
| committer | Jyotsna Verma <jverma@codeaurora.org> | 2013-02-05 18:15:34 +0000 |
| commit | 691c365aad62779c4fec9f06dbd57be31e9446f8 (patch) | |
| tree | ba3cb2edc9789ed533fe7c535e3ccb6a5474f8b3 /test/CodeGen/Hexagon | |
| parent | 294014e1585ef5e0c1bf17a9cf79039ce662b64f (diff) | |
| download | llvm-691c365aad62779c4fec9f06dbd57be31e9446f8.tar.gz llvm-691c365aad62779c4fec9f06dbd57be31e9446f8.tar.bz2 llvm-691c365aad62779c4fec9f06dbd57be31e9446f8.tar.xz | |
Hexagon: Use multiclass for absolute addressing mode stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/Hexagon')
| -rw-r--r-- | test/CodeGen/Hexagon/absaddr-store.ll | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/test/CodeGen/Hexagon/absaddr-store.ll b/test/CodeGen/Hexagon/absaddr-store.ll new file mode 100644 index 0000000000..5c2554df8a --- /dev/null +++ b/test/CodeGen/Hexagon/absaddr-store.ll @@ -0,0 +1,46 @@ +; RUN: llc -march=hexagon -mcpu=hexagonv4 < %s | FileCheck %s +; Check that we generate load instructions with absolute addressing mode. + +@a = external global i32 +@b = external global i8 +@c = external global i16 +@d = external global i64 + +define zeroext i8 @absStoreByte() nounwind { +; CHECK: memb(##b){{ *}}={{ *}}r{{[0-9]+}} +entry: + %0 = load i8* @b, align 1 + %conv = zext i8 %0 to i32 + %mul = mul nsw i32 100, %conv + %conv1 = trunc i32 %mul to i8 + store i8 %conv1, i8* @b, align 1 + ret i8 %conv1 +} + +define signext i16 @absStoreHalf() nounwind { +; CHECK: memh(##c){{ *}}={{ *}}r{{[0-9]+}} +entry: + %0 = load i16* @c, align 2 + %conv = sext i16 %0 to i32 + %mul = mul nsw i32 100, %conv + %conv1 = trunc i32 %mul to i16 + store i16 %conv1, i16* @c, align 2 + ret i16 %conv1 +} + +define i32 @absStoreWord() nounwind { +; CHECK: memw(##a){{ *}}={{ *}}r{{[0-9]+}} +entry: + %0 = load i32* @a, align 4 + %mul = mul nsw i32 100, %0 + store i32 %mul, i32* @a, align 4 + ret i32 %mul +} + +define void @absStoreDouble() nounwind { +; CHECK: memd(##d){{ *}}={{ *}}r{{[0-9]+}}:{{[0-9]+}} +entry: + store i64 100, i64* @d, align 8 + ret void +} + |